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Merge branch '2024-02-06-assorted-fixes'

Browse source 
A number of assorted fixes
This commit is contained in:
Tom Rini 2024-02-07 09:47:47 -05:00
commit 0101a2ffe1
11 changed files with 64 additions and 69 deletions
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2
arch/arm/Kconfig
View file

@ -678,7 +678,7 @@ config ARCH_BCMBCA
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
select CPU_V7A
select PL011_SERIAL
select PL01X_SERIAL
config TARGET_BCMNS
bool "Support Broadcom Northstar"

2
arch/arm/dts/nuvoton-common-npcm8xx.dtsi
View file

@ -5,6 +5,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/nuvoton,npcm8xx-reset.h>
/ {
#address-cells = <2>;
@ -152,6 +153,7 @@
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_APB5>;
clock-names = "clk_apb5";
resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_PSPI2>;
status = "disabled";
};

71
arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
View file

@ -20,34 +20,7 @@
compatible = "nuvoton,npcm845-reset", "syscon",
"simple-mfd";
reg = <0x0 0xf0801000 0x0 0xC4>;
rstc1: reset-controller1 {
compatible = "syscon-reset";
#reset-cells = <1>;
regmap = <&rstc>;
offset = <NPCM8XX_RESET_IPSRST1>;
mask = <0xFFFFFFFF>;
};
rstc2: reset-controller2 {
compatible = "syscon-reset";
#reset-cells = <1>;
regmap = <&rstc>;
offset = <NPCM8XX_RESET_IPSRST2>;
mask = <0xFFFFFFFF>;
};
rstc3: reset-controller3 {
compatible = "syscon-reset";
#reset-cells = <1>;
regmap = <&rstc>;
offset = <NPCM8XX_RESET_IPSRST3>;
mask = <0xFFFFFFFF>;
};
rstc4: reset-controller4 {
compatible = "syscon-reset";
#reset-cells = <1>;
regmap = <&rstc>;
offset = <NPCM8XX_RESET_IPSRST4>;
mask = <0xFFFFFFFF>;
};
#reset-cells = <2>;
};
clk: clock-controller@f0801000 {
@ -70,7 +43,7 @@
clock-names = "stmmaceth";
pinctrl-names = "default";
pinctrl-0 = <&rg1mdio_pins>;
resets = <&rstc2 NPCM8XX_RESET_GMAC1>;
resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_GMAC1>;
status = "disabled";
};
@ -85,7 +58,7 @@
pinctrl-names = "default";
pinctrl-0 = <&rg2_pins
&rg2mdio_pins>;
resets = <&rstc2 NPCM8XX_RESET_GMAC2>;
resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_GMAC2>;
status = "disabled";
};
@ -101,7 +74,7 @@
pinctrl-0 = <&r1_pins
&r1err_pins
&r1md_pins>;
resets = <&rstc1 NPCM8XX_RESET_GMAC3>;
resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_GMAC3>;
status = "disabled";
};
@ -117,7 +90,7 @@
pinctrl-0 = <&r2_pins
&r2err_pins
&r2md_pins>;
resets = <&rstc1 NPCM8XX_RESET_GMAC4>;
resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_GMAC4>;
status = "disabled";
};
@ -125,7 +98,7 @@
compatible = "nuvoton,npcm845-ehci";
reg = <0x0 0xf0828100 0x0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstc2 NPCM8XX_RESET_USBH1>;
resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_USBH1>;
status = "disabled";
};
@ -133,21 +106,21 @@
compatible = "nuvoton,npcm845-ehci";
reg = <0x0 0xf082a100 0x0 0x1000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstc4 NPCM8XX_RESET_USBH2>;
resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBH2>;
status = "disabled";
};
ohci1: usb@f0829000 {
compatible = "nuvoton,npcm845-ohci";
reg = <0x0 0xF0829000 0x0 0x1000>;
resets = <&rstc2 NPCM8XX_RESET_USBH1>;
resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_USBH1>;
status = "disabled";
};
ohci2: usb@f082b000 {
compatible = "nuvoton,npcm845-ohci";
reg = <0x0 0xF082B000 0x0 0x1000>;
resets = <&rstc4 NPCM8XX_RESET_USBH2>;
resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBH2>;
status = "disabled";
};
@ -160,21 +133,21 @@
compatible = "nuvoton,npcm845-usb-phy";
#phy-cells = <1>;
reg = <1>;
resets = <&rstc3 NPCM8XX_RESET_USBPHY1>;
resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_USBPHY1>;
status = "disabled";
};
usbphy2: usbphy@2 {
compatible = "nuvoton,npcm845-usb-phy";
#phy-cells = <1>;
reg = <2>;
resets = <&rstc3 NPCM8XX_RESET_USBPHY2>;
resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_USBPHY2>;
status = "disabled";
};
usbphy3: usbphy@3 {
compatible = "nuvoton,npcm845-usb-phy";
#phy-cells = <1>;
reg = <3>;
resets = <&rstc4 NPCM8XX_RESET_USBPHY3>;
resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBPHY3>;
status = "disabled";
};
};
@ -186,7 +159,7 @@
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc3 NPCM8XX_RESET_UDC0>;
resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC0>;
status = "disable";
};
@ -197,7 +170,7 @@
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc1 NPCM8XX_RESET_UDC1>;
resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC1>;
status = "disable";
};
@ -208,7 +181,7 @@
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc1 NPCM8XX_RESET_UDC2>;
resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC2>;
status = "disable";
};
@ -219,7 +192,7 @@
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc1 NPCM8XX_RESET_UDC3>;
resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC3>;
status = "disable";
};
@ -230,7 +203,7 @@
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc1 NPCM8XX_RESET_UDC4>;
resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC4>;
status = "disable";
};
@ -241,7 +214,7 @@
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc1 NPCM8XX_RESET_UDC5>;
resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC5>;
status = "disable";
};
@ -252,7 +225,7 @@
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc1 NPCM8XX_RESET_UDC6>;
resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC6>;
status = "disable";
};
@ -263,7 +236,7 @@
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc3 NPCM8XX_RESET_UDC7>;
resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC7>;
status = "disable";
};
@ -274,7 +247,7 @@
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc3 NPCM8XX_RESET_UDC8>;
resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC8>;
status = "disable";
};
@ -285,7 +258,7 @@
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc3 NPCM8XX_RESET_UDC9>;
resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC9>;
status = "disable";
};

4
arch/arm/dts/vexpress-v2p-ca9.dts
View file

@ -20,7 +20,9 @@
#address-cells = <1>;
#size-cells = <1>;
chosen { };
chosen {
stdout-path = &v2m_serial0;
};
aliases {
serial0 = &v2m_serial0;

2
arch/arm/mach-k3/j721s2_init.c
View file

@ -228,7 +228,7 @@ void k3_mem_init(void)
panic("DRAM 0 init failed: %d\n", ret);
ret = uclass_next_device_err(&dev);
if (ret)
if (ret && ret != -ENODEV)
panic("DRAM 1 init failed: %d\n", ret);
}
spl_enable_cache();

5
common/event.c
View file

@ -56,7 +56,10 @@ _Static_assert(ARRAY_SIZE(type_name) == EVT_COUNT, "event type_name size");
const char *event_type_name(enum event_t type)
{
#if CONFIG_IS_ENABLED(EVENT_DEBUG)
return type_name[type];
if (type < ARRAY_SIZE(type_name))
return type_name[type];
else
return "(unknown)";
#else
return "(unknown)";
#endif

3
configs/vexpress_ca9x4_defconfig
View file

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_TARGET_VEXPRESS_CA9X4=y
CONFIG_TEXT_BASE=0x60800000
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60000f10
@ -41,6 +41,7 @@ CONFIG_ARM_PL180_MMCI=y
CONFIG_SYS_MMC_MAX_BLK_COUNT=127
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SERIAL=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y
CONFIG_FLASH_SHOW_PROGRESS=0

1
drivers/block/host_dev.c
View file

@ -61,6 +61,7 @@ static int host_sb_attach_file(struct udevice *dev, const char *filename)
if (size % desc->blksz) {
printf("The size of host backing file '%s' is not multiple of "
"the device block size\n", filename);
ret = -EINVAL;
goto err_fname;
}
desc->lba = size / desc->blksz;

11
drivers/dma/ti/k3-udma.c
View file

@ -876,13 +876,20 @@ static int udma_alloc_tx_resources(struct udma_chan *uc)
{
struct k3_nav_ring_cfg ring_cfg;
struct udma_dev *ud = uc->ud;
int ret;
struct udma_tchan *tchan;
int ring_idx, ret;
ret = udma_get_tchan(uc);
if (ret)
return ret;
ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, uc->tchan->id, -1,
tchan = uc->tchan;
if (tchan->tflow_id >= 0)
ring_idx = tchan->tflow_id;
else
ring_idx = ud->bchan_cnt + tchan->id;
ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1,
&uc->tchan->t_ring,
&uc->tchan->tc_ring);
if (ret) {

18
drivers/firmware/ti_sci.c
View file

@ -236,21 +236,27 @@ static int ti_sci_do_xfer(struct ti_sci_info *info,
{
struct k3_sec_proxy_msg *msg = &xfer->tx_message;
u8 secure_buf[info->desc->max_msg_size];
struct ti_sci_secure_msg_hdr secure_hdr;
struct ti_sci_secure_msg_hdr *secure_hdr = (struct ti_sci_secure_msg_hdr *)secure_buf;
int ret;
/*
* The reason why we need the is_secure code is because of boot R5.
* boot R5 starts off in "secure mode" when it hands off from Boot
* ROM over to the Secondary bootloader. The initial set of calls
* we have to make need to be on a secure pipe.
*/
if (info->is_secure) {
/* ToDo: get checksum of the entire message */
secure_hdr.checksum = 0;
secure_hdr.reserved = 0;
memcpy(&secure_buf[sizeof(secure_hdr)], xfer->tx_message.buf,
secure_hdr->checksum = 0;
secure_hdr->reserved = 0;
memcpy(&secure_buf[sizeof(*secure_hdr)], xfer->tx_message.buf,
xfer->tx_message.len);
xfer->tx_message.buf = (u32 *)secure_buf;
xfer->tx_message.len += sizeof(secure_hdr);
xfer->tx_message.len += sizeof(*secure_hdr);
if (xfer->rx_len)
xfer->rx_len += sizeof(secure_hdr);
xfer->rx_len += sizeof(*secure_hdr);
}
/* Send the message */

14
scripts/gen_compile_commands.py
View file

@ -21,7 +21,7 @@ _DEFAULT_OUTPUT = 'compile_commands.json'
_DEFAULT_LOG_LEVEL = 'WARNING'
_FILENAME_PATTERN = r'^\..*\.cmd$'
_LINE_PATTERN = r'^cmd_[^ ]*\.o := (.* )([^ ]*\.c) *(;|$)'
_LINE_PATTERN = r'^(saved)?cmd_[^ ]*\.o := (?P<command_prefix>.* )(?P<file_path>[^ ]*\.[cS]) *(;|$)'
_VALID_LOG_LEVELS = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL']
# The tools/ directory adopts a different build system, and produces .cmd
# files in a different format. Do not support it.
@ -66,7 +66,7 @@ def parse_arguments():
args = parser.parse_args()
return (args.log_level,
os.path.abspath(args.directory),
os.path.realpath(args.directory),
args.output,
args.ar,
args.paths if len(args.paths) > 0 else [args.directory])
@ -174,8 +174,8 @@ def process_line(root_directory, command_prefix, file_path):
# by Make, so this code replaces the escaped version with '#'.
prefix = command_prefix.replace('\#', '#').replace('$(pound)', '#')
# Use os.path.abspath() to normalize the path resolving '.' and '..' .
abs_path = os.path.abspath(os.path.join(root_directory, file_path))
# Return the canonical path, eliminating any symbolic links encountered in the path.
abs_path = os.path.realpath(os.path.join(root_directory, file_path))
if not os.path.exists(abs_path):
raise ValueError('File %s not found' % abs_path)
return {
@ -215,15 +215,15 @@ def main():
result = line_matcher.match(f.readline())
if result:
try:
entry = process_line(directory, result.group(1),
result.group(2))
entry = process_line(directory, result.group('command_prefix'),
result.group('file_path'))
compile_commands.append(entry)
except ValueError as err:
logging.info('Could not add line from %s: %s',
cmdfile, err)
with open(output, 'wt') as f:
json.dump(compile_commands, f, indent=2, sort_keys=True)
json.dump(sorted(compile_commands, key=lambda x: x["file"]), f, indent=2, sort_keys=True)
if __name__ == '__main__':