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Driver/DDR: Update DDR driver to allow non-zero base address

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The DRAM base has been zero for Power SoCs. It could be non-zero
for ARM SoCs. Use a macro instead of hard-coding to zero.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2013-10-28 16:36:02 -07:00
parent d4263b8adb
commit 00ec3fd211
1 changed files with 3 additions and 3 deletions
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6
drivers/ddr/fsl/main.c
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@ -255,7 +255,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
} }
current_mem_base = 0ull; current_mem_base = CONFIG_SYS_DDR_SDRAM_BASE;
total_mem = 0; total_mem = 0;
if (pinfo->memctl_opts[0].memctl_interleaving) { if (pinfo->memctl_opts[0].memctl_interleaving) {
rank_density = pinfo->dimm_params[0][0].rank_density >> rank_density = pinfo->dimm_params[0][0].rank_density >>
@ -535,8 +535,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
} }
} }
total_mem = 1 + (((unsigned long long)max_end << 24ULL) total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
| 0xFFFFFFULL); 0xFFFFFFULL) - CONFIG_SYS_DDR_SDRAM_BASE;
} }
return total_mem; return total_mem;