From https://distrib-coffee.ipsl.jussieu.fr/pub/linux/altlinux/Sisyphus/x86_64/SRPMS.classic/kernel-image-un-def-5.16.16-alt1.src.rpm Thanks! arch/arm64/Kconfig.platforms | 13 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/baikal/Makefile | 9 + arch/arm64/boot/dts/baikal/bm-dbm.dts | 367 ++ arch/arm64/boot/dts/baikal/bm-mbm.dtsi | 240 ++ arch/arm64/boot/dts/baikal/bm-mbm10.dts | 30 + arch/arm64/boot/dts/baikal/bm-mbm20.dts | 102 + arch/arm64/boot/dts/baikal/bm-qemu.dts | 163 + arch/arm64/boot/dts/baikal/bm1000-clocks.dtsi | 363 ++ arch/arm64/boot/dts/baikal/bm1000-cpufreq.dtsi | 249 ++ arch/arm64/boot/dts/baikal/bm1000.dtsi | 1060 +++++ arch/arm64/configs/baikal_minimal_defconfig | 4417 ++++++++++++++++++++ drivers/clk/Makefile | 1 + drivers/clk/baikal/Makefile | 1 + drivers/clk/baikal/clk-baikal.c | 363 ++ drivers/cpufreq/cpufreq-dt-platdev.c | 2 + drivers/firmware/efi/libstub/arm64-stub.c | 62 +- drivers/gpu/drm/Kconfig | 1 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/baikal/Kconfig | 15 + drivers/gpu/drm/baikal/Makefile | 10 + drivers/gpu/drm/baikal/baikal-hdmi.c | 119 + drivers/gpu/drm/baikal/baikal_vdu_connector.c | 118 + drivers/gpu/drm/baikal/baikal_vdu_crtc.c | 337 ++ drivers/gpu/drm/baikal/baikal_vdu_debugfs.c | 87 + drivers/gpu/drm/baikal/baikal_vdu_drm.h | 65 + drivers/gpu/drm/baikal/baikal_vdu_drv.c | 363 ++ drivers/gpu/drm/baikal/baikal_vdu_plane.c | 209 + drivers/gpu/drm/baikal/baikal_vdu_regs.h | 139 + drivers/gpu/drm/bridge/Kconfig | 7 + .../gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c | 106 +- drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h | 1 + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 + drivers/gpu/drm/panfrost/panfrost_devfreq.c | 4 + drivers/gpu/drm/panfrost/panfrost_device.h | 7 + drivers/gpu/drm/panfrost/panfrost_drv.c | 4 + drivers/gpu/drm/panfrost/panfrost_gpu.c | 45 + drivers/gpu/drm/panfrost/panfrost_job.c | 14 +- drivers/hwmon/Kconfig | 7 +- drivers/hwmon/bt1-pvt.c | 139 +- drivers/hwmon/bt1-pvt.h | 8 + drivers/i2c/busses/Kconfig | 2 +- drivers/input/serio/Kconfig | 10 + drivers/input/serio/Makefile | 1 + drivers/input/serio/tp_serio.c | 749 ++++ drivers/misc/Kconfig | 18 + drivers/misc/Makefile | 1 + drivers/misc/tp_bmc.c | 747 ++++ drivers/net/ethernet/stmicro/stmmac/Kconfig | 10 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-baikal.c | 230 + .../net/ethernet/stmicro/stmmac/dwmac1000_core.c | 1 + .../net/ethernet/stmicro/stmmac/dwmac1000_dma.c | 45 +- .../net/ethernet/stmicro/stmmac/dwmac1000_dma.h | 26 + drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c | 8 + drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 68 +- drivers/net/phy/phy_device.c | 41 +- drivers/rtc/rtc-efi.c | 9 + drivers/tty/serial/8250/8250_dw.c | 7 +- drivers/usb/dwc3/dwc3-of-simple.c | 2 + kernel/power/suspend.c | 12 + sound/soc/dwc/dwc-i2s.c | 36 +- sound/soc/dwc/local.h | 1 + 63 files changed, 11154 insertions(+), 126 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 54e3910e8b9b..5861fdc3a258 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -34,6 +34,19 @@ config ARCH_APPLE This enables support for Apple's in-house ARM SoC family, starting with the Apple M1. +config ARCH_BAIKAL + bool "Baikal Electronics Baikal-M SOC Family" + select GPIOLIB + select PINCTRL + select OF_GPIO + select GPIO_SYSFS + select GPIO_DWAPB + select GPIO_GENERIC + select DW_APB_TIMER + select DW_APB_TIMER_OF + help + This enables support for Baikal Electronics Baikal-M SOC Family + config ARCH_BCM2835 bool "Broadcom BCM2835 family" select TIMER_OF diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 639e01a4d855..2cec7300fef2 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -8,6 +8,7 @@ subdir-y += amlogic subdir-y += apm subdir-y += apple subdir-y += arm +subdir-y += baikal subdir-y += bitmain subdir-y += broadcom subdir-y += cavium diff --git a/arch/arm64/boot/dts/baikal/Makefile b/arch/arm64/boot/dts/baikal/Makefile new file mode 100644 index 000000000000..9729c6e3d4f3 --- /dev/null +++ b/arch/arm64/boot/dts/baikal/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BAIKAL) += bm-dbm.dtb +dtb-$(CONFIG_ARCH_BAIKAL) += bm-mbm10.dtb +dtb-$(CONFIG_ARCH_BAIKAL) += bm-mbm20.dtb +dtb-$(CONFIG_ARCH_BAIKAL) += bm-qemu.dtb + +always := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/baikal/bm-dbm.dts b/arch/arm64/boot/dts/baikal/bm-dbm.dts new file mode 100644 index 000000000000..5a180bfda8be --- /dev/null +++ b/arch/arm64/boot/dts/baikal/bm-dbm.dts @@ -0,0 +1,367 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree source for Baikal Electronics DBM board + * Copyright (C) 2019-2021 Baikal Electronics, JSC + */ + +/dts-v1/; + +#include +#include "bm1000.dtsi" + +/ { + model = "Baikal Electronics DBM"; + compatible = "baikal,baikal-m"; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + panel { + compatible = "panel-lvds"; + width-mm = <223>; + height-mm = <125>; + data-mapping = "vesa-24"; + panel-timing { + /* 1920x1080 @ 60 Hz */ + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hsync-len = <44>; + hfront-porch = <88>; + hback-porch = <148>; + vsync-len = <5>; + vfront-porch = <4>; + vback-porch = <36>; + }; + port { + panel0_lvds0: endpoint@0 { + remote-endpoint = <&vdu_lvds0_pads>; + }; + panel0_lvds1: endpoint@1 { + remote-endpoint = <&vdu_lvds1_pads>; + }; + }; + }; + + buttons-backlight { + compatible = "gpio-keys"; + autorepeat; + button-brightness-down { + label = "Brightness Down Button"; + linux,code = ; + gpios = <&porta 18 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + }; + button-brightness-up { + label = "Brightness Up Button"; + linux,code = ; + gpios = <&porta 17 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + }; + button-brightness-toggle { + label = "Brightness Toggle Button"; + linux,code = ; + gpios = <&porta 31 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + }; + }; + + sound { + compatible = "baikal,snd_soc_be"; + baikal,cpu-dai = <&i2s>; + baikal,audio-codec = <&tlv320aic3x>; + }; +}; + +&ddr2 { + status = "okay"; +}; + +&espi0 { + cs-gpios = <&porta 28 1>; /* todo: get real gpio */ + status = "okay"; + + /* test device #0 */ + espi_test0 { + compatible = "rohm,dh2228fv"; /* same as spidev */ + reg = <0>; + spi-max-frequency = <12000000>; + status = "okay"; + }; +}; + +&gmac0 { + status = "okay"; + snps,reset-gp-out; + snps,reset-active-low; +}; + +&gmac1 { + status = "okay"; + snps,reset-gp-out; + snps,reset-active-low; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + system-coherency = <0>; +}; + +&hda { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + tlv320aic3x: tlv320aic3x@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3x"; + reg = <0x18>; + reset-gpios = <&porta 4 GPIO_ACTIVE_LOW>; + status = "okay"; + ai3x-micbias-vg = <1>; + ai3x-ocmv = <1>; + }; + + rtc@56 { + compatible = "abracon,abeoz9"; + reg = <0x56>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2s { + status = "okay"; + sound-dai = <&tlv320aic3x>; + system-clock-frequency = <12000000>; +}; + +&mmc0 { + status = "okay"; +#if 0 + /* emmc */ + non-removable; + bus-width = <8>; + max-clock = <200000000>; +#else + /* sd */ + disable-wp; + bus-width = <4>; + max-clock = <25000000>; +#endif +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + +&pcie_lcru { + status = "okay"; +}; + +&pvt0 { + status = "okay"; +}; + +&pvt1 { + status = "okay"; +}; + +&pvt2 { + status = "okay"; +}; + +&pvt3 { + status = "okay"; +}; + +&pvt_mali { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&smbus0 { + status = "okay"; +}; + +&smbus1 { + status = "okay"; +}; + +&spi0 { + num-cs = <4>; + cs-gpios = + <&porta 24 1>, /* ss0 xp8 - DD53 normal flash */ + <&porta 25 1>, /* ss1 xp9 */ + <&porta 26 1>, /* ss2 xp10 */ + <&porta 27 1>; /* ss3 xp11 */ + status = "okay"; + + /* SPI flash chip #1 */ + flash0: m25p80@0 { + compatible = "micron,n25q256a", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <12500000>; + status = "okay"; + + /* Flash chip0 partitions */ + mtd0@0 { + label = "bl1"; + reg = <0x00000000 0x00040000>; + read-only; + }; + + mtd1@40000 { + label = "fip"; + reg = <0x00040000 0x007c0000>; + }; + + mtd2@800000 { + label = "rescue"; + reg = <0x00800000 0x01800000>; + }; + }; +}; + +#if 0 +/* undefined */ +&spi1 { + num-cs = <4>; + cs-gpios = + <&porta 20 1>, /* ss0 xp15 - DD57 boot flash */ + <&porta 21 1>, /* ss1 xp16 */ + <&porta 22 1>, /* ss2 xp17 */ + <&porta 23 1>; /* ss3 xp18 */ + status = "okay"; + + /* SPI flash chip #2 */ + flash0: m25p80@0 { + compatible = "micron,n25q256a", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <12500000>; + status = "okay"; + + /* Flash chip1 partitions */ + mtd0@0 { + label = "fip_backup"; + reg = <0x00000000 0x00400000>; + read-only; + }; + + mtd1@400000 { + label = "env_backup"; + reg = <0x00400000 0x00100000>; + read-only; + }; + + mtd2@500000 { + label = "data1"; + reg = <0x00500000 0x01b00000>; + }; + }; +}; +#endif + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&timer4 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&vdec { + status = "okay"; +}; + +&vdu0 { + status = "okay"; + enable-gpios = <&porta 16 GPIO_ACTIVE_LOW>; + backlight { + min-brightness-level = <10>; + default-brightness-level = <60>; + brightness-level-step = <2>; + pwm-frequency = <20000>; + }; + port { + vdu_lvds0_pads: endpoint@0 { + remote-endpoint = <&panel0_lvds0>; + }; + vdu_lvds1_pads: endpoint@1 { + remote-endpoint = <&panel0_lvds1>; + }; + /*vdu_lvds2_pads: endpoint@2 { + remote-endpoint = <&panel0_lvds2>; + }; + vdu_lvds3_pads: endpoint@3 { + remote-endpoint = <&panel0_lvds3>; + };*/ + }; +}; + +&vdu1 { + status = "okay"; +}; + +&xgmac0 { + status = "okay"; +}; + +&xgmac1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/baikal/bm-mbm.dtsi b/arch/arm64/boot/dts/baikal/bm-mbm.dtsi new file mode 100644 index 000000000000..3603db2a465b --- /dev/null +++ b/arch/arm64/boot/dts/baikal/bm-mbm.dtsi @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree include file for MBM-compatible boards + * Copyright (C) 2021 Baikal Electronics, JSC + */ + +#include "bm1000.dtsi" + +/ { + model = "Baikal Electronics MBM"; + compatible = "baikal,baikal-m"; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + leds { + compatible = "gpio-leds"; + led0 { + gpios = <&porta 8 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "MITX-Sound-Card"; + simple-audio-card,bitclock-master = <&codec0>; + simple-audio-card,frame-master = <&codec0>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "AUX Out", + "Line", "Line In"; + simple-audio-card,routing = + "Headphones", "RHP", + "Headphones", "LHP", + "AUX Out", "AUXOUT1", + "AUX Out", "AUXOUT2", + "L2", "Mic Jack", + "R2", "Mic Jack", + "LAUX", "Line In", + "RAUX", "Line In"; + simple-audio-card,mic-det-gpio = <&porta 26 GPIO_ACTIVE_LOW>; + simple-audio-card,format = "i2s"; + simple-audio-card,cpu { + sound-dai = <&i2s>; + }; + codec0: simple-audio-card,codec { + sound-dai = <&nau8822 0>; + }; + }; +}; + +&ddr2 { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + system-coherency = <0>; +}; + +&hdmi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + bmc@8 { + compatible = "tp,mitx2-bmc", "t-platforms,mitx2-bmc"; + reg = <0x08>; + }; + + nau8822: nau8822@1a { + compatible = "nuvoton,nau8822"; + #sound-dai-cells = <1>; + reg = <0x1a>; + }; + + gpio@50 { + compatible = "nxp,pca9670"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x50>; + }; + + rtc@51 { + compatible = "nxp,pcf2129", "nxp,pcf2127"; + reg = <0x51>; + }; + + hwmon@52 { + compatible = "tp,bm_mitx_hwmon"; + reg = <0x52>; + }; + + eeprom@53 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x53>; + }; + + ps2port@54 { + compatible = "tp,tp_serio"; + reg = <0x54>; + interrupt-parent = <&porta>; + interrupts = <14 8>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2s { + status = "okay"; + system-clock-frequency = <12000000>; + #sound-dai-cells = <0>; +}; + +&mdio0 { + status = "disabled"; +}; + +&mmc0 { + status = "okay"; + disable-wp; + bus-width = <4>; + max-clock = <25000000>; +}; + +&pcie0 { + status = "okay"; + reset-gpios = <&porta 6 GPIO_ACTIVE_LOW>; +}; + +&pcie2 { + status = "okay"; + reset-gpios = <&porta 3 GPIO_ACTIVE_LOW>; +}; + +&pcie_lcru { + status = "okay"; +}; + +&porta { + pcieclk { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + output-high; + line-name = "pcie-x8-clock"; + }; +}; + +&pvt0 { + status = "okay"; +}; + +&pvt1 { + status = "okay"; +}; + +&pvt2 { + status = "okay"; +}; + +&pvt3 { + status = "okay"; +}; + +&pvt_mali { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&smbus0 { + status = "okay"; +}; + +&smbus1 { + status = "okay"; +}; + +&spi0 { + num-cs = <4>; + cs-gpios = <0>; + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&timer4 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&vdec { + status = "okay"; +}; + +&vdu1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/baikal/bm-mbm10.dts b/arch/arm64/boot/dts/baikal/bm-mbm10.dts new file mode 100644 index 000000000000..8e02d3e08f3e --- /dev/null +++ b/arch/arm64/boot/dts/baikal/bm-mbm10.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree source for MBM 1.0 compatible boards: + * - TP-TF307-MB-A0 Rev.1.0 (BM1BM1-A) + * - TF307-MB-S-C Rev.3.0 + * + * Copyright (C) 2021 Baikal Electronics, JSC + */ + +/dts-v1/; + +#include "bm-mbm.dtsi" + +/ { + sound { + simple-audio-card,hp-det-gpio = <&porta 27 GPIO_ACTIVE_HIGH>; + }; +}; + +&gmac0 { + status = "okay"; + snps,reset-gp-out; + snps,reset-active-low; +}; + +&gmac1 { + status = "okay"; + snps,reset-gp-out; + snps,reset-active-low; +}; diff --git a/arch/arm64/boot/dts/baikal/bm-mbm20.dts b/arch/arm64/boot/dts/baikal/bm-mbm20.dts new file mode 100644 index 000000000000..1c0a459a2781 --- /dev/null +++ b/arch/arm64/boot/dts/baikal/bm-mbm20.dts @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree source for MBM 2.0 compatible boards: + * - TF307-MB-S-D Rev.4.0 (BM1BM1-D) + * + * Copyright (C) 2021 Baikal Electronics, JSC + */ + +/dts-v1/; + +#include +#include "bm-mbm.dtsi" + +/ { + panel { + /* In order to utilize LVDS LCD panel, make sure that + status is "okay" along with &vdu0 status (see below). */ + status = "disabled"; + compatible = "panel-lvds"; + width-mm = <223>; + height-mm = <125>; + data-mapping = "vesa-24"; + panel-timing { + /* 1920x1080 @ 60 Hz */ + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hsync-len = <44>; + hfront-porch = <88>; + hback-porch = <148>; + vsync-len = <5>; + vfront-porch = <4>; + vback-porch = <36>; + }; + port { + panel0_lvds0: endpoint@0 { + remote-endpoint = <&vdu_lvds0_pads>; + }; + panel0_lvds1: endpoint@1 { + remote-endpoint = <&vdu_lvds1_pads>; + }; + }; + }; + + buttons-backlight { + compatible = "gpio-keys"; + autorepeat; + button-brightness-down { + label = "Brightness Down Button"; + linux,code = ; + gpios = <&porta 18 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + }; + button-brightness-up { + label = "Brightness Up Button"; + linux,code = ; + gpios = <&porta 17 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + }; + button-brightness-toggle { + label = "Brightness Toggle Button"; + linux,code = ; + gpios = <&porta 31 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + }; + }; + + sound { + simple-audio-card,hp-det-gpio = <&porta 29 GPIO_ACTIVE_HIGH>; + }; +}; + +&gmac0 { + status = "okay"; + snps,reset-gpios = <&porta 19 GPIO_ACTIVE_LOW>; +}; + +&gmac1 { + status = "okay"; + snps,reset-gpios = <&porta 20 GPIO_ACTIVE_LOW>; +}; + +&vdu0 { + /* In order to utilize LVDS LCD panel, make sure that + status is "okay" along with panel status (see above). */ + status = "disabled"; + enable-gpios = <&porta 16 GPIO_ACTIVE_LOW>; + backlight { + min-brightness-level = <10>; + default-brightness-level = <60>; + brightness-level-step = <2>; + pwm-frequency = <20000>; + }; + port { + vdu_lvds0_pads: endpoint@0 { + remote-endpoint = <&panel0_lvds0>; + }; + vdu_lvds1_pads: endpoint@1 { + remote-endpoint = <&panel0_lvds1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/baikal/bm-qemu.dts b/arch/arm64/boot/dts/baikal/bm-qemu.dts new file mode 100644 index 000000000000..c6350c0aaeb5 --- /dev/null +++ b/arch/arm64/boot/dts/baikal/bm-qemu.dts @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree source for Baikal-M software emulator (QEMU) platform + * Copyright (C) 2018-2021 Baikal Electronics, JSC + */ + +/dts-v1/; + +#include "bm1000.dtsi" + +/* + * Device "flash@0" was added to allow UEFI to boot on emulator. + * TODO: the tree should be replaced by actual Baikal-M component tree + */ + +/ { + model = "Baikal Electronics Baikal-M virtual platform"; + compatible = "baikal,baikal-m"; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "root=/dev/ram rw rootwait console=ttyS0,115200n8 earlyprintk=uart8250,mmio32,0x20230000,115200"; + }; + + memory@80000000 { + device_type = "memory"; + /* 16GB */ + reg = <0x00000000 0x80000000 0x0 0x80000000 + 0x00000008 0x80000000 0x1 0x80000000>; + }; + + /* XXX: Temporary fix for qemu to work */ + /* Device is necessary for UEFI to boot on QEMU, need to replace it with something later */ + flash@0 { + compatible = "cfi-flash"; + reg = <0x0 0x4000000 0x0 0x4000000>; + bank-width = <0x4>; + }; + + panel: panel { + compatible = "auo,b133htn01"; /* 1920x1080 */ + /*compatible = "auo,b133xtn01; /* 1366x768 */ + /*compatible = "auo,b101aw03"; /* 1024x600 */ + /*compatible = "innolux,g121x1-l03"; /* 1024x768 */ + /*compatible = "auo,b101ean01"; /* 1280x800 */ + + port { + lcd_panel: endpoint { + remote-endpoint = <&vdu_pads>; + }; + }; + }; + + /*panel_hdmi: panel { + compatible = "edt,et057090dhu"; + + port { + lcd_hdmi_panel: endpoint { + remote-endpoint = <&vdu_hdmi_pads>; + }; + }; + };*/ +}; + +&gmac0 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&spi0 { + num-cs = <6>; + status = "okay"; + + /* SPI flash chip #1 */ + flash0: m25p80@0 { + compatible = "micron,n25q256a", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + status = "okay"; + + /* Flash chip0 partitions */ + mtd0@0 { + label = "fip"; + reg = <0x00000000 0x00400000>; + read-only; + }; + + mtd1@400000 { + label = "env"; + reg = <0x00400000 0x00100000>; + }; + + mtd2@500000 { + label = "kernel"; + reg = <0x00500000 0x00400000>; + }; + + mtd3@900000 { + label = "rootfs"; + reg = <0x00900000 0x00800000>; + }; + + mtd4@1100000 { + label = "data0"; + reg = <0x01100000 0x00f00000>; + }; + }; + + /* SPI flash chip #2 */ + flash1: m25p80@1 { + compatible = "micron,n25q256a", "jedec,spi-nor"; + reg = <1>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + status = "okay"; + + /* Flash chip1 partitions */ + mtd0@0 { + label = "fip_backup"; + reg = <0x00000000 0x00400000>; + read-only; + }; + + mtd1@400000 { + label = "env_backup"; + reg = <0x00400000 0x00100000>; + read-only; + }; + + mtd2@500000 { + label = "data1"; + reg = <0x00500000 0x01b00000>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&vdu0 { + port { + vdu_pads: endpoint { + remote-endpoint = <&lcd_panel>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/baikal/bm1000-clocks.dtsi b/arch/arm64/boot/dts/baikal/bm1000-clocks.dtsi new file mode 100644 index 000000000000..0a5579d3694b --- /dev/null +++ b/arch/arm64/boot/dts/baikal/bm1000-clocks.dtsi @@ -0,0 +1,363 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree include file for BE-M1000 SoC clocks + * Copyright (C) 2017-2021 Baikal Electronics, JSC + */ + +/ { + /* external oscillator */ + osc25: oscillator25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "osc25"; + }; + + /* external oscillator */ + osc27: oscillator27 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "osc27"; + }; + + cmu_cluster0: cmu_cluster0 { + compatible = "baikal,cmu"; + clock-output-names = "baikal-ca57_cmu0"; + #clock-cells = <0>; + clocks = <&osc25>; + cmu-id = <0x28000000>; + max = <1500000000>; + min = <500000000>; + clock-frequency = <1500000000>; + }; + + cmu_cluster1: cmu_cluster1 { + compatible = "baikal,cmu"; + clock-output-names = "baikal-ca57_cmu1"; + #clock-cells = <0>; + clocks = <&osc25>; + cmu-id = <0xc000000>; + max = <1500000000>; + min = <500000000>; + clock-frequency = <1500000000>; + }; + + cmu_cluster2: cmu_cluster2 { + compatible = "baikal,cmu"; + clock-output-names = "baikal-ca57_cmu2"; + #clock-cells = <0>; + clocks = <&osc25>; + cmu-id = <0xa000000>; + max = <1500000000>; + min = <500000000>; + clock-frequency = <1500000000>; + }; + + cmu_cluster3: cmu_cluster3 { + compatible = "baikal,cmu"; + clock-output-names = "baikal-ca57_cmu3"; + #clock-cells = <0>; + clocks = <&osc25>; + cmu-id = <0x26000000>; + max = <1500000000>; + min = <500000000>; + clock-frequency = <1500000000>; + }; + + cmu0_avlsp: cmu0_avlsp { + compatible = "baikal,cmu"; + #clock-cells = <1>; + clock-output-names = "baikal-avlsp_cmu0"; + clock-names = + "gpio", // <0> + "uart1", // <1> + "uart2", // <2> + "apb", // <3> + "spi", // <4> + "espi", // <5> + "i2c1", // <6> + "i2c2", // <7> + "timer1", // <8> + "timer2", // <9> + "timer3", // <10> + "timer4", // <11> + "dmac", // <12> + "smbus1", // <13> + "smbus2", // <14> + "hda_sys_clk", // <15> + "hda_clk48", // <16> + "mshc_axi", // <17> + "mshc_ahb", // <18> + "mshc_tx_x2", // <19> + "mshc_b", // <20> + "mshc_tm", // <21> + "mshc_cqetm", // <22> + "hwa_clu", // <23> + "hwa_clu_hf", // <24> + "hwa_axi", // <25> + "vdu_axi", // <26> + "smmu"; // <27> + clock-indices = + <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, + <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>, + <20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>; + clocks = <&osc25>; + cmu-id = <0x20000000>; + max = <2100000000>; + min = <800000>; + clock-frequency = <1200000000>; + }; + + cmu1_avlsp: cmu1_avlsp { + compatible = "baikal,cmu"; + clock-output-names = "baikal-avlsp_cmu1"; + #clock-cells = <0>; + clocks = <&osc27>; + cmu-id = <0x20010000>; + max = <2100000000>; + min = <13500000>; + clock-frequency = <1039500000>; + }; + + cmu_mali: cmu_mali { + compatible = "baikal,cmu"; + clock-output-names = "baikal-mali-cmu"; + #clock-cells = <0>; + clocks = <&osc25>; + clock-names = "aclk"; + cmu-id = <0x2a000000>; + max = <800000000>; + min = <400000000>; + clock-frequency = <750000000>; + }; + + cmu0_xgbe: cmu0_xgbe { + compatible = "baikal,cmu"; + clock-output-names = "baikal-xgbe-cmu0"; + #clock-cells = <1>; + clocks = <&osc25>; + clock-names = "csr50mhz", "gmac0_tx2", "gmac1_tx2", "hdmi_aclk", "isfr"; + clock-indices = <0>, <10>, <13>, <15>, <17>; + cmu-id = <0x30000000>; + max = <1250000000>; + min = <50000000>; + clock-frequency = <1250000000>; + }; + + cmu1_xgbe: cmu1_xgbe { + compatible = "baikal,cmu"; + clock-output-names = "baikal-xgbe-cmu1"; + #clock-cells = <1>; + clocks = <&osc27>; + clock-indices = <0>; + clock-names = "pixelclk"; + cmu-id = <0x30010000>; + max = <600000000>; + min = <13500000>; + clock-frequency = <25250000>; + }; + + clocks { + cpu_clk: cpu_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1500000000>; + clock-output-names = "cpuclk"; + }; + + apb_clk: apb_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "apb_pclk"; + }; + + uart_clk: uart_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <7273800>; + clock-output-names = "soc_uartclk"; + }; + + i2c_clk: i2c_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "soc_i2cclk"; + }; + + smbus_clk: smbus_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "soc_smbusclk"; + }; + + timer1_clk: timer1_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "soc_timer1clk"; + }; + + timer2_clk: timer2_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "soc_timer2clk"; + }; + + timer3_clk: timer3_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "soc_timer3clk"; + }; + + timer4_clk: timer4_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "soc_timer4clk"; + }; + + gpio_clk: gpio_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "soc_gpioclk"; + }; + + spi_clk: spi_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "soc_spiclk"; + }; + + soc_ethclk: ethclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "eth_clk"; + }; + + soc_xgbeclk: xgbeclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + clock-output-names = "xgbe_clk"; + }; + + soc_smc50mhz: clk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "smc_clk"; + }; + + soc_faxiclk: refclk400mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "faxi_clk"; + }; + + soc_tmp_clk: refclkXXXmhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "tmpclk"; + }; + + gpu_clk: gpu_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <750000000>; + clock-output-names = "gpuclk"; + }; + gpu_opp_table: opp_table_gpu { + compatible = "operating-points-v2", "operating-points-v2-mali"; + + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + clock-latency-ns = <10000000>; + }; + opp@450000000 { + opp-hz = /bits/ 64 <450000000>; + clock-latency-ns = <10000000>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <10000000>; + }; + opp@550000000 { + opp-hz = /bits/ 64 <550000000>; + clock-latency-ns = <10000000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <10000000>; + }; + opp@650000000 { + opp-hz = /bits/ 64 <650000000>; + clock-latency-ns = <10000000>; + }; + opp@700000000 { + opp-hz = /bits/ 64 <700000000>; + clock-latency-ns = <10000000>; + }; + opp@750000000 { + opp-hz = /bits/ 64 <750000000>; + clock-latency-ns = <10000000>; + }; + }; + + clk_ahb: clk_ahb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "clk_ahb"; + }; + + clk_xin: clk_xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "clk_xin"; + }; + + cortex_cmu: cmu@cortex { + compatible = "baikal,cmu-device-clock"; + #clock-cells = <1>; + clock-frequency = <1000000000>; + clock-output-names = "baikal-cmu"; + }; + + avlsp_cmu1: cmu1@avlsp { + compatible = "baikal,cmu-device-clock"; + #clock-cells = <1>; + clock-indices = <26>; + clock-frequency = <240000000>; + clock-output-names = "baikal-cmu"; + }; + + usb_clk: usb_clk@1f04d074 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-names = "usbclk"; + clock-frequency = <500000000>; + clock-output-names = "usbclk"; + }; + + cmu1_avlsp_div7: cmu1_avlsp_div7 { + compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock"; + clocks = <&cmu1_avlsp>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + clock-output-names = "lvds_clk"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/baikal/bm1000-cpufreq.dtsi b/arch/arm64/boot/dts/baikal/bm1000-cpufreq.dtsi new file mode 100644 index 000000000000..76fee58d8bfc --- /dev/null +++ b/arch/arm64/boot/dts/baikal/bm1000-cpufreq.dtsi @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree include file for BE-M1000 SoC CPU frequencies + * Copyright (C) 2020-2021 Baikal Electronics, JSC + */ + +/ { + cpufreq { + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@1500 { + opp-hz = /bits/ 64 <1500000000>; + clock-latency-ns = <10000000>; + }; + + opp@1400 { + opp-hz = /bits/ 64 <1400000000>; + clock-latency-ns = <10000000>; + }; + + opp@1300 { + opp-hz = /bits/ 64 <1300000000>; + clock-latency-ns = <10000000>; + }; + + opp@1200 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <10000000>; + }; + + opp@1100 { + opp-hz = /bits/ 64 <1100000000>; + clock-latency-ns = <10000000>; + }; + + opp@1000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <10000000>; + }; + + opp@900 { + opp-hz = /bits/ 64 <900000000>; + clock-latency-ns = <10000000>; + }; + + opp@800 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <10000000>; + }; + + opp@700 { + opp-hz = /bits/ 64 <700000000>; + clock-latency-ns = <10000000>; + }; + + opp@600 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <10000000>; + }; + + opp@500 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <10000000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@1500 { + opp-hz = /bits/ 64 <1500000000>; + clock-latency-ns = <10000000>; + }; + + opp@1400 { + opp-hz = /bits/ 64 <1400000000>; + clock-latency-ns = <10000000>; + }; + + opp@1300 { + opp-hz = /bits/ 64 <1300000000>; + clock-latency-ns = <10000000>; + }; + + opp@1200 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <10000000>; + }; + + opp@1100 { + opp-hz = /bits/ 64 <1100000000>; + clock-latency-ns = <10000000>; + }; + + opp@1000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <10000000>; + }; + + opp@900 { + opp-hz = /bits/ 64 <900000000>; + clock-latency-ns = <10000000>; + }; + + opp@800 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <10000000>; + }; + + opp@700 { + opp-hz = /bits/ 64 <700000000>; + clock-latency-ns = <10000000>; + }; + + opp@600 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <10000000>; + }; + + opp@500 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <10000000>; + }; + }; + + cluster2_opp: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp@1500 { + opp-hz = /bits/ 64 <1500000000>; + clock-latency-ns = <10000000>; + }; + + opp@1400 { + opp-hz = /bits/ 64 <1400000000>; + clock-latency-ns = <10000000>; + }; + + opp@1300 { + opp-hz = /bits/ 64 <1300000000>; + clock-latency-ns = <10000000>; + }; + + opp@1200 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <10000000>; + }; + + opp@1100 { + opp-hz = /bits/ 64 <1100000000>; + clock-latency-ns = <10000000>; + }; + + opp@1000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <10000000>; + }; + + opp@900 { + opp-hz = /bits/ 64 <900000000>; + clock-latency-ns = <10000000>; + }; + + opp@800 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <10000000>; + }; + + opp@700 { + opp-hz = /bits/ 64 <700000000>; + clock-latency-ns = <10000000>; + }; + + opp@600 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <10000000>; + }; + + opp@500 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <10000000>; + }; + }; + + cluster3_opp: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@1500 { + opp-hz = /bits/ 64 <1500000000>; + clock-latency-ns = <10000000>; + }; + + opp@1400 { + opp-hz = /bits/ 64 <1400000000>; + clock-latency-ns = <10000000>; + }; + + opp@1300 { + opp-hz = /bits/ 64 <1300000000>; + clock-latency-ns = <10000000>; + }; + + opp@1200 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <10000000>; + }; + + opp@1100 { + opp-hz = /bits/ 64 <1100000000>; + clock-latency-ns = <10000000>; + }; + + opp@1000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <10000000>; + }; + + opp@900 { + opp-hz = /bits/ 64 <900000000>; + clock-latency-ns = <10000000>; + }; + + opp@800 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <10000000>; + }; + + opp@700 { + opp-hz = /bits/ 64 <700000000>; + clock-latency-ns = <10000000>; + }; + + opp@600 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <10000000>; + }; + + opp@500 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <10000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/baikal/bm1000.dtsi b/arch/arm64/boot/dts/baikal/bm1000.dtsi new file mode 100644 index 000000000000..390f0a0c6fdf --- /dev/null +++ b/arch/arm64/boot/dts/baikal/bm1000.dtsi @@ -0,0 +1,1060 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree include file for BE-M1000 SoC + * Copyright (C) 2017-2021 Baikal Electronics, JSC + */ + +#include "bm1000-clocks.dtsi" +#include "bm1000-cpufreq.dtsi" +#include +#include + +/* + * ARM GICv3 bindings assume interrupts (in each range) counting from 0: + * PPI: 0..15 + * SPI: 0..987 + * Baikal-M documentation ("Interrupt map") places all interrupts into the + * linear map: SGI(0..15), PPI(16..31), SPI(32-1019). + * So real interrupt IDs in this device tree must be calculated as follows: + * PPI_real = PPI_from_documentation - 16 + * SPI_real = SPI_from_documentation - 32 + */ + +/ { + compatible = "baikal,arm", "baikal,baikal-m-soc", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + aliases { + ethernet1 = &gmac0; + ethernet2 = &gmac1; + ethernet3 = &xgmac0; + ethernet4 = &xgmac1; + gic = &gic; + gpio = &gpio; + hda = &hda; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2s = &i2s; + memory-controller1 = &ddr1; + memory-controller2 = &ddr2; + mmc0 = &mmc0; + pvt0 = &pvt0; + pvt1 = &pvt1; + pvt2 = &pvt2; + pvt3 = &pvt3; + pvt_mali = &pvt_mali; + sata0 = &sata0; + sata1 = &sata1; + serial0 = &uart0; + serial1 = &uart1; + smbus0 = &smbus0; + smbus1 = &smbus1; + spi = &spi0; + ssi0 = &spi0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + timer4 = &timer4; + usb2 = &usb2; + usb3 = &usb3; + vdec = &vdec; + vdu_lvds = &vdu0; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* Do not use 'cpu-map'. It leads to wrong topology. */ + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x0>; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + clocks = <&cmu_cluster0>; + next-level-cache = <&cluster0_l2>; + clock-names = "baikal-ca57_cmu"; + operating-points-v2 = <&cluster0_opp>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x1>; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + clocks = <&cmu_cluster0>; + next-level-cache = <&cluster0_l2>; + clock-names = "baikal-ca57_cmu"; + operating-points-v2 = <&cluster0_opp>; + }; + + CPU2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x100>; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + clocks = <&cmu_cluster1>; + next-level-cache = <&cluster1_l2>; + clock-names = "baikal-ca57_cmu"; + operating-points-v2 = <&cluster1_opp>; + }; + + CPU3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x101>; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + clocks = <&cmu_cluster1>; + next-level-cache = <&cluster1_l2>; + clock-names = "baikal-ca57_cmu"; + operating-points-v2 = <&cluster1_opp>; + }; + + CPU4: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x200>; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + clocks = <&cmu_cluster2>; + next-level-cache = <&cluster2_l2>; + clock-names = "baikal-ca57_cmu"; + operating-points-v2 = <&cluster2_opp>; + }; + + CPU5: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x201>; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + clocks = <&cmu_cluster2>; + next-level-cache = <&cluster2_l2>; + clock-names = "baikal-ca57_cmu"; + operating-points-v2 = <&cluster2_opp>; + }; + + CPU6: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x300>; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + clocks = <&cmu_cluster3>; + next-level-cache = <&cluster3_l2>; + clock-names = "baikal-ca57_cmu"; + operating-points-v2 = <&cluster3_opp>; + }; + + CPU7: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x301>; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + clocks = <&cmu_cluster3>; + next-level-cache = <&cluster3_l2>; + clock-names = "baikal-ca57_cmu"; + operating-points-v2 = <&cluster3_opp>; + }; + + cluster0_l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-unified; + cache-level = <2>; + next-level-cache = <&l3>; + }; + + cluster1_l2: l2-cache1 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-unified; + cache-level = <2>; + next-level-cache = <&l3>; + }; + + cluster2_l2: l2-cache2 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-unified; + cache-level = <2>; + next-level-cache = <&l3>; + }; + + cluster3_l2: l2-cache3 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-unified; + cache-level = <2>; + next-level-cache = <&l3>; + }; + + l3: l3-cache { + cache-size = <0x800000>; + cache-unified; + cache-level = <3>; + }; + }; + + pmu { + compatible = "arm,cortex-a57-pmu"; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* DDR0 (e200000, 10000, SPI_161-166_?) */ + ddr1: memory-controller1@e200000 { + compatible = "be,emc", "be,memory-controller"; + reg = <0x0 0x0e200000 0x0 0x10000>; + interrupts = , /* ddr dfi alert err */ + , /* ddr ecc corrected err */ + , /* ddr ecc uncorrected err */ + , /* ddr sbr done */ + , /* ddr ecc corrected err fault */ + ; /* ddr ecc uncorrected err fault */ + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + /* DDR1 (22200000, 10000, SPI_171-176_?) */ + ddr2: memory-controller2@22200000 { + compatible = "be,emc", "be,memory-controller"; + reg = <0x0 0x22200000 0x0 0x10000>; + interrupts = , /* ddr dfi alert err */ + , /* ddr ecc corrected err */ + , /* ddr ecc uncorrected err */ + , /* ddr sbr done */ + , /* ddr ecc corrected err fault */ + ; /* ddr ecc uncorrected err fault */ + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + pcie_lcru: lcru@2000000 { + compatible = "syscon"; + reg = <0x0 0x2000000 0x0 0x80000>; + /*big-endian;*/ + status = "disabled"; + }; + + pcie0: pcie@2200000 { /* PCIe x4 #0 */ + compatible = "baikal,pcie-m", "snps,dw-pcie"; + reg = <0x0 0x02200000 0x0 0x1000>, /* RC config space */ + <0x0 0x40100000 0x0 0x100000>; /* PCI config space */ + reg-names = "dbi", "config"; + interrupts = , /* AER */ + ; /* MSI */ + #interrupt-cells = <1>; + baikal,pcie-lcru = <&pcie_lcru 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, /* I/O */ + <0x82000000 0x0 0x40000000 0x4 0x00000000 0x0 0x40000000>; /* 32b non-prefetchable memory */ + msi-parent = <&its 0x0>; + msi-map = <0x0 &its 0x0 0x10000>; + num-lanes = <4>; + num-viewport = <4>; + bus-range = <0x0 0xff>; + status = "disabled"; + }; + + pcie1: pcie@2210000 { /* PCIe x4 #1 */ + compatible = "baikal,pcie-m", "snps,dw-pcie"; + reg = <0x0 0x02210000 0x0 0x1000>, /* RC config space */ + <0x0 0x50100000 0x0 0x100000>; /* PCI config space */ + reg-names = "dbi", "config"; + interrupts = , /* AER */ + ; /* MSI */ + #interrupt-cells = <1>; + baikal,pcie-lcru = <&pcie_lcru 1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0x0 0x00100000 0x0 0x50000000 0x0 0x100000>, /* I/O */ + <0x82000000 0x0 0x40000000 0x5 0x00000000 0x0 0x40000000>; /* 32b non-prefetchable memory */ + msi-parent = <&its 0x0>; + msi-map = <0x0 &its 0x0 0x10000>; + num-lanes = <4>; + num-viewport = <4>; + bus-range = <0x0 0xff>; + status = "disabled"; + }; + + pcie2: pcie@2220000 { /* PCIe x8 */ + compatible = "baikal,pcie-m", "snps,dw-pcie"; + reg = <0x0 0x02220000 0x0 0x1000>, /* RC config space */ + <0x0 0x60000000 0x0 0x100000>; /* PCI config space */ + reg-names = "dbi", "config"; + interrupts = , /* AER */ + ; /* MSI */ + #interrupt-cells = <1>; + baikal,pcie-lcru = <&pcie_lcru 2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0x0 0x00200000 0x0 0x60100000 0x0 0x100000>, /* I/O */ + <0x82000000 0x0 0x80000000 0x6 0x00000000 0x0 0x80000000>; /* 32b non-prefetchable memory */ + msi-parent = <&its 0x0>; + msi-map = <0x0 &its 0x0 0x10000>; + num-lanes = <8>; + num-viewport = <4>; + bus-range = <0x0 0xff>; + status = "disabled"; + }; + + ccn: ccn@9000000 { + compatible = "arm,ccn-504"; + reg = <0x0 0x9000000 0 0x1000000>; + interrupts = ; + }; + + pvt0: pvt0@28200000 { + compatible = "baikal,pvt"; + reg = <0x0 0x28200000 0x0 0x10000>; + pvt_id = <0>; + interrupts = ; + status = "disabled"; + }; + + pvt1: pvt1@c200000 { + compatible = "baikal,pvt"; + reg = <0x0 0xc200000 0x0 0x10000>; + pvt_id = <1>; + interrupts = ; + status = "disabled"; + }; + + pvt2: pvt2@a200000 { + compatible = "baikal,pvt"; + reg = <0x0 0xa200000 0x0 0x10000>; + pvt_id = <2>; + interrupts = ; + status = "disabled"; + }; + + pvt3: pvt3@26200000 { + compatible = "baikal,pvt"; + reg = <0x0 0x26200000 0x0 0x10000>; + pvt_id = <3>; + interrupts = ; + status = "disabled"; + }; + + pvt_mali: pvt_mali@2a060000 { + compatible = "baikal,pvt"; + reg = <0x0 0x2a060000 0x0 0x10000>; + pvt_id = <4>; + interrupts = ; + status = "disabled"; + }; + + /* AVLSP: GPIO32 (20200000, 10000, SPI_131_H) */ + gpio: gpio@20200000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x20200000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + #gpio-cells = <2>; + gpio-controller; + snps,nr-gpios = <32>; + reg = <0>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = ; + }; + }; + + /* AVLSP: SPI (20210000, 10000, SPI_132_H) */ + spi0: spi@20210000 { + compatible = "snps,dw-apb-ssi", "snps,dw-spi"; + reg = <0x0 0x20210000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&cmu0_avlsp 4>; + clock-names = "soc_spiclk"; + status = "disabled"; + }; + + /* AVLSP: I2S (20220000, 1000, SPI_136-139_H) */ + i2s: i2s@20220000 { + compatible = "snps,designware-i2s"; + reg = <0x0 0x20220000 0x0 0x10000>; + interrupts = , /* rx_da */ + , /* rx_or */ + , /* tx_emp */ + ; /* tx_or */ + /*dmas = <&dma 2>, <&dma 3>;*/ + /*dma-names = "tx", "rx";*/ + /*#sound-dai-cells = <0>;*/ + clocks = <&soc_tmp_clk>; + clock-names = "i2sclk"; + status = "disabled"; + }; + + /* AVLSP: UART1 (20230000, 10000, SPI_133_H) */ + uart0: serial0@20230000 { + compatible = "snps,dw-apb-uart"; /* "snps,uart-16550-compatible" */ + reg = <0x0 0x20230000 0x0 0x10000>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cmu0_avlsp 1>, <&apb_clk>; + clock-names = "soc_uartclk", "apb_pclk"; + /*dcd-override;*/ + /*dsr-override;*/ + /*cts-override;*/ + /*ri-override;*/ + status = "disabled"; + }; + + /* AVLSP: UART2 (20240000, 10000, SPI_134_H) */ + uart1: serial1@20240000 { + compatible = "snps,dw-apb-uart"; /* "snps,uart-16550-compatible" */ + reg = <0x0 0x20240000 0x0 0x10000>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cmu0_avlsp 2>, <&apb_clk>; + clock-names = "soc_uartclk", "apb_pclk"; + status = "disabled"; + }; + + /* AVLSP: I2C1 (20250000, 10000, SPI_140_H) */ + i2c0: i2c0@20250000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20250000 0x0 0x10000>; + interrupts = ; + i2c-sda-hold-time-ns = <500>; + clock-frequency = <400000>; + clocks = <&i2c_clk>; + clock-names = "soc_i2cclk"; + status = "disabled"; + }; + + /* AVLSP: I2C2 (20260000, 10000, SPI_141_H) */ + i2c1: i2c1@20260000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20260000 0x0 0x10000>; + interrupts = ; + i2c-sda-hold-time-ns = <500>; + clock-frequency = <400000>; + clocks = <&i2c_clk>; + clock-names = "soc_i2cclk"; + status = "disabled"; + }; + + /* AVLSP: SMBus1 (20270000, 10000, SPI_142_?) */ + smbus0: smbus0@20270000 { + compatible = "be,smbus"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20270000 0x0 0x10000>; + interrupts = ; + clock-frequency = <100000>; + clocks = <&smbus_clk>; + clock-names = "soc_smbusclk"; + status = "disabled"; + }; + + /* AVLSP: SMBus2 (20280000, 10000, SPI_143_?) */ + smbus1: smbus1@20280000 { + compatible = "be,smbus"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20280000 0x0 0x10000>; + interrupts = ; + clock-frequency = <100000>; + clocks = <&smbus_clk>; + clock-names = "soc_smbusclk"; + status = "disabled"; + }; + + /* AVLSP: Timers (20290000, 10000, SPI_127_L) */ + timer1: timer1@20290000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x0 0x20290000 0x0 0x14>; + interrupts = ; + clock-frequency = <50000000>; + clocks = <&timer1_clk>; + clock-names = "soc_timer1clk"; + status = "disabled"; + }; + + /* AVLSP: Timers (20290000, 10000, SPI_128_L) */ + timer2: timer2@20290014 { + compatible = "snps,dw-apb-timer-sp"; + reg = <0x0 0x20290014 0x0 0x14>; + interrupts = ; + clock-frequency = <50000000>; + clocks = <&timer2_clk>; + clock-names = "soc_timer2clk"; + status = "disabled"; + }; + + /* AVLSP: Timers (20290000, 10000, SPI_129_L) */ + timer3: timer3@20290028 { + compatible = "snps,dw-apb-timer-sp"; + reg = <0x0 0x20290028 0x0 0x14>; + interrupts = ; + clock-frequency = <50000000>; + clocks = <&timer3_clk>; + clock-names = "soc_timer3clk"; + status = "disabled"; + }; + + /* AVLSP: Timers (20290000, 10000, SPI_130_L) */ + timer4: timer4@2029003c { + compatible = "snps,dw-apb-timer-sp"; + reg = <0x0 0x2029003c 0x0 0x14>; + interrupts = ; + clock-frequency = <50000000>; + clocks = <&timer4_clk>; + clock-names = "soc_timer4clk"; + status = "disabled"; + }; + + /* AVLSP: eSPI (202a0000, 10000, SPI_135_?) */ + espi0: espi0@202a0000 { + compatible = "be,espi"; + reg = <0x0 0x202a0000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&cmu0_avlsp 5>; + clock-names = "soc_espiclk"; + status = "disabled"; + /* + * Block Configuration: + * - master/slave + * - 32-bit APB slave + * - tx-fifo = rx-fifo = 256 byte + * - 4 SPI IO channels + * - 8 slave select IO channels + * - DMA - missing + * - M-flash controller - missing + */ + }; + + /* AVLSP: DMAC (202b0000, 10000, SPI_41-80_H) */ + lsdma: dma@202b0000 { + compatible = "snps,dma-spear1340"; + reg = <0x0 0x202b0000 0x0 0x10000>; + /* TODO: interrupts */ + interrupts = ; + dma-channels = <8>; + dma-requests = <16>; + dma-masters = <2>; + #dma-cells = <3>; + chan_allocation_order = <1>; + chan_priority = <1>; + block_size = <0xfff>; + data_width = <3 3 0 0>; + clocks = <&soc_tmp_clk>; + clock-names = "tmpclk"; + status = "disabled"; + }; + + /* AVLSP: HDA (202c0000, 10000, SPI_86_H) */ + hda: hda@202c0000 { + compatible = "be,cw-hda"; + reg = <0x0 0x202c0000 0x0 0x1000>; + interrupts = ; + clocks = <&cmu0_avlsp 15>, <&cmu0_avlsp 16>; + clock-names = "hda_sys_clk", "hda_clk48"; + status = "disabled"; + }; + + /* AVLSP: VDU (202d0000, 10000, SPI_144-145_?) */ + vdu0: vdu_lvds@202d0000 { + compatible = "baikal,vdu"; + reg = <0x0 0x202d0000 0x0 0x1000>; + interrupts = , /* VDU INTR */ + ; /* VDU INTR_CDD */ + clocks = <&cmu1_avlsp_div7>; + clock-names = "pclk"; + lvds-out; + status = "disabled"; + }; + + /* AVLSP: SD/eMMC (202e0000, 10000, SPI_83-84_H) */ + mmc0: mmc@202e0000 { + compatible = "snps,dwcmshc-sdhci"; + reg = <0x0 0x202e0000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = , + ; + clock-names = "bus", "core"; + clocks = <&cmu0_avlsp 18>, <&cmu0_avlsp 19>; + status = "disabled"; + }; + + vdec: vdec@24200000 { + compatible = "baikal,d5500-vxd"; + reg = <0x0 0x24200000 0x0 0x10000>; + interrupts = ; + status = "disabled"; + }; + + gpu: gpu@2a200000 { + compatible = "arm,mali-midgard", "arm,mali-t628"; + #cooling-cells = <2>; /* min followed by max */ + reg = <0x0 0x2a200000 0x0 0x4000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&cmu_mali>; + clock-names = "gpuclk"; + dma-coherent; + operating-points-v2 = <&gpu_opp_table>; + }; + + /* USB MM: USB2 (2c400000, 100000, SPI_267-268_H, SPI_277_H) */ + usb2: usb2@2c400000 { + compatible = "be,baikal-dwc3"; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&usb_clk>; + clock-names = "usb"; + dma-coherent; + + dwc3@2c400000 { + compatible = "snps,dwc3", "synopsys,dwc3", "generic-xhci"; + reg = <0x0 0x2c400000 0x0 0x100000>; + interrupts = , + , + ; + dr_mode = "host"; + dma-coherent; + maximum-speed = "high-speed"; + }; + }; + + /* USB MM: USB3 (2c500000, 100000, SPI_269-276_H, SPI_278_H) */ + usb3: usb3@2c500000 { + compatible = "be,baikal-dwc3"; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&usb_clk>; + clock-names = "usb"; + + dwc3@2c500000 { + compatible = "snps,dwc3", "synopsys,dwc3", "generic-xhci"; + reg = <0x0 0x2c500000 0x0 0x100000>; + interrupts = , + , + , + , + , + , + , + , + ; + dr_mode = "host"; + dma-coherent; + }; + }; + + /* USB MM: SATA0 (2c600000, 10000, SPI_265_H) */ + sata0: sata0@2c600000 { + compatible = "snps,dwc-ahci", "generic-ahci"; + reg = <0x0 0x2c600000 0 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + ports-implemented = <1>; + dma-coherent; + clocks = <&soc_faxiclk>; + clock-names = "sataclk"; + status = "disabled"; + }; + + /* USB MM: SATA1 (2c610000, 10000, SPI_266_H) */ + sata1: sata1@2c610000 { + compatible = "snps,dwc-ahci", "generic-ahci"; + reg = <0x0 0x2c610000 0 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + ports-implemented = <1>; + dma-coherent; + clocks = <&soc_faxiclk>; + clock-names = "sataclk"; + status = "disabled"; + }; + + /* DMA-330: DMAC ("secure", 2c620000, 10000, SPI_255-263_H) */ + /* ("non-secure", 2c630000, 10000, ?) */ + dma: dma@2c620000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x2c620000 0 0x1000>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + interrupts = , + , + , + , + , + , + , + , + ; + clocks = <&soc_faxiclk>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gic: interrupt-controller@2d000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x2d000000 0x0 0x10000>, /* GICD */ + <0x0 0x2d100000 0x0 0x200000>, /* GICR */ + <0x0 0x10200000 0x0 0x2000>, /* GICC */ + <0x0 0x10210000 0x0 0x1000>, /* GICH */ + <0x0 0x10220000 0x0 0x2000>; /* GICV */ + interrupts = ; + + its: its@2d020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x2d020000 0x0 0x20000>; /* GITS */ + }; + }; + + axi_gmac: stmmac-axi-config0 { + snps,wr_osr_lmt = <0x0>; + snps,rd_osr_lmt = <0x0>; + snps,blen = <0 0 0 0 0 0 4>; + }; + + gmac0: eth0@30240000 { + compatible = "be,dwmac", "snps,dwmac-3.710", "snps,dwmac"; + reg = <0x0 0x30240000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-names = "macirq"; + max-speed = <1000>; + clocks = <&soc_ethclk>, <&cmu0_xgbe 10>; + clock-names = "stmmaceth", "tx2_clk"; + mac-address = [ 00 00 00 00 00 00 ]; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-mode = "rgmii-id"; + phy-handle = <&gmac0_phy>; + snps,fixed-burst; + snps,axi-config = <&axi_gmac>; + snps,no-pbl-x8; + snps,txpbl = <4>; + snps,rxpbl = <4>; + snps,reset-delays-us = <0 10200 1000>; + status = "disabled"; + dma-coherent; + + gmdio0: gmac0_mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + gmac0_phy: ethernet-phy@3 { + compatible = "ethernet-phy-id0022.1620", "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txc-skew-ps = <0xff>; + }; + }; + }; + + gmac1: eth1@30250000 { + compatible = "be,dwmac", "snps,dwmac-3.710", "snps,dwmac"; + reg = <0x0 0x30250000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-names = "macirq"; + max-speed = <1000>; + clocks = <&soc_ethclk>, <&cmu0_xgbe 13>; + clock-names = "stmmaceth", "tx2_clk"; + mac-address = [ 00 00 00 00 00 00 ]; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-mode = "rgmii-id"; + phy-handle = <&gmac1_phy>; + snps,fixed-burst; + snps,axi-config = <&axi_gmac>; + snps,no-pbl-x8; + snps,txpbl = <4>; + snps,rxpbl = <4>; + snps,reset-delays-us = <0 10200 1000>; + status = "disabled"; + dma-coherent; + + gmdio1: gmac1_mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + gmac1_phy: ethernet-phy@3 { + compatible = "ethernet-phy-id0022.1620", "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txc-skew-ps = <0xff>; + }; + }; + }; + + /* Baikal internal MDIO */ + mdio0: be-mdio { + compatible = "be,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + mdc-pin = <&porta 30 GPIO_ACTIVE_HIGH>; + mdio-pin = <&porta 29 GPIO_ACTIVE_HIGH>; + clocks = <&gpio_clk>; + clock-names = "gpioclk"; + + mv_ch0: ethernet-phy@c { + compatible = "marvell,88x2222", "ethernet-phy-ieee802.3-c45"; + reg = <0x0c>; + phy-mode = "xgmii"; + mv,line-mode = "KR"; + mv,host-mode = "KX4"; + }; + + mv_ch2: ethernet-phy@e { + compatible = "marvell,88x2222", "ethernet-phy-ieee802.3-c45"; + reg = <0x0e>; + phy-mode = "xgmii"; + mv,line-mode = "KR"; + mv,host-mode = "KX4"; + }; + }; + + /* XGMAC0 */ + xgmac0: eth2@30200000 { + compatible = "amd,xgbe-seattle-v1a"; + reg = <0x0 0x30200000 0x0 0x10000>, + <0x0 0x30210000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + fsl,num-rx-queues=<3>; + clocks = <&soc_xgbeclk>, <&soc_xgbeclk>, <&soc_xgbeclk>; + clock-names = "dma_clk", "ptp_clk", "xgbe_clk"; + phy-mode = "xgmii"; + mac-address = [ 00 20 13 ba 1c a1 ]; + local-mac-address = [ 00 20 13 ba 1c a1 ]; + be,pcs-mode = "KX4"; + ext-phy-handle = <&mv_ch0>; + status = "disabled"; + amd,per-channel-interrupt; + amd,speed-set = <0>; + #stream-id-cells = <16>; + }; + + /* XGMAC1 */ + xgmac1: eth3@30220000 { + compatible = "amd,xgbe-seattle-v1a"; + reg = <0x0 0x30220000 0x0 0x10000>, + <0x0 0x30230000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + fsl,num-rx-queues=<3>; + clocks = <&soc_xgbeclk>, <&soc_xgbeclk>, <&soc_xgbeclk>; + clock-names = "dma_clk", "ptp_clk", "xgbe_clk"; + phy-mode = "xgmii"; + mac-address = [ 00 20 13 ba 1c a2 ]; + local-mac-address = [ 00 20 13 ba 1c a2 ]; + be,pcs-mode = "KX4"; + ext-phy-handle = <&mv_ch2>; + status = "disabled"; + amd,per-channel-interrupt; + amd,speed-set = <0>; + #stream-id-cells = <16>; + }; + + /* HDMI VDU (30260000, 10000, SPI_361-362_?) */ + vdu1: vdu_hdmi@30260000 { + compatible = "baikal,vdu"; + reg = <0x0 0x30260000 0x0 0x1000>; + interrupts = , /* VDU INTR */ + ; /* VDU INTR_CDD */ + clocks = <&cmu1_xgbe 0>; + clock-names = "pclk"; + status = "disabled"; + + port { + vdu_hdmi_out: endpoint { + remote-endpoint = <&hdmi_tx_in>; + }; + }; + }; + + hdmi: hdmi@30280000 { + compatible = "baikal,hdmi"; + reg = <0 0x30280000 0 0x20000>; + reg-io-width = <4>; + interrupts = ; + clocks = <&cmu0_xgbe 0>, <&cmu0_xgbe 17>; + clock-names = "iahb", "isfr"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hdmi_tx_in: endpoint { + remote-endpoint = <&vdu_hdmi_out>; + }; + }; + port@1 { + reg = <1>; + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + }; /* end of soc node */ + + hdmi-out { + compatible = "hdmi-connector"; + label = "HDMI0 OUT"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; +}; diff --git a/arch/arm64/configs/baikal_minimal_defconfig b/arch/arm64/configs/baikal_minimal_defconfig new file mode 100644 index 000000000000..6c3fe0e3c4db --- /dev/null +++ b/arch/arm64/configs/baikal_minimal_defconfig @@ -0,0 +1,4417 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm64 5.6.0 Kernel Configuration +# + +# +# Compiler: aarch64-linux-gnu-gcc (Ubuntu/Linaro 7.5.0-3ubuntu1~18.04) 7.5.0 +# +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=70500 +CONFIG_CLANG_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_HOSTNAME="" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_USELIB is not set +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_IRQ_MSI_IOMMU=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPTION=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +# CONFIG_PSI_DEFAULT_DISABLED is not set +# end of CPU/Task time and stats accounting + +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +CONFIG_PREEMPT_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# end of RCU Subsystem + +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# CONFIG_UCLAMP_TASK is not set +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_CC_HAS_INT128=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_SWAP_ENABLED=y +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_CGROUP_PIDS=y +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_FREEZER=y +# CONFIG_CGROUP_HUGETLB is not set +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +# CONFIG_CGROUP_BPF is not set +# CONFIG_CGROUP_DEBUG is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +# CONFIG_CHECKPOINT_RESTORE is not set +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_BOOT_CONFIG=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_HAVE_UID16=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_BPF=y +# CONFIG_EXPERT is not set +CONFIG_UID16=y +CONFIG_MULTIUSER=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_HAVE_FUTEX_CMPXCHG=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_BPF_SYSCALL=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y +# CONFIG_BPF_JIT_ALWAYS_ON is not set +CONFIG_BPF_JIT_DEFAULT_ON=y +CONFIG_USERFAULTFD=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_RSEQ=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# end of General setup + +CONFIG_ARM64=y +CONFIG_64BIT=y +CONFIG_MMU=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_CONT_SHIFT=4 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=33 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA32=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_SMP=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=4 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_PROC_KCORE_TEXT=y + +# +# Platform selection +# +# CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_AGILEX is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_ALPINE is not set +CONFIG_ARCH_BAIKAL=y +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_BITMAIN is not set +# CONFIG_ARCH_BRCMSTB is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_K3 is not set +# CONFIG_ARCH_LAYERSCAPE is not set +# CONFIG_ARCH_LG1K is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_REALTEK is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_S32 is not set +# CONFIG_ARCH_SEATTLE is not set +# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_SYNQUACER is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_SPRD is not set +# CONFIG_ARCH_THUNDER is not set +# CONFIG_ARCH_THUNDER2 is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZX is not set +# CONFIG_ARCH_ZYNQMP is not set +# end of Platform selection + +# +# Kernel Features +# + +# +# ARM errata workarounds via the alternatives framework +# +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_832075=y +CONFIG_ARM64_ERRATUM_845719=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_ERRATUM_1024718=y +CONFIG_ARM64_ERRATUM_1418040=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT_VHE=y +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1530923=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT_NVHE=y +CONFIG_ARM64_ERRATUM_1319367=y +CONFIG_ARM64_ERRATUM_1463225=y +CONFIG_ARM64_ERRATUM_1542419=y +CONFIG_CAVIUM_ERRATUM_22375=y +CONFIG_CAVIUM_ERRATUM_23154=y +CONFIG_CAVIUM_ERRATUM_27456=y +CONFIG_CAVIUM_ERRATUM_30115=y +CONFIG_CAVIUM_TX2_ERRATUM_219=y +CONFIG_QCOM_FALKOR_ERRATUM_1003=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_QCOM_FALKOR_ERRATUM_1009=y +CONFIG_QCOM_QDF2400_ERRATUM_0065=y +CONFIG_SOCIONEXT_SYNQUACER_PREITS=y +CONFIG_HISILICON_ERRATUM_161600802=y +CONFIG_QCOM_FALKOR_ERRATUM_E1041=y +CONFIG_FUJITSU_ERRATUM_010001=y +# end of ARM errata workarounds via the alternatives framework + +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_16K_PAGES is not set +# CONFIG_ARM64_64K_PAGES is not set +# CONFIG_ARM64_VA_BITS_39 is not set +CONFIG_ARM64_VA_BITS_48=y +CONFIG_ARM64_VA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PA_BITS=48 +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SCHED_MC=y +# CONFIG_SCHED_SMT is not set +CONFIG_NR_CPUS=8 +CONFIG_HOTPLUG_CPU=y +# CONFIG_NUMA is not set +CONFIG_HOLES_IN_ZONE=y +# CONFIG_HZ_100 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +CONFIG_HZ_1000=y +CONFIG_HZ=1000 +CONFIG_SCHED_HRTICK=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HW_PERF_EVENTS=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_SECCOMP=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +# CONFIG_KEXEC_SIG is not set +# CONFIG_CRASH_DUMP is not set +# CONFIG_XEN is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDEN_EL2_VECTORS=y +CONFIG_ARM64_SSBD=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +# CONFIG_ARM64_SW_TTBR0_PAN is not set +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_COMPAT=y +CONFIG_KUSER_HELPERS=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y + +# +# ARMv8.1 architectural features +# +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_PAN=y +CONFIG_ARM64_LSE_ATOMICS=y +CONFIG_ARM64_USE_LSE_ATOMICS=y +CONFIG_ARM64_VHE=y +# end of ARMv8.1 architectural features + +# +# ARMv8.2 architectural features +# +CONFIG_ARM64_UAO=y +# CONFIG_ARM64_PMEM is not set +CONFIG_ARM64_RAS_EXTN=y +CONFIG_ARM64_CNP=y +# end of ARMv8.2 architectural features + +# +# ARMv8.3 architectural features +# +CONFIG_ARM64_PTR_AUTH=y +# end of ARMv8.3 architectural features + +# +# ARMv8.5 architectural features +# +CONFIG_ARM64_E0PD=y +CONFIG_ARCH_RANDOM=y +# end of ARMv8.5 architectural features + +CONFIG_ARM64_SVE=y +CONFIG_ARM64_MODULE_PLTS=y +# CONFIG_ARM64_PSEUDO_NMI is not set +# CONFIG_RANDOMIZE_BASE is not set +# end of Kernel Features + +# +# Boot options +# +CONFIG_CMDLINE="" +CONFIG_EFI_STUB=y +CONFIG_EFI=y +CONFIG_DMI=y +# end of Boot options + +CONFIG_SYSVIPC_COMPAT=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +CONFIG_PM_STD_PARTITION="" +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_CLK=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_CPU_PM=y +# CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# end of Power management options + +# +# CPU Power Management +# + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set +CONFIG_DT_IDLE_STATES=y + +# +# ARM CPU Idle Drivers +# +CONFIG_ARM_CPUIDLE=y +# CONFIG_ARM_PSCI_CPUIDLE is not set +# end of ARM CPU Idle Drivers +# end of CPU Idle + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_STAT is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=m +CONFIG_CPU_FREQ_GOV_ONDEMAND=m +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y + +# +# CPU frequency scaling drivers +# +CONFIG_CPUFREQ_DT=m +CONFIG_CPUFREQ_DT_PLATDEV=y +# CONFIG_QORIQ_CPUFREQ is not set +# end of CPU Frequency scaling +# end of CPU Power Management + +# +# Firmware Drivers +# +# CONFIG_ARM_SCMI_PROTOCOL is not set +# CONFIG_ARM_SCPI_PROTOCOL is not set +# CONFIG_ARM_SDE_INTERFACE is not set +CONFIG_DMIID=y +# CONFIG_DMI_SYSFS is not set +# CONFIG_FW_CFG_SYSFS is not set +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_VARS=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_VARS_PSTORE=y +# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_ARMSTUB_DTB_LOADER=y +CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y +CONFIG_EFI_BOOTLOADER_CONTROL=y +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# end of EFI (Extensible Firmware Interface) Support + +CONFIG_EFI_EARLYCON=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +CONFIG_ARCH_SUPPORTS_ACPI=y +# CONFIG_ACPI is not set +# CONFIG_VIRTUALIZATION is not set +# CONFIG_ARM64_CRYPTO is not set + +# +# General architecture-dependent options +# +CONFIG_CRASH_CORE=y +CONFIG_KEXEC_CORE=y +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +CONFIG_STATIC_KEYS_SELFTEST=y +CONFIG_UPROBES=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_KRETPROBES=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_KEEPINITRD=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_CC_HAS_STACKPROTECTOR_NONE=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_COMPAT_OLD_SIGACTION=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_PLUGIN_HOSTCC="" +CONFIG_HAVE_GCC_PLUGINS=y +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +CONFIG_MODULE_COMPRESS=y +#CONFIG_MODULE_COMPRESS_GZIP is not set +CONFIG_MODULE_COMPRESS_XZ=y +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_RQ_ALLOC_TIME=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_ZONED is not set +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +# CONFIG_BLK_CMDLINE_PARSER is not set +CONFIG_BLK_WBT=y +CONFIG_BLK_CGROUP_IOLATENCY=y +CONFIG_BLK_CGROUP_IOCOST=y +CONFIG_BLK_WBT_MQ=y +# CONFIG_BLK_DEBUG_FS is not set +# CONFIG_BLK_SED_OPAL is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set +# end of Partition Types + +CONFIG_BLOCK_COMPAT=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +CONFIG_IOSCHED_BFQ=y +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFQ_CGROUP_DEBUG is not set +# end of IO Schedulers + +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +CONFIG_BINFMT_MISC=m +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_FLATMEM_MANUAL is not set +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_MEMORY_HOTPLUG is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_BOUNCE=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +# CONFIG_MEMORY_FAILURE is not set +CONFIG_TRANSPARENT_HUGEPAGE=y +# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +CONFIG_TRANSPARENT_HUGE_PAGECACHE=y +# CONFIG_CLEANCACHE is not set +CONFIG_FRONTSWAP=y +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_AREAS=7 +CONFIG_ZSWAP=y +CONFIG_ZPOOL=y +CONFIG_ZBUD=m +CONFIG_Z3FOLD=m +CONFIG_ZSMALLOC=m +# CONFIG_PGTABLE_MAPPING is not set +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_PTE_DEVMAP=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +# end of Memory Management options + +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_UNIX_DIAG=m +# CONFIG_TLS is not set +# CONFIG_XFRM_USER is not set +# CONFIG_NET_KEY is not set +# CONFIG_XDP_SOCKETS is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=m +# CONFIG_IP_MROUTE is not set +CONFIG_SYN_COOKIES=y +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_DIAG_DESTROY=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_TUNNEL=m +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_MPTCP is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_BPFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_MRP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +# CONFIG_DNS_RESOLVER is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +CONFIG_NETLINK_DIAG=m +# CONFIG_MPLS is not set +# CONFIG_NET_NSH is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +# CONFIG_CGROUP_NET_PRIO is not set +# CONFIG_CGROUP_NET_CLASSID is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_BPF_JIT=y +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_DROP_MONITOR is not set +# end of Network testing +# end of Networking options + +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +CONFIG_PAGE_POOL=y +# CONFIG_FAILOVER is not set +CONFIG_ETHTOOL_NETLINK=y +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_PCIEAER=y +# CONFIG_PCIEAER_INJECT is not set +CONFIG_PCIE_ECRC=y +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +CONFIG_PCIE_PME=y +# CONFIG_PCIE_DPC is not set +CONFIG_PCIE_PTM=y +# CONFIG_PCIE_BW is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=m +# CONFIG_PCI_PF_STUB is not set +CONFIG_PCI_ATS=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +CONFIG_PCI_LABEL=y +CONFIG_HOTPLUG_PCI=y +# CONFIG_HOTPLUG_PCI_CPCI is not set +# CONFIG_HOTPLUG_PCI_SHPC is not set + +# +# PCI controller drivers +# +# CONFIG_PCI_FTPCI100 is not set +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCIE_XILINX is not set +# CONFIG_PCI_XGENE is not set +# CONFIG_PCIE_ALTERA is not set +# CONFIG_PCI_HOST_THUNDER_PEM is not set +# CONFIG_PCI_HOST_THUNDER_ECAM is not set +CONFIG_PCI_BAIKAL=m + +# +# DesignWare PCI Core Support +# +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_DW_PLAT=y +CONFIG_PCIE_DW_PLAT_HOST=y +# CONFIG_PCIE_DW_PLAT_EP is not set +# CONFIG_PCI_HISI is not set +# CONFIG_PCIE_KIRIN is not set +# CONFIG_PCI_MESON is not set +# CONFIG_PCIE_AL is not set +# end of DesignWare PCI Core Support + +# +# Cadence PCIe controllers support +# +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set +# CONFIG_PCIE_CADENCE_PLAT_EP is not set +# end of Cadence PCIe controllers support +# end of PCI controller drivers + +# +# PCI Endpoint +# +CONFIG_PCI_ENDPOINT=y +# CONFIG_PCI_ENDPOINT_CONFIGFS is not set +# CONFIG_PCI_EPF_TEST is not set +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set +# end of PCI switch controller drivers + +# CONFIG_PCCARD is not set +# CONFIG_RAPIDIO is not set + +# +# Generic Driver Options +# +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER is not set +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_CACHE=y +# end of Firmware loader + +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_REGMAP_MMIO=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_GENERIC_ARCH_TOPOLOGY=y +# end of Generic Driver Options + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_MOXTET is not set +# CONFIG_SIMPLE_PM_BUS is not set +# CONFIG_VEXPRESS_CONFIG is not set +# end of Bus devices + +CONFIG_CONNECTOR=m +# CONFIG_GNSS is not set +CONFIG_MTD=m +# CONFIG_MTD_TESTS is not set + +# +# Partition parsers +# +# CONFIG_MTD_AR7_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=m +CONFIG_MTD_OF_PARTS=m +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# end of Partition parsers + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_GEN_PROBE=m +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_INTELEXT is not set +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=m +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# end of RAM/ROM/Flash chip drivers + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set +# end of Mapping drivers for chip access + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# end of Self-contained MTD device drivers + +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_RAW_NAND is not set +# CONFIG_MTD_SPI_NAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# end of LPDDR & LPDDR2 PCM memory drivers + +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_MTK_QUADSPI is not set +# CONFIG_MTD_UBI is not set +# CONFIG_MTD_HYPERBUS is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +CONFIG_CDROM=m +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +CONFIG_ZRAM=m +# CONFIG_ZRAM_WRITEBACK is not set +# CONFIG_ZRAM_MEMORY_TRACKING is not set +# CONFIG_BLK_DEV_UMEM is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SKD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=8 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set + +# +# NVME Support +# +CONFIG_NVME_CORE=m +CONFIG_BLK_DEV_NVME=m +# CONFIG_NVME_MULTIPATH is not set +# CONFIG_NVME_HWMON is not set +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TCP is not set +# CONFIG_NVME_TARGET is not set +# end of NVME Support + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_PVPANIC is not set +CONFIG_TP_BMC=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set +# end of EEPROM support + +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# end of Texas Instruments shared transport line discipline + +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC & related support +# +# CONFIG_VOP_BUS is not set +# end of Intel MIC & related support + +# CONFIG_GENWQE is not set +# CONFIG_ECHO is not set +# CONFIG_MISC_ALCOR_PCI is not set +# CONFIG_MISC_RTSX_PCI is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_HABANA_AI is not set +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR_VENDOR=y +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# end of SCSI Transports + +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# end of SCSI device support + +CONFIG_HAVE_PATA_PLATFORM=y +CONFIG_ATA=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI=y +CONFIG_SATA_MOBILE_LPM_POLICY=0 +CONFIG_SATA_AHCI_PLATFORM=y +# CONFIG_AHCI_CEVA is not set +# CONFIG_AHCI_QORIQ is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_SATA_ACARD_AHCI is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_ATA_SFF is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +# CONFIG_MD_LINEAR is not set +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +# CONFIG_BCACHE is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_BUFIO=m +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_PERSISTENT_DATA=m +# CONFIG_DM_UNSTRIPED is not set +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +# CONFIG_DM_CACHE is not set +# CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_CLONE is not set +CONFIG_DM_MIRROR=m +# CONFIG_DM_LOG_USERSPACE is not set +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_DUST is not set +CONFIG_DM_UEVENT=y +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_DM_INTEGRITY is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# end of IEEE 1394 (FireWire) support + +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +# CONFIG_WIREGUARD is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_NET_TEAM is not set +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +# CONFIG_VXLAN is not set +# CONFIG_GENEVE is not set +# CONFIG_GTP is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +CONFIG_TUN=m +CONFIG_TAP=m +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=m +CONFIG_NLMON=m +# CONFIG_ARCNET is not set + +# +# Distributed Switch Architecture drivers +# +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_STMMAC_ETH=y +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STMMAC_PLATFORM=y +# CONFIG_DWMAC_DWC_QOS_ETH is not set +CONFIG_DWMAC_GENERIC=y +CONFIG_DWMAC_BAIKAL=y +# CONFIG_STMMAC_PCI is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +# CONFIG_MDIO_BCM_UNIMAC is not set +CONFIG_MDIO_BITBANG=m +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +CONFIG_MDIO_GPIO=m +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_THUNDER is not set +CONFIG_PHYLINK=y +CONFIG_PHYLIB=y +CONFIG_SWPHY=y + +# +# MII PHY device drivers +# +# CONFIG_SFP is not set +# CONFIG_ADIN_PHY is not set +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AX88796B_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM84881_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +CONFIG_MARVELL_PHY=m +# CONFIG_MARVELL_10G_PHY is not set +CONFIG_MICREL_PHY=y +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_REALTEK_PHY=m +# CONFIG_RENESAS_PHY is not set +# CONFIG_ROCKCHIP_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +# CONFIG_SLIP is not set +CONFIG_SLHC=m +# CONFIG_USB_NET_DRIVERS is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_NETDEVSIM is not set +# CONFIG_NET_FAILOVER is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=m +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_BCM is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_SMBUS=y +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +# CONFIG_MOUSE_ELAN_I2C is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=m +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_APBPS2 is not set +CONFIG_SERIO_TPLATFORMS=m +# CONFIG_SERIO_GPIO_PS2 is not set +# CONFIG_USERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_NULL_TTY is not set +CONFIG_LDISC_AUTOLOAD=y +CONFIG_DEVMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +# CONFIG_SERIAL_8250_ASPEED_VUART is not set +# CONFIG_SERIAL_8250_SHARE_IRQ is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_DW=y +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_OF_PLATFORM=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_KGDB_NMI is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SIFIVE is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# end of Serial drivers + +CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_CAVIUM is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_XILLYBUS is not set +# end of Character devices + +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=m + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +# CONFIG_I2C_MUX_MLXCPLD is not set +# end of Multiplexer I2C Chip support + +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NVIDIA_GPU is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_CBUS_GPIO is not set +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +# CONFIG_I2C_DESIGNWARE_SLAVE is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_THUNDERX is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# end of I2C Hardware Bus support + +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +CONFIG_SPI_DESIGNWARE=y +# CONFIG_SPI_DW_PCI is not set +CONFIG_SPI_DW_MMIO=y +# CONFIG_SPI_NXP_FLEXSPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SIFIVE is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_THUNDERX is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_SLAVE is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +# CONFIG_PTP_1588_CLOCK_IDTCM is not set +# end of PTP clock support + +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_SX150X is not set +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_EQUILIBRIUM is not set +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_GENERIC=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_CADENCE is not set +CONFIG_GPIO_DWAPB=y +# CONFIG_GPIO_EXAR is not set +# CONFIG_GPIO_FTGPIO010 is not set +CONFIG_GPIO_GENERIC_PLATFORM=y +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +# CONFIG_GPIO_SIFIVE is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_XGENE is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +CONFIG_GPIO_PCF857X=y +# CONFIG_GPIO_TPIC2810 is not set +# end of I2C GPIO expanders + +# +# MFD GPIO expanders +# +# end of MFD GPIO expanders + +# +# PCI GPIO expanders +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_PCI_IDIO_16 is not set +# CONFIG_GPIO_PCIE_IDIO_24 is not set +# CONFIG_GPIO_RDC321X is not set +# end of PCI GPIO expanders + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set +# end of SPI GPIO expanders + +# +# USB GPIO expanders +# +# end of USB GPIO expanders + +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMSTB is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_XGENE is not set +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +# CONFIG_SYSCON_REBOOT_MODE is not set +# CONFIG_NVMEM_REBOOT_MODE is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_MANAGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_CHARGER_RT9455 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM1177 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AS370 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ASPEED is not set +# CONFIG_SENSORS_ATXP1 is not set +CONFIG_SENSORS_BT1_PVT=m +# CONFIG_SENSORS_DRIVETEMP is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2947_I2C is not set +# CONFIG_SENSORS_LTC2947_SPI is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX6621 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP513 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83773G is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +CONFIG_WATCHDOG_SYSFS=y + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_GPIO_WATCHDOG=m +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +# CONFIG_ARM_SBSA_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +CONFIG_DW_WATCHDOG=m +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_I6300ESB_WDT is not set +# CONFIG_MEN_A21_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_UCB1400_CORE is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD70528 is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_MFD_STMFX is not set +# end of Multifunction device drivers + +# CONFIG_REGULATOR is not set +# CONFIG_RC_CORE is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_DRM=y +# CONFIG_DRM_DP_AUX_CHARDEV is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_SELFTEST is not set +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_KMS_FB_HELPER=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +# CONFIG_DRM_DP_CEC is not set +CONFIG_DRM_GEM_CMA_HELPER=y +CONFIG_DRM_KMS_CMA_HELPER=y + +# +# I2C encoder or helper chips +# +# CONFIG_DRM_I2C_CH7006 is not set +# CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# end of I2C encoder or helper chips + +# +# ARM devices +# +# CONFIG_DRM_HDLCD is not set +# CONFIG_DRM_MALI_DISPLAY is not set +# CONFIG_DRM_KOMEDA is not set +# end of ARM devices + +CONFIG_DRM_BAIKAL_VDU=y +# CONFIG_DRM_RADEON is not set +# CONFIG_DRM_AMDGPU is not set + +# +# ACP (Audio CoProcessor) Configuration +# +# end of ACP (Audio CoProcessor) Configuration + +# CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_VKMS is not set +# CONFIG_DRM_UDL is not set +# CONFIG_DRM_AST is not set +# CONFIG_DRM_MGAG200 is not set +# CONFIG_DRM_CIRRUS_QEMU is not set +# CONFIG_DRM_RCAR_DW_HDMI is not set +# CONFIG_DRM_RCAR_LVDS is not set +CONFIG_DRM_RCAR_WRITEBACK=y +# CONFIG_DRM_QXL is not set +# CONFIG_DRM_BOCHS is not set +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +CONFIG_DRM_PANEL_LVDS=y +CONFIG_DRM_PANEL_SIMPLE=y +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_DUMB_VGA_DAC is not set +# CONFIG_DRM_LVDS_CODEC is not set +CONFIG_DRM_BAIKAL_HDMI=y +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +# CONFIG_DRM_NXP_PTN3460 is not set +# CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_SIL_SII8620 is not set +# CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SII9234 is not set +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TOSHIBA_TC358764 is not set +# CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_ANALOGIX_ANX6345 is not set +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_I2C_ADV7511 is not set +CONFIG_DRM_DW_HDMI=y +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +# CONFIG_DRM_DW_HDMI_I2S_AUDIO is not set +# CONFIG_DRM_DW_HDMI_CEC is not set +# end of Display Interface Bridges + +# CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_ARCPGU is not set +# CONFIG_DRM_HISI_HIBMC is not set +# CONFIG_DRM_HISI_KIRIN is not set +# CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_GM12U320 is not set +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set +# CONFIG_DRM_PL111 is not set +# CONFIG_DRM_LIMA is not set +CONFIG_DRM_PANFROST=m +# CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_UVESA is not set +CONFIG_FB_EFI=y +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SM712 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +# CONFIG_LCD_AMS369FG06 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_HX8357 is not set +# CONFIG_LCD_OTM3225A is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +# CONFIG_BACKLIGHT_QCOM_WLED is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# end of Backlight & LCD device support + +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# end of Console display driver support + +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +# end of Graphics support + +CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_DMAENGINE_PCM=m +CONFIG_SND_HWDEP=m +CONFIG_SND_SEQ_DEVICE=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_PCM_TIMER=y +CONFIG_SND_HRTIMER=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_MAX_CARDS=32 +# CONFIG_SND_SUPPORT_OLD_API is not set +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_SEQUENCER=m +# CONFIG_SND_SEQ_DUMMY is not set +CONFIG_SND_SEQUENCER_OSS=m +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_SEQ_MIDI_EVENT=m +CONFIG_SND_SEQ_MIDI=m +CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DRIVERS=y +CONFIG_SND_DUMMY=m +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_AC97_POWER_SAVE is not set +# CONFIG_SND_PCI is not set + +# +# HD-Audio +# +# end of HD-Audio + +CONFIG_SND_HDA_PREALLOC_SIZE=64 +# CONFIG_SND_SPI is not set +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_VARIAX is not set +CONFIG_SND_SOC=m +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_ATMEL_SOC is not set +CONFIG_SND_DESIGNWARE_I2S=m +CONFIG_SND_DESIGNWARE_PCM=y + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# end of SoC Audio for Freescale CPUs + +# CONFIG_SND_I2S_HI6210_I2S is not set +# CONFIG_SND_SOC_IMG is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +# CONFIG_SND_SOC_SOF_TOPLEVEL is not set + +# +# STMicroelectronics STM32 SOC audio support +# +# end of STMicroelectronics STM32 SOC audio support + +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_ZX_TDM is not set +CONFIG_SND_SOC_I2C_AND_SPI=m + +# +# CODEC drivers +# +CONFIG_SND_SOC_AC97_CODEC=m +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_ADAU1761_I2C is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +# CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_ADAU7118_HW is not set +# CONFIG_SND_SOC_ADAU7118_I2C is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4458 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_AK5558 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_BD28623 is not set +# CONFIG_SND_SOC_BT_SCO is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +# CONFIG_SND_SOC_CS35L34 is not set +# CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set +# CONFIG_SND_SOC_CS42L42 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DA7213 is not set +# CONFIG_SND_SOC_DMIC is not set +# CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8316 is not set +# CONFIG_SND_SOC_ES8328_I2C is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_INNO_RK3036 is not set +# CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98357A is not set +# CONFIG_SND_SOC_MAX98504 is not set +# CONFIG_SND_SOC_MAX9867 is not set +# CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MAX98373 is not set +# CONFIG_SND_SOC_MAX9860 is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1789_I2C is not set +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_I2C is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RK3328 is not set +# CONFIG_SND_SOC_RT5616 is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set +# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +CONFIG_SND_SOC_SPDIF=m +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS6424 is not set +# CONFIG_SND_SOC_TDA7419 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +CONFIG_SND_SOC_TLV320AIC3X=m +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_TSCS42XX is not set +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8524 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set +# CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_ZX_AUD96P22 is not set +# CONFIG_SND_SOC_MAX9759 is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +CONFIG_SND_SOC_NAU8822=m +# CONFIG_SND_SOC_NAU8824 is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# end of CODEC drivers + +CONFIG_SND_SIMPLE_CARD_UTILS=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD=m +CONFIG_AC97_BUS=m + +# +# HID support +# +CONFIG_HID=y +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACCUTOUCH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CREATIVE_SB0540 is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_RETRODE is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set +# end of Special HID drivers + +# +# USB HID support +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +# end of USB HID support + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +# end of I2C HID support +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ULPI_BUS=y +# CONFIG_USB_CONN_GPIO is not set +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_PCI=y +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_MON=m + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=m +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD_PLATFORM=m +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_OHCI_HCD=m +CONFIG_USB_OHCI_HCD_PCI=m +CONFIG_USB_OHCI_HCD_PLATFORM=m +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +CONFIG_USB_UAS=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_MUSB_HDRC is not set +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_ULPI=y +CONFIG_USB_DWC3_HOST=y + +# +# Platform Glue Driver Support +# +CONFIG_USB_DWC3_HAPS=y +CONFIG_USB_DWC3_OF_SIMPLE=y +CONFIG_USB_DWC3_BAIKAL=y +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +CONFIG_USB_SERIAL_CH341=m +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +CONFIG_USB_SERIAL_CP210X=m +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +CONFIG_USB_SERIAL_FTDI_SIO=m +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_F8153X is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_METRO is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MXUPORT is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +CONFIG_USB_SERIAL_PL2303=m +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +CONFIG_USB_SERIAL_WWAN=m +CONFIG_USB_SERIAL_OPTION=m +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_XSENS_MT is not set +# CONFIG_USB_SERIAL_WISHBONE is not set +# CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_QT2 is not set +# CONFIG_USB_SERIAL_UPD78F0730 is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_CHAOSKEY is not set + +# +# USB Physical Layer drivers +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y +# end of USB Physical Layer drivers + +# CONFIG_USB_GADGET is not set +# CONFIG_TYPEC is not set +# CONFIG_USB_ROLE_SWITCH is not set +CONFIG_MMC=m +CONFIG_PWRSEQ_EMMC=m +CONFIG_PWRSEQ_SIMPLE=m +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_SDHCI=m +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=m +CONFIG_MMC_SDHCI_OF_ARASAN=m +# CONFIG_MMC_SDHCI_OF_ASPEED is not set +CONFIG_MMC_SDHCI_OF_AT91=m +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +# CONFIG_MMC_SDHCI_CADENCE is not set +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDHCI_MILBEAUT is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_DW is not set +CONFIG_MMC_VUB300=m +CONFIG_MMC_USHC=m +# CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_CQHCI=m +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MMC_SDHCI_XENON is not set +# CONFIG_MMC_SDHCI_OMAP is not set +# CONFIG_MMC_SDHCI_AM654 is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +CONFIG_RTC_DRV_ABEOZ9=m +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12026 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD3078 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +CONFIG_RTC_DRV_PCF2127=y +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_EFI is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_CADENCE is not set +# CONFIG_RTC_DRV_FTRTC010 is not set +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_R7301 is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +# CONFIG_ALTERA_MSGDMA is not set +# CONFIG_AMBA_PL08X is not set +# CONFIG_BCM_SBA_RAID is not set +# CONFIG_DW_AXI_DMAC is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_FSL_QDMA is not set +# CONFIG_HISI_DMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_MV_XOR_V2 is not set +# CONFIG_PL330_DMA is not set +# CONFIG_PLX_DMA is not set +# CONFIG_XILINX_DMA is not set +# CONFIG_XILINX_ZYNQMP_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set +# CONFIG_DW_DMAC is not set +# CONFIG_DW_DMAC_PCI is not set +# CONFIG_DW_EDMA is not set +# CONFIG_DW_EDMA_PCIE is not set +# CONFIG_SF_PDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +# CONFIG_SW_SYNC is not set +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set +# end of DMABUF options + +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VFIO is not set +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_VIRTIO_MENU is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +CONFIG_COMMON_CLK_VERSATILE=y +# CONFIG_CLK_SP810 is not set +# CONFIG_CLK_HSDK is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_XGENE is not set +# CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +# end of Common Clock Framework + +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_DW_APB_TIMER=y +CONFIG_DW_APB_TIMER_OF=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +# CONFIG_FSL_ERRATUM_A008585 is not set +CONFIG_HISILICON_ERRATUM_161010101=y +CONFIG_ARM64_ERRATUM_858921=y +# CONFIG_MICROCHIP_PIT64B is not set +# end of Clock Source drivers + +CONFIG_MAILBOX=y +CONFIG_ARM_MHU=m +# CONFIG_PLATFORM_MHU is not set +# CONFIG_PL320_MBOX is not set +# CONFIG_ALTERA_MBOX is not set +# CONFIG_MAILBOX_TEST is not set +CONFIG_IOMMU_IOVA=y +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +CONFIG_IOMMU_IO_PGTABLE=y +CONFIG_IOMMU_IO_PGTABLE_LPAE=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_OF_IOMMU=y +CONFIG_IOMMU_DMA=y +CONFIG_ARM_SMMU=y +# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y +CONFIG_ARM_SMMU_V3=y + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_VIRTIO is not set +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Aspeed SoC drivers +# +# end of Aspeed SoC drivers + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# CONFIG_QUICC_ENGINE is not set +# CONFIG_FSL_RCPM is not set +# end of NXP/Freescale QorIQ SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Qualcomm SoC drivers +# +# end of Qualcomm SoC drivers + +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# CONFIG_XILINX_VCU is not set +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +# CONFIG_DEVFREQ_GOV_USERSPACE is not set +# CONFIG_DEVFREQ_GOV_PASSIVE is not set + +# +# DEVFREQ Drivers +# +# CONFIG_PM_DEVFREQ_EVENT is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_NTB is not set +# CONFIG_VME_BUS is not set +# CONFIG_PWM is not set + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +# CONFIG_AL_FIC is not set +CONFIG_PARTITION_PERCPU=y +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_BRCMSTB_RESCAL is not set +# CONFIG_RESET_INTEL_GW is not set +# CONFIG_RESET_TI_SYSCON is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_PHY_XGENE is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_CADENCE_DP is not set +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +# CONFIG_PHY_QCOM_USB_HS is not set +# CONFIG_PHY_QCOM_USB_HSIC is not set +# CONFIG_PHY_TUSB1210 is not set +# CONFIG_PHY_INTEL_EMMC is not set +# end of PHY Subsystem + +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_ARM_CCI_PMU is not set +# CONFIG_ARM_CCN is not set +CONFIG_ARM_PMU=y +# CONFIG_ARM_DSU_PMU is not set +# CONFIG_ARM_SPE_PMU is not set +# end of Performance monitor support + +CONFIG_RAS=y + +# +# Android +# +# CONFIG_ANDROID is not set +# end of Android + +# CONFIG_LIBNVDIMM is not set +# CONFIG_DAX is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_FSI is not set +# CONFIG_TEE is not set +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# end of Device Drivers + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_VALIDATE_FS_PARSER is not set +CONFIG_FS_IOMAP=y +# CONFIG_EXT2_FS is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +# CONFIG_CUSE is not set +# CONFIG_VIRTIO_FS is not set +CONFIG_OVERLAY_FS=y +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=866 +CONFIG_FAT_DEFAULT_IOCHARSET="utf8" +CONFIG_FAT_DEFAULT_UTF8=y +# CONFIG_NTFS_FS is not set +# end of DOS/FAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=m +CONFIG_EFIVAR_FS=m +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +# CONFIG_SQUASHFS_ZSTD is not set +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFLATE_COMPRESS=y +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +# CONFIG_PSTORE_LZ4HC_COMPRESS is not set +# CONFIG_PSTORE_842_COMPRESS is not set +# CONFIG_PSTORE_ZSTD_COMPRESS is not set +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +# CONFIG_PSTORE_FTRACE is not set +# CONFIG_PSTORE_RAM is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=m +# CONFIG_NFS_SWAP is not set +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_PNFS_FILE_LAYOUT=m +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +CONFIG_NFS_V4_1_MIGRATION=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_SCSILAYOUT=y +# CONFIG_NFSD_FLEXFILELAYOUT is not set +CONFIG_NFSD_V4_2_INTER_SSC=y +CONFIG_GRACE_PERIOD=m +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_BACKCHANNEL=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DFS_UPCALL=y +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +CONFIG_NLS_CODEPAGE_866=y +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set +# CONFIG_UNICODE is not set +CONFIG_IO_WQ=y +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_BIG_KEYS=y +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +# CONFIG_HARDENED_USERCOPY is not set +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization +# end of Kernel hardening options +# end of Security options + +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Public-key cryptography +# +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_CURVE25519 is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_GCM=y +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_SEQIV=y +# CONFIG_CRYPTO_ECHAINIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CFB is not set +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_ESSIV=m + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=m +# CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S is not set +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +# CONFIG_CRYPTO_LIB_BLAKE2S is not set +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +# CONFIG_CRYPTO_LIB_POLY1305 is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_SHA256=y +# CONFIG_CRYPTO_HW is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set + +# +# Certificates for signature checking +# +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_RAID6_PQ=m +CONFIG_RAID6_PQ_BENCHMARK=y +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +# CONFIG_CORDIC is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +# CONFIG_INDIRECT_PIO is not set +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +# CONFIG_CRC8 is not set +CONFIG_XXHASH=y +CONFIG_AUDIT_GENERIC=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_AUDIT_COMPAT_GENERIC=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_XARRAY_MULTI=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_SWIOTLB=y +CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +# CONFIG_DMA_API_DEBUG is not set +CONFIG_SGL_ALLOC=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_IRQ_POLL=y +CONFIG_LIBFDT=y +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_SG_POOL=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set +# end of Library routines + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_READABLE_ASM is not set +# CONFIG_HEADERS_INSTALL is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x01b6 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_DEBUG_FS=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_KGDB=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KGDB_KDB=y +CONFIG_KDB_DEFAULT_ENABLE=0x1 +# CONFIG_KDB_KEYBOARD is not set +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_UBSAN_ALIGNMENT=y +# end of Generic Kernel Debugging Instruments + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Memory Debugging +# +CONFIG_PAGE_EXTENSION=y +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_OWNER is not set +CONFIG_PAGE_POISONING=y +CONFIG_PAGE_POISONING_NO_SANITY=y +# CONFIG_PAGE_POISONING_ZERO is not set +# CONFIG_DEBUG_PAGE_REF is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_SCHED_STACK_END_CHECK=y +# CONFIG_DEBUG_VM is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_CC_HAS_KASAN_GENERIC=y +# CONFIG_KASAN is not set +CONFIG_KASAN_STACK=1 +# end of Memory Debugging + +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_WQ_WATCHDOG=y +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y +# end of Scheduler Debugging + +# CONFIG_DEBUG_TIMEKEEPING is not set +CONFIG_DEBUG_PREEMPT=y + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_PROVE_LOCKING=y +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y +CONFIG_DEBUG_RWSEMS=y +CONFIG_DEBUG_LOCK_ALLOC=y +CONFIG_LOCKDEP=y +# CONFIG_DEBUG_LOCKDEP is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +CONFIG_TRACE_IRQFLAGS=y +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_HAVE_DEBUG_BUGVERBOSE=y + +# +# Debug kernel data structures +# +CONFIG_DEBUG_LIST=y +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +CONFIG_PROVE_RCU=y +# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_LATENCYTOP=y +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_PREEMPTIRQ_TRACEPOINTS=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_BOOTTIME_TRACING is not set +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_DYNAMIC_FTRACE=y +# CONFIG_FUNCTION_PROFILER is not set +CONFIG_STACK_TRACER=y +# CONFIG_PREEMPTIRQ_EVENTS is not set +CONFIG_IRQSOFF_TRACER=y +# CONFIG_PREEMPT_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_HWLAT_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_TRACER_SNAPSHOT=y +CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_KPROBE_EVENTS=y +CONFIG_UPROBE_EVENTS=y +CONFIG_BPF_EVENTS=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_PROBE_EVENTS=y +# CONFIG_BPF_KPROBE_OVERRIDE is not set +CONFIG_FTRACE_MCOUNT_RECORD=y +# CONFIG_HIST_TRIGGERS is not set +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_SAMPLES is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +CONFIG_STRICT_DEVMEM=y +CONFIG_IO_STRICT_DEVMEM=y + +# +# arm64 Debugging +# +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set +# CONFIG_DEBUG_WX is not set +# CONFIG_DEBUG_ALIGN_RODATA is not set +# CONFIG_ARM64_RELOC_TEST is not set +# CONFIG_CORESIGHT is not set +# end of arm64 Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +# CONFIG_MEMTEST is not set +# end of Kernel Testing and Coverage +# end of Kernel hacking diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e42312121e51..aecbb26b7fb5 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_COMMON_CLK_AT91) += at91/ obj-$(CONFIG_ARCH_ARTPEC) += axis/ obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ obj-$(CONFIG_CLK_BAIKAL_T1) += baikal-t1/ +obj-$(CONFIG_ARCH_BAIKAL) += baikal/ obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_ARCH_DAVINCI) += davinci/ diff --git a/drivers/clk/baikal/Makefile b/drivers/clk/baikal/Makefile new file mode 100644 index 000000000000..56aa4de4081c --- /dev/null +++ b/drivers/clk/baikal/Makefile @@ -0,0 +1 @@ +obj-y += clk-baikal.o \ No newline at end of file diff --git a/drivers/clk/baikal/clk-baikal.c b/drivers/clk/baikal/clk-baikal.c new file mode 100644 index 000000000000..5f285a2965bf --- /dev/null +++ b/drivers/clk/baikal/clk-baikal.c @@ -0,0 +1,363 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * clk-baikal.c - Baikal-M clock driver. + * + * Copyright (C) 2015,2016,2020,2021 Baikal Electronics JSC + * Author: Ekaterina Skachko + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CMU_PLL_SET_RATE 0 +#define CMU_PLL_GET_RATE 1 +#define CMU_PLL_ENABLE 2 +#define CMU_PLL_DISABLE 3 +#define CMU_PLL_ROUND_RATE 4 +#define CMU_PLL_IS_ENABLED 5 +#define CMU_CLK_CH_SET_RATE 6 +#define CMU_CLK_CH_GET_RATE 7 +#define CMU_CLK_CH_ENABLE 8 +#define CMU_CLK_CH_DISABLE 9 +#define CMU_CLK_CH_ROUND_RATE 10 +#define CMU_CLK_CH_IS_ENABLED 11 + +struct baikal_clk_cmu { + struct clk_hw hw; + uint32_t cmu_id; + unsigned int parent; + const char *name; + uint32_t is_clk_ch; +}; + +#define to_baikal_cmu(_hw) container_of(_hw, struct baikal_clk_cmu, hw) + +/* Pointer to the place on handling SMC CMU calls in monitor */ +#define BAIKAL_SMC_LCRU_ID 0x82000000 + +static int baikal_clk_enable(struct clk_hw *hw) +{ + struct arm_smccc_res res; + struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); + uint32_t cmd; + + if (pclk->is_clk_ch) { + cmd = CMU_CLK_CH_ENABLE; + } else { + cmd = CMU_PLL_ENABLE; + } + + /* If clock valid */ + arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, 0, + pclk->parent, 0, 0, 0, &res); + + pr_debug("%s(%s, %s@0x%x): %s\n", + __func__, + pclk->name, + pclk->is_clk_ch ? "clkch" : "pll", + pclk->cmu_id, + res.a0 ? "error" : "ok"); + + return res.a0; +} + +static void baikal_clk_disable(struct clk_hw *hw) +{ + struct arm_smccc_res res; + struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); + uint32_t cmd; + + if (pclk->is_clk_ch) { + cmd = CMU_CLK_CH_DISABLE; + } else { + cmd = CMU_PLL_DISABLE; + } + + /* If clock valid */ + arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, 0, + pclk->parent, 0, 0, 0, &res); + + pr_debug("%s(%s, %s@0x%x): %s\n", + __func__, + pclk->name, + pclk->is_clk_ch ? "clkch" : "pll", + pclk->cmu_id, + res.a0 ? "error" : "ok"); +} + +static int baikal_clk_is_enabled(struct clk_hw *hw) +{ + struct arm_smccc_res res; + struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); + uint32_t cmd; + + if (pclk->is_clk_ch) { + cmd = CMU_CLK_CH_IS_ENABLED; + } else { + cmd = CMU_PLL_IS_ENABLED; + } + + /* If clock valid */ + arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, 0, + pclk->parent, 0, 0, 0, &res); + + pr_debug("%s(%s, %s@0x%x): %s\n", + __func__, + pclk->name, + pclk->is_clk_ch ? "clkch" : "pll", + pclk->cmu_id, + res.a0 ? "true" : "false"); + + return res.a0; +} + +static unsigned long baikal_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct arm_smccc_res res; + struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); + uint32_t cmd; + unsigned long parent; + + if (pclk->is_clk_ch) { + cmd = CMU_CLK_CH_GET_RATE; + parent = pclk->parent; + } else { + cmd = CMU_PLL_GET_RATE; + parent= parent_rate; + } + + /* If clock valid */ + arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, 0, + parent, 0, 0, 0, &res); + + pr_debug("%s(%s, %s@0x%x): %ld Hz\n", + __func__, + pclk->name, + pclk->is_clk_ch ? "clkch" : "pll", + pclk->cmu_id, + res.a0); + + /* Return actual freq */ + return res.a0; +} + +static int baikal_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct arm_smccc_res res; + struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); + uint32_t cmd; + unsigned long parent; + + if (pclk->is_clk_ch) { + cmd = CMU_CLK_CH_SET_RATE; + parent = pclk->parent; + } else { + cmd = CMU_PLL_SET_RATE; + parent = parent_rate; + } + + arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, rate, + parent, 0, 0, 0, &res); + + pr_debug("%s(%s, %s@0x%x, %ld Hz): %s\n", + __func__, + pclk->name, + pclk->is_clk_ch ? "clkch" : "pll", + pclk->cmu_id, + rate, + res.a0 ? "error" : "ok"); + + return res.a0; +} + +static long baikal_clk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct arm_smccc_res res; + struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); + unsigned long parent; + uint32_t cmd; + + if (pclk->is_clk_ch) { + cmd = CMU_CLK_CH_ROUND_RATE; + parent = pclk->parent; + } else { + cmd = CMU_PLL_ROUND_RATE; + parent = *prate; + } + + /* If clock valid */ + arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, rate, + parent, 0, 0, 0, &res); + + pr_debug("%s(%s, %s@0x%x): %ld Hz\n", + __func__, + pclk->name, + pclk->is_clk_ch ? "clkch" : "pll", + pclk->cmu_id, + res.a0); + + /* Return actual freq */ + return res.a0; +} + +static const struct clk_ops be_clk_pll_ops = { + .enable = baikal_clk_enable, + .disable = baikal_clk_disable, + .is_enabled = baikal_clk_is_enabled, + .recalc_rate = baikal_clk_recalc_rate, + .set_rate = baikal_clk_set_rate, + .round_rate = baikal_clk_round_rate +}; + +static int __init baikal_clk_probe(struct device_node *node) +{ + struct clk_init_data init; + struct clk_init_data *init_ch; + struct baikal_clk_cmu *cmu; + struct baikal_clk_cmu **cmu_ch; + + struct clk *clk; + struct clk_onecell_data *clk_ch; + + int number, i = 0; + u32 rc, index; + struct property *prop; + const __be32 *p; + const char *clk_ch_name; + const char *parent_name; + + cmu = kzalloc(sizeof(struct baikal_clk_cmu), GFP_KERNEL); + if (!cmu) { + pr_err("%s: could not allocate CMU clk\n", __func__); + return -ENOMEM; + } + + of_property_read_string(node, "clock-output-names", &cmu->name); + of_property_read_u32(node, "clock-frequency", &cmu->parent); + of_property_read_u32(node, "cmu-id", &cmu->cmu_id); + + parent_name = of_clk_get_parent_name(node, 0); + + /* Setup clock init structure */ + init.parent_names = &parent_name; + init.num_parents = 1; + init.name = cmu->name; + init.ops = &be_clk_pll_ops; + init.flags = CLK_IGNORE_UNUSED; + + cmu->hw.init = &init; + cmu->is_clk_ch = 0; + + /* Register the clock */ + pr_debug("%s: add %s, parent %s\n", __func__, cmu->name, parent_name ? parent_name : "null"); + clk = clk_register(NULL, &cmu->hw); + + if (IS_ERR(clk)) { + pr_err("%s: could not register clk %s\n", __func__, cmu->name); + return -ENOMEM; + } + + /* Register the clock for lookup */ + rc = clk_register_clkdev(clk, cmu->name, NULL); + if (rc != 0) { + pr_err("%s: could not register lookup clk %s\n", + __func__, cmu->name); + } + + /* FIXME We probably SHOULDN'T enable it here */ + clk_prepare_enable(clk); + + number = of_property_count_u32_elems(node, "clock-indices"); + + if (number > 0) { + clk_ch = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); + if (!clk_ch) { + pr_err("%s: could not allocate CMU clk channel\n", __func__); + return -ENOMEM; + } + + /* Get the last index to find out max number of children*/ + of_property_for_each_u32(node, "clock-indices", prop, p, index) { + ; + } + + clk_ch->clks = kcalloc(index + 1, sizeof(struct clk *), GFP_KERNEL); + clk_ch->clk_num = index + 1; + cmu_ch = kcalloc((index + 1), sizeof(struct baikal_clk_cmu *), GFP_KERNEL); + if (!cmu_ch) { + kfree(clk_ch); + return -ENOMEM; + } + init_ch = kcalloc((number + 1), sizeof(struct clk_init_data), GFP_KERNEL); + if (!init_ch) { + pr_err("%s: could not allocate CMU init structure \n", __func__); + kfree(cmu_ch); + kfree(clk_ch); + return -ENOMEM; + } + + of_property_for_each_u32(node, "clock-indices", prop, p, index) { + of_property_read_string_index(node, "clock-names", + i, &clk_ch_name); + pr_info("%s: clkch <%s>, index %d, i %d\n", __func__, clk_ch_name, index, i); + init_ch[i].parent_names = &cmu->name; + init_ch[i].num_parents = 1; + init_ch[i].name = clk_ch_name; + init_ch[i].ops = &be_clk_pll_ops; + init_ch[i].flags = CLK_IGNORE_UNUSED; + + cmu_ch[index] = kzalloc(sizeof(struct baikal_clk_cmu), GFP_KERNEL); + if (!cmu_ch[index]) { + pr_err("%s: could not allocate baikal_clk_cmu structure\n", __func__); + return -ENOMEM; + } + cmu_ch[index]->name = clk_ch_name; + cmu_ch[index]->cmu_id = index; + cmu_ch[index]->parent = cmu->cmu_id; + cmu_ch[index]->is_clk_ch = 1; + cmu_ch[index]->hw.init = &init_ch[i]; + clk_ch->clks[index] = clk_register(NULL, &cmu_ch[index]->hw); + + if (IS_ERR(clk_ch->clks[index])) { + pr_err("%s: could not register clk %s\n", __func__, clk_ch_name); + } + + /* Register the clock for lookup */ + rc = clk_register_clkdev(clk_ch->clks[index], clk_ch_name, NULL); + if (rc != 0) { + pr_err("%s: could not register lookup clk %s\n", + __func__, clk_ch_name); + } + + /* FIXME We probably SHOULDN'T enable it here */ + clk_prepare_enable(clk_ch->clks[index]); + i++; + } + + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_ch); + } + + return of_clk_add_provider(node, of_clk_src_simple_get, clk); +} + +static void __init baikal_clk_init(struct device_node *np) +{ + int err; + err = baikal_clk_probe(np); + if (err) { + panic("%s: failed to probe clock %pOF: %d\n", __func__, np, err); + } else { + pr_info("%s: successfully probed %pOF\n", __func__, np); + } +} +CLK_OF_DECLARE_DRIVER(baikal_cmu, "baikal,cmu", baikal_clk_init); diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index ca1d103ec449..29b14e8d7b6b 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -105,6 +105,8 @@ static const struct of_device_id blocklist[] __initconst = { { .compatible = "arm,vexpress", }, + { .compatible = "baikal,baikal-m", }, + { .compatible = "calxeda,highbank", }, { .compatible = "calxeda,ecx-2000", }, diff --git a/drivers/firmware/efi/libstub/arm64-stub.c b/drivers/firmware/efi/libstub/arm64-stub.c index 2363fee9211c..6bcc155c7d1c 100644 --- a/drivers/firmware/efi/libstub/arm64-stub.c +++ b/drivers/firmware/efi/libstub/arm64-stub.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include "efistub.h" @@ -34,6 +35,31 @@ efi_status_t check_platform_features(void) return EFI_SUCCESS; } +static const char* machines_need_low_alloc[] = { + "baikal,baikal-m", +}; + +static bool need_low_alloc(void) { + size_t i; + const void *fdt; + const char *match; + + fdt = get_efi_config_table(DEVICE_TREE_GUID); + if (!fdt) { + efi_info("failed to retrive FDT from EFI\n"); + return false; + } + + for (i = 0; i < ARRAY_SIZE(machines_need_low_alloc); i++) { + match = machines_need_low_alloc[i]; + if (fdt_node_check_compatible(fdt, 0, match) == 0) { + efi_info("machine %s: forcing kernel relocation to low address\n", match); + return true; + } + } + return false; +} + /* * Distro versions of GRUB may ignore the BSS allocation entirely (i.e., fail * to provide space, and fail to zero it). Check for this condition by double @@ -79,6 +105,19 @@ static bool check_image_region(u64 base, u64 size) return ret; } +static inline efi_status_t efi_low_alloc(unsigned long size, unsigned long align, + unsigned long *addr) +{ + /* + * Don't allocate at 0x0. It will confuse code that + * checks pointers against NULL. Skip the first 8 + * bytes so we start at a nice even number. + */ + return efi_low_alloc_above(size, align, addr, 0x8); +} + + + efi_status_t handle_kernel_image(unsigned long *image_addr, unsigned long *image_size, unsigned long *reserve_addr, @@ -99,6 +138,14 @@ efi_status_t handle_kernel_image(unsigned long *image_addr, */ u64 min_kimg_align = efi_nokaslr ? MIN_KIMG_ALIGN : EFI_KIMG_ALIGN; + bool force_low_reloc = need_low_alloc(); + if (force_low_reloc) { + if (!efi_nokaslr) { + efi_info("booting on a broken firmware, KASLR will be disabled\n"); + efi_nokaslr = true; + } + } + if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) { if (!efi_nokaslr) { status = efi_get_random_bytes(sizeof(phys_seed), @@ -112,7 +159,8 @@ efi_status_t handle_kernel_image(unsigned long *image_addr, efi_nokaslr = true; } } else { - efi_info("KASLR disabled on kernel command line\n"); + if (!force_low_reloc) + efi_info("KASLR disabled on kernel command line\n"); } } @@ -140,6 +188,15 @@ efi_status_t handle_kernel_image(unsigned long *image_addr, status = EFI_OUT_OF_RESOURCES; } + if (force_low_reloc) { + status = efi_low_alloc(*reserve_size, + min_kimg_align, + reserve_addr); + if (status != EFI_SUCCESS) { + efi_err("Failed to relocate kernel, expect secondary CPUs boot failure\n"); + } + } + if (status != EFI_SUCCESS) { if (!check_image_region((u64)_text, kernel_memsize)) { efi_err("FIRMWARE BUG: Image BSS overlaps adjacent EFI memory region\n"); @@ -164,6 +221,9 @@ efi_status_t handle_kernel_image(unsigned long *image_addr, } *image_addr = *reserve_addr; + if (efi_nokaslr) { + efi_info("relocating kernel to 0x%lx\n", *image_addr); + } memcpy((void *)*image_addr, _text, kernel_size); return EFI_SUCCESS; diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 0039df26854b..40a8fd58388a 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -236,6 +236,7 @@ config DRM_SCHED source "drivers/gpu/drm/i2c/Kconfig" source "drivers/gpu/drm/arm/Kconfig" +source "drivers/gpu/drm/baikal/Kconfig" config DRM_RADEON tristate "ATI Radeon" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 0dff40bb863c..56244cba2e06 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -127,3 +127,4 @@ obj-$(CONFIG_DRM_TIDSS) += tidss/ obj-y += xlnx/ obj-y += gud/ obj-$(CONFIG_DRM_HYPERV) += hyperv/ +obj-$(CONFIG_DRM_BAIKAL_VDU) += baikal/ diff --git a/drivers/gpu/drm/baikal/Kconfig b/drivers/gpu/drm/baikal/Kconfig new file mode 100644 index 000000000000..7f3661ae5578 --- /dev/null +++ b/drivers/gpu/drm/baikal/Kconfig @@ -0,0 +1,15 @@ +config DRM_BAIKAL_VDU + tristate "DRM Support for Baikal-M VDU" + depends on DRM + depends on ARM || ARM64 || COMPILE_TEST + depends on COMMON_CLK + default y if ARCH_BAIKAL + select DRM_KMS_HELPER + select DRM_KMS_CMA_HELPER + select DRM_GEM_CMA_HELPER + select DRM_PANEL + select DRM_BAIKAL_HDMI + select VT_HW_CONSOLE_BINDING if FRAMEBUFFER_CONSOLE + help + Choose this option for DRM support for the Baikal-M Video Display Unit (VDU). + If M is selected the module will be called baikal_vdu_drm. diff --git a/drivers/gpu/drm/baikal/Makefile b/drivers/gpu/drm/baikal/Makefile new file mode 100644 index 000000000000..eb029494e823 --- /dev/null +++ b/drivers/gpu/drm/baikal/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +baikal_vdu_drm-y += baikal_vdu_connector.o \ + baikal_vdu_crtc.o \ + baikal_vdu_drv.o \ + baikal_vdu_plane.o + +baikal_vdu_drm-$(CONFIG_DEBUG_FS) += baikal_vdu_debugfs.o + +obj-$(CONFIG_DRM_BAIKAL_VDU) += baikal_vdu_drm.o +obj-$(CONFIG_DRM_BAIKAL_HDMI) += baikal-hdmi.o diff --git a/drivers/gpu/drm/baikal/baikal-hdmi.c b/drivers/gpu/drm/baikal/baikal-hdmi.c new file mode 100644 index 000000000000..6a55d03d93f8 --- /dev/null +++ b/drivers/gpu/drm/baikal/baikal-hdmi.c @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Baikal Electronics BE-M1000 DesignWare HDMI 2.0 Tx PHY support driver + * + * Copyright (C) 2019-2021 Baikal Electronics JSC + * + * Author: Pavel Parkhomenko + * + * Parts of this file were based on sources as follows: + * + * Copyright (C) 2016 Renesas Electronics Corporation + * + * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) + */ + +#include +#include +#include + +#include + +int fixed_clock = 0; +int max_clock = 0; + +static const struct dw_hdmi_mpll_config baikal_hdmi_mpll_cfg[] = { + /* pixelclk opmode gmp */ + { 44900000, { { 0x00b3, 0x0000 }, }, }, + { 90000000, { { 0x0072, 0x0001 }, }, }, + { 182750000, { { 0x0051, 0x0002 }, }, }, + { 340000000, { { 0x0040, 0x0003 }, }, }, + { 594000000, { { 0x1a40, 0x0003 }, }, }, + { ~0UL, { { 0x0000, 0x0000 }, }, } +}; + +static const struct dw_hdmi_curr_ctrl baikal_hdmi_cur_ctr[] = { + /* pixelclk current */ + { 44900000, { 0x0000, }, }, + { 90000000, { 0x0008, }, }, + { 182750000, { 0x001b, }, }, + { 340000000, { 0x0036, }, }, + { 594000000, { 0x003f, }, }, + { ~0UL, { 0x0000, }, } +}; + +static const struct dw_hdmi_phy_config baikal_hdmi_phy_cfg[] = { + /* pixelclk symbol term vlev */ + { 148250000, 0x8009, 0x0004, 0x0232}, + { 218250000, 0x8009, 0x0004, 0x0230}, + { 288000000, 0x8009, 0x0004, 0x0273}, + { 340000000, 0x8029, 0x0004, 0x0273}, + { 594000000, 0x8039, 0x0004, 0x014a}, + { ~0UL, 0x0000, 0x0000, 0x0000} +}; + +static enum drm_mode_status baikal_hdmi_mode_valid(struct dw_hdmi *hdmi, + void *data, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + if (mode->clock < 13500) + return MODE_CLOCK_LOW; + if (mode->clock >= 340000) + return MODE_CLOCK_HIGH; + if (fixed_clock && mode->clock != fixed_clock) + return MODE_BAD; + if (max_clock && mode->clock > max_clock) + return MODE_BAD; + + return MODE_OK; +} + +static struct dw_hdmi_plat_data baikal_dw_hdmi_plat_data = { + .mpll_cfg = baikal_hdmi_mpll_cfg, + .cur_ctr = baikal_hdmi_cur_ctr, + .phy_config = baikal_hdmi_phy_cfg, + .mode_valid = baikal_hdmi_mode_valid, +}; + +static int baikal_dw_hdmi_probe(struct platform_device *pdev) +{ + struct dw_hdmi *hdmi; + hdmi = dw_hdmi_probe(pdev, &baikal_dw_hdmi_plat_data); + if (IS_ERR(hdmi)) { + return PTR_ERR(hdmi); + } else { + return 0; + } +} + +static int baikal_dw_hdmi_remove(struct platform_device *pdev) +{ + struct dw_hdmi *hdmi = platform_get_drvdata(pdev); + dw_hdmi_remove(hdmi); + return 0; +} + +static const struct of_device_id baikal_dw_hdmi_of_table[] = { + { .compatible = "baikal,hdmi" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, baikal_dw_hdmi_of_table); + +static struct platform_driver baikal_dw_hdmi_platform_driver = { + .probe = baikal_dw_hdmi_probe, + .remove = baikal_dw_hdmi_remove, + .driver = { + .name = "baikal-dw-hdmi", + .of_match_table = baikal_dw_hdmi_of_table, + }, +}; + +module_param(fixed_clock, int, 0644); +module_param(max_clock, int, 0644); + +module_platform_driver(baikal_dw_hdmi_platform_driver); + +MODULE_AUTHOR("Pavel Parkhomenko "); +MODULE_DESCRIPTION("Baikal BE-M1000 SoC DesignWare HDMI 2.0 Tx + Gen2 PHY Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/baikal/baikal_vdu_connector.c b/drivers/gpu/drm/baikal/baikal_vdu_connector.c new file mode 100644 index 000000000000..2f20cf3da627 --- /dev/null +++ b/drivers/gpu/drm/baikal/baikal_vdu_connector.c @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2019-2020 Baikal Electronics JSC + * + * Author: Pavel Parkhomenko + * + * Parts of this file were based on sources as follows: + * + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * Copyright (C) 2011 Texas Instruments + * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. + * + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms of + * such GNU licence. + * + */ + +/** + * baikal_vdu_connector.c + * Implementation of the connector functions for Baikal Electronics BE-M1000 SoC's VDU + */ +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "baikal_vdu_drm.h" +#include "baikal_vdu_regs.h" + +#define to_baikal_vdu_private(x) \ + container_of(x, struct baikal_vdu_private, connector) + +static void baikal_vdu_drm_connector_destroy(struct drm_connector *connector) +{ + drm_connector_unregister(connector); + drm_connector_cleanup(connector); +} + +static enum drm_connector_status baikal_vdu_drm_connector_detect( + struct drm_connector *connector, bool force) +{ + struct baikal_vdu_private *priv = to_baikal_vdu_private(connector); + + return (priv->panel ? + connector_status_connected : + connector_status_disconnected); +} + +static int baikal_vdu_drm_connector_helper_get_modes( + struct drm_connector *connector) +{ + struct baikal_vdu_private *priv = to_baikal_vdu_private(connector); + + if (!priv->panel) + return 0; + + return drm_panel_get_modes(priv->panel, connector); +} + +const struct drm_connector_funcs connector_funcs = { + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = baikal_vdu_drm_connector_destroy, + .detect = baikal_vdu_drm_connector_detect, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +const struct drm_connector_helper_funcs connector_helper_funcs = { + .get_modes = baikal_vdu_drm_connector_helper_get_modes, +}; + +static const struct drm_encoder_funcs encoder_funcs = { + .destroy = drm_encoder_cleanup, +}; + +int baikal_vdu_lvds_connector_create(struct drm_device *dev) +{ + struct baikal_vdu_private *priv = dev->dev_private; + struct drm_connector *connector = &priv->connector; + struct drm_encoder *encoder = &priv->encoder; + int ret = 0; + + ret = drm_connector_init(dev, connector, &connector_funcs, + DRM_MODE_CONNECTOR_LVDS); + if (ret) { + dev_err(dev->dev, "drm_connector_init failed: %d\n", ret); + goto out; + } + drm_connector_helper_add(connector, &connector_helper_funcs); + ret = drm_encoder_init(dev, encoder, &encoder_funcs, + DRM_MODE_ENCODER_LVDS, NULL); + if (ret) { + dev_err(dev->dev, "drm_encoder_init failed: %d\n", ret); + goto out; + } + encoder->crtc = &priv->crtc; + encoder->possible_crtcs = drm_crtc_mask(encoder->crtc); + ret = drm_connector_attach_encoder(connector, encoder); + if (ret) { + dev_err(dev->dev, "drm_connector_attach_encoder failed: %d\n", ret); + goto out; + } + ret = drm_connector_register(connector); + if (ret) { + dev_err(dev->dev, "drm_connector_register failed: %d\n", ret); + goto out; + } +out: + return ret; +} diff --git a/drivers/gpu/drm/baikal/baikal_vdu_crtc.c b/drivers/gpu/drm/baikal/baikal_vdu_crtc.c new file mode 100644 index 000000000000..039150c593e9 --- /dev/null +++ b/drivers/gpu/drm/baikal/baikal_vdu_crtc.c @@ -0,0 +1,337 @@ +/* + * Copyright (C) 2019-2020 Baikal Electronics JSC + * + * Author: Pavel Parkhomenko + * + * Parts of this file were based on sources as follows: + * + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * Copyright (C) 2011 Texas Instruments + * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. + * + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms of + * such GNU licence. + * + */ + +/** + * baikal_vdu_crtc.c + * Implementation of the CRTC functions for Baikal Electronics BE-M1000 VDU driver + */ +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "baikal_vdu_drm.h" +#include "baikal_vdu_regs.h" + +struct baikal_vdu_crtc_mode_fixup { + int vdisplay; + int vfp_add; +}; + +static const struct baikal_vdu_crtc_mode_fixup mode_fixups[] = { + { 480, 38 }, + { 600, 8 }, + { 720, 43 }, + { 768, 43 }, + { 800, 71 }, + { 864, 71 }, + { 900, 71 }, + { 960, 71 }, + { 1024, 25 }, + { 1050, 25 }, + { 1080, 8 }, + { 1200, 32 }, + { 1440, 27 }, + { ~0U }, +}; + +irqreturn_t baikal_vdu_irq(int irq, void *data) +{ + struct drm_device *drm = data; + struct baikal_vdu_private *priv = drm->dev_private; + irqreturn_t status = IRQ_NONE; + u32 raw_stat; + u32 irq_stat; + + irq_stat = readl(priv->regs + IVR); + raw_stat = readl(priv->regs + ISR); + + if (irq_stat & INTR_VCT) { + priv->counters[10]++; + drm_crtc_handle_vblank(&priv->crtc); + status = IRQ_HANDLED; + } + + if (irq_stat & INTR_FER) { + priv->counters[11]++; + priv->counters[12] = readl(priv->regs + DBAR); + priv->counters[13] = readl(priv->regs + DCAR); + priv->counters[14] = readl(priv->regs + MRR); + status = IRQ_HANDLED; + } + + priv->counters[3] |= raw_stat; + + /* Clear all interrupts */ + writel(irq_stat, priv->regs + ISR); + + return status; +} + +bool baikal_vdu_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct baikal_vdu_private *priv = crtc->dev->dev_private; + + memcpy(adjusted_mode, mode, sizeof(*mode)); + + if (!priv->mode_fixup) + return true; + + if (priv->mode_fixup == -1) { + const struct baikal_vdu_crtc_mode_fixup *fixups = mode_fixups; + for (; fixups && fixups->vdisplay != ~0U; ++fixups) { + if (mode->vdisplay <= fixups->vdisplay) + break; + } + if (fixups->vdisplay == ~0U) + return true; + else + priv->mode_fixup = fixups->vfp_add; + } + + adjusted_mode->vtotal += priv->mode_fixup; + adjusted_mode->vsync_start += priv->mode_fixup; + adjusted_mode->vsync_end += priv->mode_fixup; + adjusted_mode->clock = mode->clock * adjusted_mode->vtotal / mode->vtotal; + + return true; +} + +static void baikal_vdu_crtc_helper_mode_set_nofb(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct baikal_vdu_private *priv = dev->dev_private; + const struct drm_display_mode *orig_mode = &crtc->state->mode; + const struct drm_display_mode *mode = &crtc->state->adjusted_mode; + unsigned int ppl, hsw, hfp, hbp; + unsigned int lpp, vsw, vfp, vbp; + unsigned int reg; + + drm_mode_debug_printmodeline(orig_mode); + drm_mode_debug_printmodeline(mode); + + ppl = mode->hdisplay / 16; + if (priv->panel) { + hsw = mode->hsync_end - mode->hsync_start; + hfp = mode->hsync_start - mode->hdisplay - 1; + } else { + hsw = mode->hsync_end - mode->hsync_start - 1; + hfp = mode->hsync_start - mode->hdisplay; + } + hbp = mode->htotal - mode->hsync_end; + + lpp = mode->vdisplay; + vsw = mode->vsync_end - mode->vsync_start; + vfp = mode->vsync_start - mode->vdisplay; + vbp = mode->vtotal - mode->vsync_end; + + writel((HTR_HFP(hfp) & HTR_HFP_MASK) | + (HTR_PPL(ppl) & HTR_PPL_MASK) | + (HTR_HBP(hbp) & HTR_HBP_MASK) | + (HTR_HSW(hsw) & HTR_HSW_MASK), + priv->regs + HTR); + + if (mode->hdisplay > 4080 || ppl * 16 != mode->hdisplay) + writel((HPPLOR_HPPLO(mode->hdisplay) & HPPLOR_HPPLO_MASK) | HPPLOR_HPOE, + priv->regs + HPPLOR); + + writel((VTR1_VSW(vsw) & VTR1_VSW_MASK) | + (VTR1_VFP(vfp) & VTR1_VFP_MASK) | + (VTR1_VBP(vbp) & VTR1_VBP_MASK), + priv->regs + VTR1); + + writel(lpp & VTR2_LPP_MASK, priv->regs + VTR2); + + writel((HVTER_VSWE(vsw >> VTR1_VSW_LSB_WIDTH) & HVTER_VSWE_MASK) | + (HVTER_HSWE(hsw >> HTR_HSW_LSB_WIDTH) & HVTER_HSWE_MASK) | + (HVTER_VBPE(vbp >> VTR1_VBP_LSB_WIDTH) & HVTER_VBPE_MASK) | + (HVTER_VFPE(vfp >> VTR1_VFP_LSB_WIDTH) & HVTER_VFPE_MASK) | + (HVTER_HBPE(hbp >> HTR_HBP_LSB_WIDTH) & HVTER_HBPE_MASK) | + (HVTER_HFPE(hfp >> HTR_HFP_LSB_WIDTH) & HVTER_HFPE_MASK), + priv->regs + HVTER); + + /* Set polarities */ + reg = readl(priv->regs + CR1); + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + reg |= CR1_VSP; + else + reg &= ~CR1_VSP; + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + reg |= CR1_HSP; + else + reg &= ~CR1_HSP; + reg |= CR1_DEP; // set DE to active high; + writel(reg, priv->regs + CR1); + + crtc->hwmode = crtc->state->adjusted_mode; +} + +static void baikal_vdu_crtc_helper_enable(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct baikal_vdu_private *priv = crtc->dev->dev_private; + struct drm_panel *panel = priv->panel; + struct device_node *panel_node; + const char *data_mapping; + u32 cntl, gpio; + + DRM_DEV_DEBUG_DRIVER(crtc->dev->dev, "enabling pixel clock\n"); + clk_prepare_enable(priv->clk); + + drm_panel_prepare(panel); + + writel(ISCR_VSC_VFP, priv->regs + ISCR); + + /* release clock reset; enable clocking */ + cntl = readl(priv->regs + PCTR); + cntl |= PCTR_PCR + PCTR_PCI; + writel(cntl, priv->regs + PCTR); + + /* Set 16-word input FIFO watermark */ + /* Enable and Power Up */ + cntl = readl(priv->regs + CR1); + cntl &= ~CR1_FDW_MASK; + cntl |= CR1_LCE + CR1_FDW_16_WORDS; + + if (priv->type == VDU_TYPE_LVDS) { + panel_node = panel->dev->of_node; + if (of_property_read_string(panel_node, "data-mapping", &data_mapping)) { + cntl |= CR1_OPS_LCD18; + } else if (strncmp(data_mapping, "vesa-24", 7)) + cntl |= CR1_OPS_LCD24; + else if (strncmp(data_mapping, "jeida-18", 8)) + cntl |= CR1_OPS_LCD18; + else { + dev_warn(crtc->dev->dev, "%s data mapping is not supported, vesa-24 is set\n", data_mapping); + cntl |= CR1_OPS_LCD24; + } + gpio = GPIOR_UHD_ENB; + if (priv->ep_count == 4) + gpio |= GPIOR_UHD_QUAD_PORT; + else if (priv->ep_count == 2) + gpio |= GPIOR_UHD_DUAL_PORT; + else + gpio |= GPIOR_UHD_SNGL_PORT; + writel(gpio, priv->regs + GPIOR); + } else + cntl |= CR1_OPS_LCD24; + writel(cntl, priv->regs + CR1); + + drm_panel_enable(priv->panel); + drm_crtc_vblank_on(crtc); +} + +void baikal_vdu_crtc_helper_disable(struct drm_crtc *crtc) +{ + struct baikal_vdu_private *priv = crtc->dev->dev_private; + + drm_crtc_vblank_off(crtc); + drm_panel_disable(priv->panel); + + drm_panel_unprepare(priv->panel); + + /* Disable clock */ + DRM_DEV_DEBUG_DRIVER(crtc->dev->dev, "disabling pixel clock\n"); + clk_disable_unprepare(priv->clk); +} + +static void baikal_vdu_crtc_helper_atomic_flush(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct drm_pending_vblank_event *event = crtc->state->event; + + if (event) { + crtc->state->event = NULL; + + spin_lock_irq(&crtc->dev->event_lock); + if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0) + drm_crtc_arm_vblank_event(crtc, event); + else + drm_crtc_send_vblank_event(crtc, event); + spin_unlock_irq(&crtc->dev->event_lock); + } +} + +static int baikal_vdu_enable_vblank(struct drm_crtc *crtc) +{ + struct baikal_vdu_private *priv = crtc->dev->dev_private; + + /* clear interrupt status */ + writel(0x3ffff, priv->regs + ISR); + + writel(INTR_VCT + INTR_FER, priv->regs + IMR); + + return 0; +} + +static void baikal_vdu_disable_vblank(struct drm_crtc *crtc) +{ + struct baikal_vdu_private *priv = crtc->dev->dev_private; + + /* clear interrupt status */ + writel(0x3ffff, priv->regs + ISR); + + writel(INTR_FER, priv->regs + IMR); +} + +const struct drm_crtc_funcs crtc_funcs = { + .set_config = drm_atomic_helper_set_config, + .page_flip = drm_atomic_helper_page_flip, + .reset = drm_atomic_helper_crtc_reset, + .destroy = drm_crtc_cleanup, + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, + .enable_vblank = baikal_vdu_enable_vblank, + .disable_vblank = baikal_vdu_disable_vblank, +}; + +const struct drm_crtc_helper_funcs crtc_helper_funcs = { + .mode_fixup = baikal_vdu_crtc_mode_fixup, + .mode_set_nofb = baikal_vdu_crtc_helper_mode_set_nofb, + .atomic_flush = baikal_vdu_crtc_helper_atomic_flush, + .disable = baikal_vdu_crtc_helper_disable, + .atomic_enable = baikal_vdu_crtc_helper_enable, +}; + +int baikal_vdu_crtc_create(struct drm_device *dev) +{ + struct baikal_vdu_private *priv = dev->dev_private; + struct drm_crtc *crtc = &priv->crtc; + + drm_crtc_init_with_planes(dev, crtc, + &priv->primary, NULL, + &crtc_funcs, "primary"); + drm_crtc_helper_add(crtc, &crtc_helper_funcs); + + /* XXX: The runtime clock disabling still results in + * occasional system hangs, and needs debugging. + */ + + DRM_DEV_DEBUG_DRIVER(crtc->dev->dev, "enabling pixel clock\n"); + clk_prepare_enable(priv->clk); + + return 0; +} diff --git a/drivers/gpu/drm/baikal/baikal_vdu_debugfs.c b/drivers/gpu/drm/baikal/baikal_vdu_debugfs.c new file mode 100644 index 000000000000..77be6aa588dc --- /dev/null +++ b/drivers/gpu/drm/baikal/baikal_vdu_debugfs.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2019-2020 Baikal Electronics JSC + * + * Author: Pavel Parkhomenko + * + * Parts of this file were based on sources as follows: + * + * Copyright © 2017 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include "baikal_vdu_drm.h" +#include "baikal_vdu_regs.h" + +#define REGDEF(reg) { reg, #reg } +static const struct { + u32 reg; + const char *name; +} baikal_vdu_reg_defs[] = { + REGDEF(CR1), + REGDEF(HTR), + REGDEF(VTR1), + REGDEF(VTR2), + REGDEF(PCTR), + REGDEF(ISR), + REGDEF(IMR), + REGDEF(IVR), + REGDEF(ISCR), + REGDEF(DBAR), + REGDEF(DCAR), + REGDEF(DEAR), + REGDEF(HVTER), + REGDEF(HPPLOR), + REGDEF(GPIOR), + REGDEF(OWER), + REGDEF(OWXSER0), + REGDEF(OWYSER0), + REGDEF(OWDBAR0), + REGDEF(OWDCAR0), + REGDEF(OWDEAR0), + REGDEF(OWXSER1), + REGDEF(OWYSER1), + REGDEF(OWDBAR1), + REGDEF(OWDCAR1), + REGDEF(OWDEAR1), + REGDEF(MRR), +}; + +int baikal_vdu_debugfs_regs(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct baikal_vdu_private *priv = dev->dev_private; + int i; + + for (i = 0; i < ARRAY_SIZE(baikal_vdu_reg_defs); i++) { + seq_printf(m, "%s (0x%04x): 0x%08x\n", + baikal_vdu_reg_defs[i].name, baikal_vdu_reg_defs[i].reg, + readl(priv->regs + baikal_vdu_reg_defs[i].reg)); + } + + for (i = 0; i < ARRAY_SIZE(priv->counters); i++) { + seq_printf(m, "COUNTER[%d]: 0x%08x\n", i, priv->counters[i]); + } + + return 0; +} + +static const struct drm_info_list baikal_vdu_debugfs_list[] = { + {"regs", baikal_vdu_debugfs_regs, 0}, +}; + +void baikal_vdu_debugfs_init(struct drm_minor *minor) +{ + drm_debugfs_create_files(baikal_vdu_debugfs_list, + ARRAY_SIZE(baikal_vdu_debugfs_list), + minor->debugfs_root, minor); +} diff --git a/drivers/gpu/drm/baikal/baikal_vdu_drm.h b/drivers/gpu/drm/baikal/baikal_vdu_drm.h new file mode 100644 index 000000000000..755d4abeedf7 --- /dev/null +++ b/drivers/gpu/drm/baikal/baikal_vdu_drm.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2019-2020 Baikal Electronics JSC + * + * Author: Pavel Parkhomenko + * + * Parts of this file were based on sources as follows: + * + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * Copyright (C) 2011 Texas Instruments + * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. + * + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms of + * such GNU licence. + * + */ + +#ifndef __BAIKAL_VDU_DRM_H__ +#define __BAIKAL_VDU_DRM_H__ + +#include +#include + +#define VDU_TYPE_HDMI 0 +#define VDU_TYPE_LVDS 1 + +struct baikal_vdu_private { + struct drm_device *drm; + + unsigned int irq; + bool irq_enabled; + + struct drm_connector connector; + struct drm_crtc crtc; + struct drm_encoder encoder; + struct drm_panel *panel; + struct drm_bridge *bridge; + struct drm_plane primary; + + void *regs; + struct clk *clk; + u32 counters[20]; + int mode_fixup; + int type; + u32 ep_count; + u32 fb_addr; + u32 fb_end; + + struct gpio_desc *enable_gpio; +}; + +/* CRTC Functions */ +int baikal_vdu_crtc_create(struct drm_device *dev); +irqreturn_t baikal_vdu_irq(int irq, void *data); + +int baikal_vdu_primary_plane_init(struct drm_device *dev); + +/* Connector Functions */ +int baikal_vdu_lvds_connector_create(struct drm_device *dev); + +void baikal_vdu_debugfs_init(struct drm_minor *minor); + +#endif /* __BAIKAL_VDU_DRM_H__ */ diff --git a/drivers/gpu/drm/baikal/baikal_vdu_drv.c b/drivers/gpu/drm/baikal/baikal_vdu_drv.c new file mode 100644 index 000000000000..af0e0ca193c7 --- /dev/null +++ b/drivers/gpu/drm/baikal/baikal_vdu_drv.c @@ -0,0 +1,363 @@ +/* + * Copyright (C) 2019-2020 Baikal Electronics JSC + * + * Author: Pavel Parkhomenko + * All bugs by Alexey Sheplyakov + * + * This driver is based on ARM PL111 DRM driver + * + * Parts of this file were based on sources as follows: + * + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * Copyright (C) 2011 Texas Instruments + * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. + * + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms of + * such GNU licence. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "baikal_vdu_drm.h" +#include "baikal_vdu_regs.h" + +#define DRIVER_NAME "baikal-vdu" +#define DRIVER_DESC "DRM module for Baikal VDU" +#define DRIVER_DATE "20200131" + +#define BAIKAL_SMC_SCP_LOG_DISABLE 0x82000200 + +int mode_fixup = 0; + +static struct drm_mode_config_funcs mode_config_funcs = { + .fb_create = drm_gem_fb_create, + .atomic_check = drm_atomic_helper_check, + .atomic_commit = drm_atomic_helper_commit, +}; + +static const struct drm_encoder_funcs baikal_vdu_encoder_funcs = { + .destroy = drm_encoder_cleanup, +}; + +DEFINE_DRM_GEM_CMA_FOPS(drm_fops); + +static struct drm_driver vdu_drm_driver = { + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, + .ioctls = NULL, + .fops = &drm_fops, + .name = DRIVER_NAME, + .desc = DRIVER_DESC, + .date = DRIVER_DATE, + .major = 1, + .minor = 0, + .patchlevel = 0, + DRM_GEM_CMA_DRIVER_OPS, +#if defined(CONFIG_DEBUG_FS) + .debugfs_init = baikal_vdu_debugfs_init, +#endif +}; + +static int vdu_modeset_init(struct drm_device *dev) +{ + struct drm_mode_config *mode_config; + struct baikal_vdu_private *priv = dev->dev_private; + struct arm_smccc_res res; + int ret = 0, ep_count = 0; + + if (priv == NULL) + return -EINVAL; + + drm_mode_config_init(dev); + mode_config = &dev->mode_config; + mode_config->funcs = &mode_config_funcs; + mode_config->min_width = 1; + mode_config->max_width = 4096; + mode_config->min_height = 1; + mode_config->max_height = 4096; + + ret = baikal_vdu_primary_plane_init(dev); + if (ret != 0) { + dev_err(dev->dev, "Failed to init primary plane\n"); + goto out_config; + } + + ret = baikal_vdu_crtc_create(dev); + if (ret) { + dev_err(dev->dev, "Failed to create crtc\n"); + goto out_config; + } + + ret = drm_of_find_panel_or_bridge(dev->dev->of_node, -1, -1, + &priv->panel, + &priv->bridge); + if (ret == -EPROBE_DEFER) { + dev_info(dev->dev, "Bridge probe deferred\n"); + goto out_config; + } + ep_count = of_graph_get_endpoint_count(dev->dev->of_node); + if (ep_count <= 0) { + dev_err(dev->dev, "no endpoints connected to panel/bridge\n"); + goto out_config; + } + priv->ep_count = ep_count; + + if (priv->bridge) { + struct drm_encoder *encoder = &priv->encoder; + ret = drm_encoder_init(dev, encoder, &baikal_vdu_encoder_funcs, + DRM_MODE_ENCODER_NONE, NULL); + if (ret) { + dev_err(dev->dev, "failed to create DRM encoder\n"); + goto out_config; + } + encoder->crtc = &priv->crtc; + encoder->possible_crtcs = drm_crtc_mask(encoder->crtc); + priv->bridge->encoder = &priv->encoder; + ret = drm_bridge_attach(&priv->encoder, priv->bridge, NULL, 0); + if (ret) { + dev_err(dev->dev, "Failed to attach DRM bridge %d\n", ret); + goto out_config; + } + } else if (priv->panel) { + dev_dbg(dev->dev, "panel has %d endpoints\n", priv->ep_count); + ret = baikal_vdu_lvds_connector_create(dev); + if (ret) { + dev_err(dev->dev, "Failed to create DRM connector\n"); + goto out_config; + } + } else + ret = -EINVAL; + + if (ret) { + dev_err(dev->dev, "No bridge or panel attached!\n"); + goto out_config; + } + + priv->clk = clk_get(dev->dev, "pclk"); + if (IS_ERR(priv->clk)) { + dev_err(dev->dev, "fatal: unable to get pclk, err %ld\n", PTR_ERR(priv->clk)); + ret = PTR_ERR(priv->clk); + goto out_config; + } + + priv->mode_fixup = mode_fixup; + + drm_aperture_remove_framebuffers(false, &vdu_drm_driver); + + ret = drm_vblank_init(dev, 1); + if (ret != 0) { + dev_err(dev->dev, "Failed to init vblank\n"); + goto out_clk; + } + + arm_smccc_smc(BAIKAL_SMC_SCP_LOG_DISABLE, 0, 0, 0, 0, 0, 0, 0, &res); + + drm_mode_config_reset(dev); + + drm_kms_helper_poll_init(dev); + + ret = drm_dev_register(dev, 0); + if (ret) + goto out_clk; + + drm_fbdev_generic_setup(dev, 32); + goto finish; + +out_clk: + clk_put(priv->clk); +out_config: + drm_mode_config_cleanup(dev); +finish: + return ret; +} + + +static int baikal_vdu_irq_install(struct baikal_vdu_private *priv, int irq) +{ + int ret; + ret= request_irq(irq, baikal_vdu_irq, 0, DRIVER_NAME, priv->drm); + if (ret < 0) + return ret; + priv->irq_enabled = true; + return 0; +} + +static void baikal_vdu_irq_uninstall(struct baikal_vdu_private *priv) +{ + if (priv->irq_enabled) { + priv->irq_enabled = false; + disable_irq(priv->irq); + free_irq(priv->irq, priv->drm); + } +} + +static int vdu_maybe_enable_lvds(struct baikal_vdu_private *vdu) +{ + int err = 0; + struct device *dev; + if (!vdu->drm) { + pr_err("%s: vdu->drm is NULL\n", __func__); + return -EINVAL; + } + dev = vdu->drm->dev; + + vdu->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); + if (IS_ERR(vdu->enable_gpio)) { + err = (int)PTR_ERR(vdu->enable_gpio); + dev_err(dev, "failed to get enable-gpios, error %d\n", err); + vdu->enable_gpio = NULL; + return err; + } + if (vdu->enable_gpio) { + dev_dbg(dev, "%s: setting enable-gpio\n", __func__); + gpiod_set_value_cansleep(vdu->enable_gpio, 1); + } else { + dev_dbg(dev, "%s: no enable-gpios, assuming it's handled by panel-lvds\n", __func__); + } + return 0; +} + +static int baikal_vdu_drm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct baikal_vdu_private *priv; + struct drm_device *drm; + struct resource *mem; + int irq; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + drm = drm_dev_alloc(&vdu_drm_driver, dev); + if (IS_ERR(drm)) + return PTR_ERR(drm); + platform_set_drvdata(pdev, drm); + priv->drm = drm; + drm->dev_private = priv; + + if (!(mem = platform_get_resource(pdev, IORESOURCE_MEM, 0))) { + dev_err(dev, "%s no MMIO resource specified\n", __func__); + return -EINVAL; + } + + priv->regs = devm_ioremap_resource(dev, mem); + if (IS_ERR(priv->regs)) { + dev_err(dev, "%s MMIO allocation failed\n", __func__); + return PTR_ERR(priv->regs); + } + + /* turn off interrupts before requesting the irq */ + writel(0, priv->regs + IMR); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "%s no IRQ resource specified\n", __func__); + return -EINVAL; + } + priv->irq = irq; + + ret = baikal_vdu_irq_install(priv, irq); + if (ret != 0) { + dev_err(dev, "%s IRQ %d allocation failed\n", __func__, irq); + return ret; + } + + if (pdev->dev.of_node && of_property_read_bool(pdev->dev.of_node, "lvds-out")) { + priv->type = VDU_TYPE_LVDS; + if (of_property_read_u32(pdev->dev.of_node, "num-lanes", &priv->ep_count)) + priv->ep_count = 1; + } + else + priv->type = VDU_TYPE_HDMI; + + ret = vdu_modeset_init(drm); + if (ret != 0) { + dev_err(dev, "Failed to init modeset\n"); + goto dev_unref; + } + + ret = vdu_maybe_enable_lvds(priv); + if (ret != 0) { + dev_err(dev, "failed to enable LVDS\n"); + } + + return 0; + +dev_unref: + writel(0, priv->regs + IMR); + writel(0x3ffff, priv->regs + ISR); + baikal_vdu_irq_uninstall(priv); + drm->dev_private = NULL; + drm_dev_put(drm); + return ret; +} + +static int baikal_vdu_drm_remove(struct platform_device *pdev) +{ + struct drm_device *drm; + struct baikal_vdu_private *priv; + + drm = platform_get_drvdata(pdev); + if (!drm) { + return -1; + } + priv = drm->dev_private; + + drm_dev_unregister(drm); + drm_mode_config_cleanup(drm); + baikal_vdu_irq_uninstall(priv); + drm->dev_private = NULL; + drm_dev_put(drm); + + return 0; +} + +static const struct of_device_id baikal_vdu_of_match[] = { + { .compatible = "baikal,vdu" }, + { }, +}; +MODULE_DEVICE_TABLE(of, baikal_vdu_of_match); + +static struct platform_driver baikal_vdu_platform_driver = { + .probe = baikal_vdu_drm_probe, + .remove = baikal_vdu_drm_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = baikal_vdu_of_match, + }, +}; + +module_param(mode_fixup, int, 0644); + +module_platform_driver(baikal_vdu_platform_driver); + +MODULE_AUTHOR("Pavel Parkhomenko "); +MODULE_DESCRIPTION("Baikal Electronics BE-M1000 Video Display Unit (VDU) DRM Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRIVER_NAME); +MODULE_SOFTDEP("pre: baikal_hdmi"); diff --git a/drivers/gpu/drm/baikal/baikal_vdu_plane.c b/drivers/gpu/drm/baikal/baikal_vdu_plane.c new file mode 100644 index 000000000000..4a3e971793d2 --- /dev/null +++ b/drivers/gpu/drm/baikal/baikal_vdu_plane.c @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2019-2020 Baikal Electronics JSC + * + * Author: Pavel Parkhomenko + * + * Parts of this file were based on sources as follows: + * + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * Copyright (C) 2011 Texas Instruments + * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. + * + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms of + * such GNU licence. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "baikal_vdu_drm.h" +#include "baikal_vdu_regs.h" + +static int baikal_vdu_primary_plane_atomic_check(struct drm_plane *plane, + struct drm_atomic_state *atomic_state) +{ + struct drm_device *dev = plane->dev; + struct baikal_vdu_private *priv = dev->dev_private; + struct drm_crtc_state *crtc_state; + struct drm_plane_state *state; + struct drm_display_mode *mode; + int rate, ret; + u32 cntl; + + state = drm_atomic_get_new_plane_state(atomic_state, plane); + if (!state || !state->crtc) + return 0; + + crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); + if (IS_ERR(crtc_state)) { + ret = PTR_ERR(crtc_state); + dev_warn(dev->dev, "failed to get crtc_state: %d\n", ret); + return ret; + } + mode = &crtc_state->adjusted_mode; + rate = mode->clock * 1000; + if (rate == clk_get_rate(priv->clk)) + return 0; + + /* hold clock domain reset; disable clocking */ + writel(0, priv->regs + PCTR); + + if (__clk_is_enabled(priv->clk)) + clk_disable_unprepare(priv->clk); + ret = clk_set_rate(priv->clk, rate); + DRM_DEV_DEBUG_DRIVER(dev->dev, "Requested pixel clock is %d Hz\n", rate); + + if (ret < 0) { + DRM_ERROR("Cannot set desired pixel clock (%d Hz)\n", + rate); + ret = -EINVAL; + } else { + clk_prepare_enable(priv->clk); + if (__clk_is_enabled(priv->clk)) + ret = 0; + else { + DRM_ERROR("PLL could not lock at desired frequency (%d Hz)\n", + rate); + ret = -EINVAL; + } + } + + /* release clock domain reset; enable clocking */ + cntl = readl(priv->regs + PCTR); + cntl |= PCTR_PCR + PCTR_PCI; + writel(cntl, priv->regs + PCTR); + + return ret; +} + +static void baikal_vdu_primary_plane_atomic_update(struct drm_plane *plane, + struct drm_atomic_state *old_state) +{ + struct drm_device *dev = plane->dev; + struct baikal_vdu_private *priv = dev->dev_private; + struct drm_plane_state *state = plane->state; + struct drm_framebuffer *fb = state->fb; + u32 cntl, addr, end; + + if (!fb) + return; + + addr = drm_fb_cma_get_gem_addr(fb, state, 0); + priv->fb_addr = addr & 0xfffffff8; + + cntl = readl(priv->regs + CR1); + cntl &= ~CR1_BPP_MASK; + + /* Note that the the hardware's format reader takes 'r' from + * the low bit, while DRM formats list channels from high bit + * to low bit as you read left to right. + */ + switch (fb->format->format) { + case DRM_FORMAT_BGR888: + cntl |= CR1_BPP24 | CR1_FBP | CR1_BGR; + break; + case DRM_FORMAT_RGB888: + cntl |= CR1_BPP24 | CR1_FBP; + break; + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_XBGR8888: + cntl |= CR1_BPP24 | CR1_BGR; + break; + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XRGB8888: + cntl |= CR1_BPP24; + break; + case DRM_FORMAT_BGR565: + cntl |= CR1_BPP16_565 | CR1_BGR; + break; + case DRM_FORMAT_RGB565: + cntl |= CR1_BPP16_565; + break; + case DRM_FORMAT_ABGR1555: + case DRM_FORMAT_XBGR1555: + cntl |= CR1_BPP16_555 | CR1_BGR; + break; + case DRM_FORMAT_ARGB1555: + case DRM_FORMAT_XRGB1555: + cntl |= CR1_BPP16_555; + break; + default: + WARN_ONCE(true, "Unknown FB format 0x%08x, set XRGB8888 instead\n", + fb->format->format); + cntl |= CR1_BPP24; + break; + } + + writel(priv->fb_addr, priv->regs + DBAR); + end = ((priv->fb_addr + fb->height * fb->pitches[0] - 1) & MRR_DEAR_MRR_MASK) | \ + MRR_OUTSTND_RQ(4); + + if (priv->fb_end < end) { + writel(end, priv->regs + MRR); + priv->fb_end = end; + } + writel(cntl, priv->regs + CR1); +} + +static const struct drm_plane_helper_funcs baikal_vdu_primary_plane_helper_funcs = { + .atomic_check = baikal_vdu_primary_plane_atomic_check, + .atomic_update = baikal_vdu_primary_plane_atomic_update, +}; + +static const struct drm_plane_funcs baikal_vdu_primary_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, + .reset = drm_atomic_helper_plane_reset, + .destroy = drm_plane_cleanup, + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, +}; + +int baikal_vdu_primary_plane_init(struct drm_device *drm) +{ + struct baikal_vdu_private *priv = drm->dev_private; + struct drm_plane *plane = &priv->primary; + static const u32 formats[] = { + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_BGR565, + DRM_FORMAT_RGB565, + DRM_FORMAT_ABGR1555, + DRM_FORMAT_XBGR1555, + DRM_FORMAT_ARGB1555, + DRM_FORMAT_XRGB1555, + }; + int ret; + + ret = drm_universal_plane_init(drm, plane, 0, + &baikal_vdu_primary_plane_funcs, + formats, + ARRAY_SIZE(formats), + NULL, + DRM_PLANE_TYPE_PRIMARY, + NULL); + if (ret) + return ret; + + drm_plane_helper_add(plane, &baikal_vdu_primary_plane_helper_funcs); + + return 0; +} + + diff --git a/drivers/gpu/drm/baikal/baikal_vdu_regs.h b/drivers/gpu/drm/baikal/baikal_vdu_regs.h new file mode 100644 index 000000000000..5553fcac5fec --- /dev/null +++ b/drivers/gpu/drm/baikal/baikal_vdu_regs.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019-2021 Baikal Electronics JSC + * + * Author: Pavel Parkhomenko + * + * Parts of this file were based on sources as follows: + * + * David A Rusling + * Copyright (C) 2001 ARM Limited + */ + +#ifndef __BAIKAL_VDU_REGS_H__ +#define __BAIKAL_VDU_REGS_H__ + +#define CR1 0x000 +#define HTR 0x008 +#define VTR1 0x00C +#define VTR2 0x010 +#define PCTR 0x014 +#define ISR 0x018 +#define IMR 0x01C +#define IVR 0x020 +#define ISCR 0x024 +#define DBAR 0x028 +#define DCAR 0x02C +#define DEAR 0x030 +#define HVTER 0x044 +#define HPPLOR 0x048 +#define GPIOR 0x1F8 +#define OWER 0x600 +#define OWXSER0 0x604 +#define OWYSER0 0x608 +#define OWDBAR0 0x60C +#define OWDCAR0 0x610 +#define OWDEAR0 0x614 +#define OWXSER1 0x618 +#define OWYSER1 0x61C +#define OWDBAR1 0x620 +#define OWDCAR1 0x624 +#define OWDEAR1 0x628 +#define MRR 0xFFC + +#define INTR_BAU BIT(7) +#define INTR_VCT BIT(6) +#define INTR_MBE BIT(5) +#define INTR_FER BIT(4) + +#define CR1_FBP BIT(19) +#define CR1_FDW_MASK GENMASK(17, 16) +#define CR1_FDW_4_WORDS (0 << 16) +#define CR1_FDW_8_WORDS (1 << 16) +#define CR1_FDW_16_WORDS (2 << 16) +#define CR1_OPS_LCD18 (0 << 13) +#define CR1_OPS_LCD24 (1 << 13) +#define CR1_OPS_565 (0 << 12) +#define CR1_OPS_555 (1 << 12) +#define CR1_VSP BIT(11) +#define CR1_HSP BIT(10) +#define CR1_DEP BIT(8) +#define CR1_BGR BIT(5) +#define CR1_BPP_MASK GENMASK(4, 2) +#define CR1_BPP1 (0 << 2) +#define CR1_BPP2 (1 << 2) +#define CR1_BPP4 (2 << 2) +#define CR1_BPP8 (3 << 2) +#define CR1_BPP16 (4 << 2) +#define CR1_BPP18 (5 << 2) +#define CR1_BPP24 (6 << 2) +#define CR1_LCE BIT(0) + +#define CR1_BPP16_555 ((CR1_BPP16) | (CR1_OPS_555)) +#define CR1_BPP16_565 ((CR1_BPP16) | (CR1_OPS_565)) + +#define VTR1_VBP_MASK GENMASK(23, 16) +#define VTR1_VBP(x) ((x) << 16) +#define VTR1_VBP_LSB_WIDTH 8 +#define VTR1_VFP_MASK GENMASK(15, 8) +#define VTR1_VFP(x) ((x) << 8) +#define VTR1_VFP_LSB_WIDTH 8 +#define VTR1_VSW_MASK GENMASK(7, 0) +#define VTR1_VSW(x) ((x) << 0) +#define VTR1_VSW_LSB_WIDTH 8 + +#define VTR2_LPP_MASK GENMASK(11, 0) + +#define HTR_HSW_MASK GENMASK(31, 24) +#define HTR_HSW(x) ((x) << 24) +#define HTR_HSW_LSB_WIDTH 8 +#define HTR_HBP_MASK GENMASK(23, 16) +#define HTR_HBP(x) ((x) << 16) +#define HTR_HBP_LSB_WIDTH 8 +#define HTR_PPL_MASK GENMASK(15, 8) +#define HTR_PPL(x) ((x) << 8) +#define HTR_HFP_MASK GENMASK(7, 0) +#define HTR_HFP(x) ((x) << 0) +#define HTR_HFP_LSB_WIDTH 8 + +#define PCTR_PCI2 BIT(11) +#define PCTR_PCR BIT(10) +#define PCTR_PCI BIT(9) +#define PCTR_PCB BIT(8) +#define PCTR_PCD_MASK GENMASK(7, 0) +#define PCTR_MAX_PCD 128 + +#define ISCR_VSC_OFF 0x0 +#define ISCR_VSC_VSW 0x4 +#define ISCR_VSC_VBP 0x5 +#define ISCR_VSC_VACTIVE 0x6 +#define ISCR_VSC_VFP 0x7 + +#define HVTER_VSWE_MASK GENMASK(25, 24) +#define HVTER_VSWE(x) ((x) << 24) +#define HVTER_HSWE_MASK GENMASK(17, 16) +#define HVTER_HSWE(x) ((x) << 16) +#define HVTER_VBPE_MASK GENMASK(13, 12) +#define HVTER_VBPE(x) ((x) << 12) +#define HVTER_VFPE_MASK GENMASK(9, 8) +#define HVTER_VFPE(x) ((x) << 8) +#define HVTER_HBPE_MASK GENMASK(5, 4) +#define HVTER_HBPE(x) ((x) << 4) +#define HVTER_HFPE_MASK GENMASK(1, 0) +#define HVTER_HFPE(x) ((x) << 0) + +#define HPPLOR_HPOE BIT(31) +#define HPPLOR_HPPLO_MASK GENMASK(11, 0) +#define HPPLOR_HPPLO(x) ((x) << 0) + +#define GPIOR_UHD_MASK GENMASK(23, 16) +#define GPIOR_UHD_SNGL_PORT (0 << 18) +#define GPIOR_UHD_DUAL_PORT (1 << 18) +#define GPIOR_UHD_QUAD_PORT (2 << 18) +#define GPIOR_UHD_ENB BIT(17) + +#define MRR_DEAR_MRR_MASK GENMASK(31, 3) +#define MRR_OUTSTND_RQ_MASK GENMASK(2, 0) +#define MRR_OUTSTND_RQ(x) ((x >> 1) << 0) + +#endif /* __BAIKAL_VDU_REGS_H__ */ diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 431b6e12a81f..0c2661be5937 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -135,6 +135,13 @@ config DRM_LVDS_CODEC Support for transparent LVDS encoders and decoders that don't require any configuration. +config DRM_BAIKAL_HDMI + tristate "Baikal-M HDMI transmitter" + default y if ARCH_BAIKAL + select DRM_DW_HDMI + help + Choose this if you want to use HDMI on Baikal-M. + config DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW tristate "MegaChips stdp4028-ge-b850v3-fw and stdp2690-ge-b850v3-fw" depends on OF diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c index d0db1acf11d7..3bb652e42718 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c @@ -132,12 +132,45 @@ struct snd_dw_hdmi { u8 cs[192][8]; }; -static void dw_hdmi_writel(u32 val, void __iomem *ptr) +static inline void dw_hdmi_writeb_relaxed(u8 value, const struct dw_hdmi_audio_data *data, int offset) { - writeb_relaxed(val, ptr); - writeb_relaxed(val >> 8, ptr + 1); - writeb_relaxed(val >> 16, ptr + 2); - writeb_relaxed(val >> 24, ptr + 3); + void __iomem *base = data->base; + if (data->reg_offset != 0) + offset <<= data->reg_offset; + writeb_relaxed(value, base + offset); +} + +static inline void dw_hdmi_writeb(u8 value, const struct dw_hdmi_audio_data *data, int offset) +{ + void __iomem *base = data->base; + if (data->reg_offset != 0) + offset <<= data->reg_offset; + writeb(value, base + offset); +} + +static inline u8 dw_hdmi_readb(const struct dw_hdmi_audio_data *data, int offset) +{ + void __iomem *base = data->base; + if (data->reg_offset != 0) + offset <<= data->reg_offset; + return readb(base + offset); + +} + +static inline u8 dw_hdmi_readb_relaxed(const struct dw_hdmi_audio_data *data, int offset) +{ + void __iomem *base = data->base; + if (data->reg_offset != 0) + offset <<= data->reg_offset; + return readb_relaxed(base + offset); +} + +static void dw_hdmi_writel(u32 val, const struct dw_hdmi_audio_data *data, int offset) +{ + dw_hdmi_writeb_relaxed(val, data, offset); + dw_hdmi_writeb_relaxed(val >> 8, data, offset + 1); + dw_hdmi_writeb_relaxed(val >> 16, data, offset + 2); + dw_hdmi_writeb_relaxed(val >> 24, data, offset + 3); } /* @@ -240,18 +272,18 @@ static void dw_hdmi_start_dma(struct snd_dw_hdmi *dw) dw->reformat(dw, offset, period); /* Clear all irqs before enabling irqs and starting DMA */ - writeb_relaxed(HDMI_IH_AHBDMAAUD_STAT0_ALL, - base + HDMI_IH_AHBDMAAUD_STAT0); + dw_hdmi_writeb_relaxed(HDMI_IH_AHBDMAAUD_STAT0_ALL, + &dw->data, HDMI_IH_AHBDMAAUD_STAT0); start = dw->buf_addr + offset; stop = start + period - 1; /* Setup the hardware start/stop addresses */ - dw_hdmi_writel(start, base + HDMI_AHB_DMA_STRADDR0); - dw_hdmi_writel(stop, base + HDMI_AHB_DMA_STPADDR0); + dw_hdmi_writel(start, &dw->data, HDMI_AHB_DMA_STRADDR0); + dw_hdmi_writel(stop, &dw->data, HDMI_AHB_DMA_STPADDR0); - writeb_relaxed((u8)~HDMI_AHB_DMA_MASK_DONE, base + HDMI_AHB_DMA_MASK); - writeb(HDMI_AHB_DMA_START_START, base + HDMI_AHB_DMA_START); + dw_hdmi_writeb_relaxed((u8)~HDMI_AHB_DMA_MASK_DONE, &dw->data, HDMI_AHB_DMA_MASK); + dw_hdmi_writeb(HDMI_AHB_DMA_START_START, &dw->data, HDMI_AHB_DMA_START); offset += period; if (offset >= dw->buf_size) @@ -262,8 +294,8 @@ static void dw_hdmi_start_dma(struct snd_dw_hdmi *dw) static void dw_hdmi_stop_dma(struct snd_dw_hdmi *dw) { /* Disable interrupts before disabling DMA */ - writeb_relaxed(~0, dw->data.base + HDMI_AHB_DMA_MASK); - writeb_relaxed(HDMI_AHB_DMA_STOP_STOP, dw->data.base + HDMI_AHB_DMA_STOP); + dw_hdmi_writeb_relaxed(~0, &dw->data, HDMI_AHB_DMA_MASK); + dw_hdmi_writeb_relaxed(HDMI_AHB_DMA_STOP_STOP, &dw->data, HDMI_AHB_DMA_STOP); } static irqreturn_t snd_dw_hdmi_irq(int irq, void *data) @@ -272,11 +304,11 @@ static irqreturn_t snd_dw_hdmi_irq(int irq, void *data) struct snd_pcm_substream *substream; unsigned stat; - stat = readb_relaxed(dw->data.base + HDMI_IH_AHBDMAAUD_STAT0); + stat = dw_hdmi_readb_relaxed(&dw->data, HDMI_IH_AHBDMAAUD_STAT0); if (!stat) return IRQ_NONE; - writeb_relaxed(stat, dw->data.base + HDMI_IH_AHBDMAAUD_STAT0); + dw_hdmi_writeb_relaxed(stat, &dw->data, HDMI_IH_AHBDMAAUD_STAT0); substream = dw->substream; if (stat & HDMI_IH_AHBDMAAUD_STAT0_DONE && substream) { @@ -319,7 +352,6 @@ { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_dw_hdmi *dw = substream->private_data; - void __iomem *base = dw->data.base; u8 *eld; int ret; @@ -345,16 +376,16 @@ static int dw_hdmi_open(struct snd_pcm_substream *substream) return ret; /* Clear FIFO */ - writeb_relaxed(HDMI_AHB_DMA_CONF0_SW_FIFO_RST, - base + HDMI_AHB_DMA_CONF0); + dw_hdmi_writeb_relaxed(HDMI_AHB_DMA_CONF0_SW_FIFO_RST, + &dw->data, HDMI_AHB_DMA_CONF0); /* Configure interrupt polarities */ - writeb_relaxed(~0, base + HDMI_AHB_DMA_POL); - writeb_relaxed(~0, base + HDMI_AHB_DMA_BUFFPOL); + dw_hdmi_writeb_relaxed(~0, &dw->data, HDMI_AHB_DMA_POL); + dw_hdmi_writeb_relaxed(~0, &dw->data, HDMI_AHB_DMA_BUFFPOL); /* Keep interrupts masked, and clear any pending */ - writeb_relaxed(~0, base + HDMI_AHB_DMA_MASK); - writeb_relaxed(~0, base + HDMI_IH_AHBDMAAUD_STAT0); + dw_hdmi_writeb_relaxed(~0, &dw->data, HDMI_AHB_DMA_MASK); + dw_hdmi_writeb_relaxed(~0, &dw->data, HDMI_IH_AHBDMAAUD_STAT0); ret = request_irq(dw->data.irq, snd_dw_hdmi_irq, IRQF_SHARED, "dw-hdmi-audio", dw); @@ -362,9 +393,9 @@ static int dw_hdmi_open(struct snd_pcm_substream *substream) return ret; /* Un-mute done interrupt */ - writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL & - ~HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE, - base + HDMI_IH_MUTE_AHBDMAAUD_STAT0); + dw_hdmi_writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL & + ~HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE, + &dw->data, HDMI_IH_MUTE_AHBDMAAUD_STAT0); return 0; } @@ -374,8 +405,8 @@ static int dw_hdmi_close(struct snd_pcm_substream *substream) struct snd_dw_hdmi *dw = substream->private_data; /* Mute all interrupts */ - writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL, - dw->data.base + HDMI_IH_MUTE_AHBDMAAUD_STAT0); + dw_hdmi_writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL, + &dw->data, HDMI_IH_MUTE_AHBDMAAUD_STAT0); free_irq(dw->data.irq, dw); @@ -416,6 +447,11 @@ static int dw_hdmi_prepare(struct snd_pcm_substream *substream) HDMI_AHB_DMA_CONF0_INCR8; threshold = 128; break; + case 0x2a: /* this revision is used in Baikal-M SoC */ + conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE | + HDMI_AHB_DMA_CONF0_INCR16; + threshold = 128; + break; default: /* NOTREACHED */ return -EINVAL; @@ -430,9 +466,9 @@ static int dw_hdmi_prepare(struct snd_pcm_substream *substream) conf1 = default_hdmi_channel_config[runtime->channels - 2].conf1; ca = default_hdmi_channel_config[runtime->channels - 2].ca; - writeb_relaxed(threshold, dw->data.base + HDMI_AHB_DMA_THRSLD); - writeb_relaxed(conf0, dw->data.base + HDMI_AHB_DMA_CONF0); - writeb_relaxed(conf1, dw->data.base + HDMI_AHB_DMA_CONF1); + dw_hdmi_writeb_relaxed(threshold, &dw->data, HDMI_AHB_DMA_THRSLD); + dw_hdmi_writeb_relaxed(conf0, &dw->data, HDMI_AHB_DMA_CONF0); + dw_hdmi_writeb_relaxed(conf1, &dw->data, HDMI_AHB_DMA_CONF1); dw_hdmi_set_channel_count(dw->data.hdmi, runtime->channels); dw_hdmi_set_channel_allocation(dw->data.hdmi, ca); @@ -524,10 +560,10 @@ static int snd_dw_hdmi_probe(struct platform_device *pdev) unsigned revision; int ret; - writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL, - data->base + HDMI_IH_MUTE_AHBDMAAUD_STAT0); - revision = readb_relaxed(data->base + HDMI_REVISION_ID); - if (revision != 0x0a && revision != 0x1a) { + dw_hdmi_writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL, + data, HDMI_IH_MUTE_AHBDMAAUD_STAT0); + revision = dw_hdmi_readb_relaxed(data, HDMI_REVISION_ID); + if (revision != 0x0a && revision != 0x1a && revision != 0x2a) { dev_err(dev, "dw-hdmi-audio: unknown revision 0x%02x\n", revision); return -ENXIO; diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h index cb07dc0da5a7..8fb5ebd5a169 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h @@ -10,6 +10,7 @@ int irq; struct dw_hdmi *hdmi; u8 *(*get_eld)(struct dw_hdmi *hdmi); + unsigned reg_offset; }; struct dw_hdmi_i2s_audio_data { diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index f08d0fded61f..069984b26d99 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -3440,6 +3440,12 @@ audio.irq = irq; audio.hdmi = hdmi; audio.get_eld = hdmi_audio_get_eld; + audio.reg_offset = 0; + if (of_device_is_compatible(np, "baikal,hdmi")) { + audio.reg_offset = 2; + dev_info(dev, "setting audio.reg_offset=%d for BE-M1000 SoC\n", + audio.reg_offset); + } hdmi->enable_audio = dw_hdmi_ahb_audio_enable; hdmi->disable_audio = dw_hdmi_ahb_audio_disable; diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c index 194af7f607a6..fc0e586f8f33 100644 --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c @@ -100,6 +100,10 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev) DRM_DEV_INFO(dev, "More than 1 supply is not supported yet\n"); return 0; } + if (of_device_is_compatible(of_root, "baikal,baikal-m")) { + dev_info(pfdev->dev, "disabling GPU devfreq on BE-M1000\n"); + return 0; + } ret = devm_pm_opp_set_regulators(dev, pfdev->comp->supply_names, pfdev->comp->num_supplies); diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h index 8b25278f34c8..aa43b1413c8a 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -23,6 +23,12 @@ struct panfrost_perfcnt; #define NUM_JOB_SLOTS 3 #define MAX_PM_DOMAINS 3 +#define MAX_COHERENT_GROUPS 2 + +struct panfrost_coherent_group { + u64 core_mask; + unsigned int nr_cores; +}; struct panfrost_features { u16 id; @@ -54,6 +60,7 @@ struct panfrost_features { unsigned long hw_features[64 / BITS_PER_LONG]; unsigned long hw_issues[64 / BITS_PER_LONG]; + struct panfrost_coherent_group core_groups[MAX_COHERENT_GROUPS]; }; /* diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c index 82ad9a67f251..24e9926b5d02 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -561,6 +561,10 @@ static int panfrost_probe(struct platform_device *pdev) return -ENODEV; pfdev->coherent = device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT; + if (!pfdev->coherent && of_device_is_compatible(of_root, "baikal,baikal-m")) { + pfdev->coherent = true; + dev_warn(&pdev->dev, "marking as DMA coherent on BE-M1000"); + } /* Allocate and initialze the DRM device. */ ddev = drm_dev_alloc(&panfrost_drm_driver, &pdev->dev); diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c index bbe628b306ee..a02cb160cb4f 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c @@ -209,6 +209,41 @@ static const struct panfrost_model gpu_models[] = { GPU_REV(g31, 1, 0)), }; +static void panfrost_decode_coherent_groups(struct panfrost_features *features) +{ + struct panfrost_coherent_group *current_group; + u64 group_present; + u64 group_mask; + u64 first_set, first_set_prev; + u32 nr_group = 0; + + if (features->mem_features & GROUPS_L2_COHERENT) + group_present = features->l2_present; + else + group_present = features->shader_present; + + current_group = features->core_groups; + first_set = group_present & ~(group_present - 1); + + while (group_present != 0 && nr_group < MAX_COHERENT_GROUPS) { + group_present -= first_set; + first_set_prev = first_set; + + first_set = group_present & ~(group_present - 1); + group_mask = (first_set - 1) & ~(first_set_prev - 1); + current_group->core_mask = group_mask & features->shader_present; + current_group->nr_cores = hweight64(current_group->core_mask); + + nr_group++; + current_group++; + } + + if (group_present) { + pr_warn("%s: too many coherent groups, expected <= %d", + __func__, MAX_COHERENT_GROUPS); + } +} + static void panfrost_gpu_init_features(struct panfrost_device *pfdev) { u32 gpu_id, num_js, major, minor, status, rev; @@ -217,6 +252,7 @@ static void panfrost_gpu_init_features(struct panfrost_device *pfdev) u64 hw_issues = hw_issues_all; const struct panfrost_model *model; int i; + unsigned long core_mask[64/BITS_PER_LONG]; pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES); pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES); @@ -296,6 +332,7 @@ static void panfrost_gpu_init_features(struct panfrost_device *pfdev) bitmap_from_u64(pfdev->features.hw_features, hw_feat); bitmap_from_u64(pfdev->features.hw_issues, hw_issues); + panfrost_decode_coherent_groups(&pfdev->features); dev_info(pfdev->dev, "mali-%s id 0x%x major 0x%x minor 0x%x status 0x%x", name, gpu_id, major, minor, status); @@ -314,6 +351,14 @@ static void panfrost_gpu_init_features(struct panfrost_device *pfdev) dev_info(pfdev->dev, "shader_present=0x%0llx l2_present=0x%0llx", pfdev->features.shader_present, pfdev->features.l2_present); + dev_info(pfdev->dev, "%u core groups\n", pfdev->features.nr_core_groups); + for (i = 0; i < (int)pfdev->features.nr_core_groups; i++) { + bitmap_from_u64(core_mask, pfdev->features.core_groups[i].core_mask); + dev_info(pfdev->dev, "core group %u: cores: %64pbl (total %u)\n", + i, + core_mask, + pfdev->features.core_groups[i].nr_cores); + } } void panfrost_gpu_power_on(struct panfrost_device *pfdev) diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c b/drivers/gpu/drm/panfrost/panfrost_job.c index 908d79520853..a2ec4bc5c90d 100644 --- a/drivers/gpu/drm/panfrost/panfrost_job.c +++ b/drivers/gpu/drm/panfrost/panfrost_job.c @@ -132,11 +132,21 @@ static void panfrost_job_write_affinity(struct panfrost_device *pfdev, /* * Use all cores for now. - * Eventually we may need to support tiler only jobs and h/w with - * multiple (2) coherent core groups + * Eventually we may need to support tiler only jobs. */ affinity = pfdev->features.shader_present; + /* Userspace does not set the requirements properly yet. + * Adjust affinity of all jobs on dual core group GPUs + */ + if (pfdev->features.nr_core_groups > 1) { + if (js == 2) + affinity &= pfdev->features.core_groups[1].core_mask; + else + affinity &= pfdev->features.core_groups[0].core_mask; + dev_dbg(pfdev->dev, "js: %d, affinity: %llxu\n", js, affinity); + } + job_write(pfdev, JS_AFFINITY_NEXT_LO(js), lower_32_bits(affinity)); job_write(pfdev, JS_AFFINITY_NEXT_HI(js), upper_32_bits(affinity)); } diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 64bd3dfba2c4..3ade6b7e31e3 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -412,10 +412,11 @@ config SENSORS_ATXP1 will be called atxp1. config SENSORS_BT1_PVT - tristate "Baikal-T1 Process, Voltage, Temperature sensor driver" - depends on MIPS_BAIKAL_T1 || COMPILE_TEST + tristate "Baikal-T1/M Process, Voltage, Temperature sensor driver" + depends on MIPS_BAIKAL_T1 || ARCH_BAIKAL || COMPILE_TEST + default m if MIPS_BAIKAL_T1 || ARCH_BAIKAL help - If you say yes here you get support for Baikal-T1 PVT sensor + If you say yes here you get support for Baikal-M or Baikal-T1 PVT sensor embedded into the SoC. This driver can also be built as a module. If so, the module will be diff --git a/drivers/hwmon/bt1-pvt.c b/drivers/hwmon/bt1-pvt.c index 74ce5211eb75..a32ef9f9351c 100644 --- a/drivers/hwmon/bt1-pvt.c +++ b/drivers/hwmon/bt1-pvt.c @@ -29,6 +29,9 @@ #include #include #include +#ifdef CONFIG_ARM64 +#include +#endif #include "bt1-pvt.h" @@ -138,12 +141,43 @@ static long pvt_calc_poly(const struct pvt_poly *poly, long data) return ret / poly->total_divider; } -static inline u32 pvt_update(void __iomem *reg, u32 mask, u32 data) +#ifdef BT1_PVT_DIRECT_REG_ACCESS +static inline u32 pvt_readl(struct pvt_hwmon const *pvt, int reg) { + return readl(pvt->regs + reg); +} + +static inline u32 pvt_readl_relaxed(struct pvt_hwmon const *pvt, int reg) { + return readl_relaxed(pvt->regs + reg); +} + +static inline void pvt_writel(u32 data, struct pvt_hwmon const *pvt, int reg) { + writel(data, pvt->regs + reg); +} +#else +static inline u32 pvt_readl(struct pvt_hwmon const *pvt, int reg) { + struct arm_smccc_res res; + arm_smccc_smc(BAIKAL_SMC_PVT_ID, PVT_READ, pvt->pvt_id, reg, + 0, 0, 0, 0, &res); + return res.a0; +} + +static inline u32 pvt_readl_relaxed(struct pvt_hwmon const *pvt, int reg) { + return pvt_readl(pvt, reg); +} + +static inline void pvt_writel(u32 data, struct pvt_hwmon const *pvt, int reg) { + struct arm_smccc_res res; + arm_smccc_smc(BAIKAL_SMC_PVT_ID, PVT_WRITE, pvt->pvt_id, reg, + data, 0, 0, 0, &res); +} +#endif + +static inline u32 pvt_update(struct pvt_hwmon *pvt, int reg, u32 mask, u32 data) { u32 old; - old = readl_relaxed(reg); - writel((old & ~mask) | (data & mask), reg); + old = pvt_readl_relaxed(pvt, reg); + pvt_writel((old & ~mask) | (data & mask), pvt, reg); return old & mask; } @@ -161,8 +195,8 @@ static inline void pvt_set_mode(struct pvt_hwmon *pvt, u32 mode) mode = FIELD_PREP(PVT_CTRL_MODE_MASK, mode); - old = pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); - pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_MODE_MASK | PVT_CTRL_EN, + old = pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, 0); + pvt_update(pvt, PVT_CTRL, PVT_CTRL_MODE_MASK | PVT_CTRL_EN, mode | old); } @@ -179,8 +213,8 @@ static inline void pvt_set_trim(struct pvt_hwmon *pvt, u32 trim) trim = FIELD_PREP(PVT_CTRL_TRIM_MASK, trim); - old = pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); - pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_TRIM_MASK | PVT_CTRL_EN, + old = pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, 0); + pvt_update(pvt, PVT_CTRL, PVT_CTRL_TRIM_MASK | PVT_CTRL_EN, trim | old); } @@ -188,9 +222,9 @@ static inline void pvt_set_tout(struct pvt_hwmon *pvt, u32 tout) { u32 old; - old = pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); - writel(tout, pvt->regs + PVT_TTIMEOUT); - pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, old); + old = pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, 0); + pvt_writel(tout, pvt, PVT_TTIMEOUT); + pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, old); } /* @@ -237,7 +271,7 @@ static irqreturn_t pvt_soft_isr(int irq, void *data) * status before the next conversion happens. Threshold events will be * handled a bit later. */ - thres_sts = readl(pvt->regs + PVT_RAW_INTR_STAT); + thres_sts = pvt_readl(pvt, PVT_RAW_INTR_STAT); /* * Then lets recharge the PVT interface with the next sampling mode. @@ -260,14 +294,14 @@ static irqreturn_t pvt_soft_isr(int irq, void *data) */ mutex_lock(&pvt->iface_mtx); - old = pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_DVALID, + old = pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_DVALID, PVT_INTR_DVALID); - val = readl(pvt->regs + PVT_DATA); + val = pvt_readl(pvt, PVT_DATA); pvt_set_mode(pvt, pvt_info[pvt->sensor].mode); - pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_DVALID, old); + pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_DVALID, old); mutex_unlock(&pvt->iface_mtx); @@ -337,7 +371,7 @@ static int pvt_read_limit(struct pvt_hwmon *pvt, enum pvt_sensor_type type, u32 data; /* No need in serialization, since it is just read from MMIO. */ - data = readl(pvt->regs + pvt_info[type].thres_base); + data = pvt_readl(pvt, pvt_info[type].thres_base); if (is_low) data = FIELD_GET(PVT_THRES_LO_MASK, data); @@ -372,7 +406,7 @@ static int pvt_write_limit(struct pvt_hwmon *pvt, enum pvt_sensor_type type, return ret; /* Make sure the upper and lower ranges don't intersect. */ - limit = readl(pvt->regs + pvt_info[type].thres_base); + limit = pvt_readl(pvt, pvt_info[type].thres_base); if (is_low) { limit = FIELD_GET(PVT_THRES_HI_MASK, limit); data = clamp_val(data, PVT_DATA_MIN, limit); @@ -385,7 +419,7 @@ static int pvt_write_limit(struct pvt_hwmon *pvt, enum pvt_sensor_type type, mask = PVT_THRES_HI_MASK; } - pvt_update(pvt->regs + pvt_info[type].thres_base, mask, data); + pvt_update(pvt, pvt_info[type].thres_base, mask, data); mutex_unlock(&pvt->iface_mtx); @@ -439,14 +473,14 @@ static irqreturn_t pvt_hard_isr(int irq, void *data) * Mask the DVALID interrupt so after exiting from the handler a * repeated conversion wouldn't happen. */ - pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_DVALID, + pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_DVALID, PVT_INTR_DVALID); /* * Nothing special for alarm-less driver. Just read the data, update * the cache and notify a waiter of this event. */ - val = readl(pvt->regs + PVT_DATA); + val = pvt_readl(pvt, PVT_DATA); if (!(val & PVT_DATA_VALID)) { dev_err(pvt->dev, "Got IRQ when data isn't valid\n"); return IRQ_HANDLED; @@ -498,8 +532,8 @@ static int pvt_read_data(struct pvt_hwmon *pvt, enum pvt_sensor_type type, * Unmask the DVALID interrupt and enable the sensors conversions. * Do the reverse procedure when conversion is done. */ - pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_DVALID, 0); - pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, PVT_CTRL_EN); + pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_DVALID, 0); + pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, PVT_CTRL_EN); /* * Wait with timeout since in case if the sensor is suddenly powered @@ -510,8 +544,8 @@ static int pvt_read_data(struct pvt_hwmon *pvt, enum pvt_sensor_type type, timeout = 2 * usecs_to_jiffies(ktime_to_us(pvt->timeout)); ret = wait_for_completion_timeout(&cache->conversion, timeout); - pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); - pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_DVALID, + pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, 0); + pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_DVALID, PVT_INTR_DVALID); data = READ_ONCE(cache->data); @@ -637,7 +671,7 @@ static int pvt_read_trim(struct pvt_hwmon *pvt, long *val) { u32 data; - data = readl(pvt->regs + PVT_CTRL); + data = pvt_readl(pvt, PVT_CTRL); *val = FIELD_GET(PVT_CTRL_TRIM_MASK, data) * PVT_TRIM_STEP; return 0; @@ -916,6 +950,7 @@ static int pvt_request_regs(struct pvt_hwmon *pvt) { struct platform_device *pdev = to_platform_device(pvt->dev); struct resource *res; + int err = 0; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { @@ -923,27 +958,38 @@ static int pvt_request_regs(struct pvt_hwmon *pvt) return -EINVAL; } +#ifdef BT1_PVT_DIRECT_REG_ACCESS pvt->regs = devm_ioremap_resource(pvt->dev, res); if (IS_ERR(pvt->regs)) return PTR_ERR(pvt->regs); +#else + err = of_property_read_u32(pvt->dev->of_node, "pvt_id", &(pvt->pvt_id)); + if (err) { + dev_err(pvt->dev, "couldn't find pvt_id\n"); + return err; + } +#endif return 0; } +#ifdef BT1_PVT_DIRECT_REG_ACCESS static void pvt_disable_clks(void *data) { struct pvt_hwmon *pvt = data; clk_bulk_disable_unprepare(PVT_CLOCK_NUM, pvt->clks); } +#endif static int pvt_request_clks(struct pvt_hwmon *pvt) { - int ret; + int ret = 0; pvt->clks[PVT_CLOCK_APB].id = "pclk"; pvt->clks[PVT_CLOCK_REF].id = "ref"; +#ifdef BT1_PVT_DIRECT_REG_ACCESS ret = devm_clk_bulk_get(pvt->dev, PVT_CLOCK_NUM, pvt->clks); if (ret) { dev_err(pvt->dev, "Couldn't get PVT clocks descriptors\n"); @@ -961,8 +1007,11 @@ static int pvt_request_clks(struct pvt_hwmon *pvt) dev_err(pvt->dev, "Can't add PVT clocks disable action\n"); return ret; } - - return 0; +#else + pvt->clks[PVT_CLOCK_APB].clk = NULL; + pvt->clks[PVT_CLOCK_REF].clk = NULL; +#endif + return ret; } static int pvt_check_pwr(struct pvt_hwmon *pvt) @@ -981,45 +1030,48 @@ static int pvt_check_pwr(struct pvt_hwmon *pvt) * conversion. In the later case alas we won't be able to detect the * problem. */ - pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_ALL, PVT_INTR_ALL); - pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, PVT_CTRL_EN); + pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_ALL, PVT_INTR_ALL); + pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, PVT_CTRL_EN); pvt_set_tout(pvt, 0); - readl(pvt->regs + PVT_DATA); + pvt_readl(pvt, PVT_DATA); tout = PVT_TOUT_MIN / NSEC_PER_USEC; usleep_range(tout, 2 * tout); - data = readl(pvt->regs + PVT_DATA); + data = pvt_readl(pvt, PVT_DATA); if (!(data & PVT_DATA_VALID)) { ret = -ENODEV; dev_err(pvt->dev, "Sensor is powered down\n"); } - pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); + pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, 0); return ret; } static int pvt_init_iface(struct pvt_hwmon *pvt) { - unsigned long rate; u32 trim, temp; +#ifdef BT1_PVT_DIRECT_REG_ACCESS + unsigned long rate; + rate = clk_get_rate(pvt->clks[PVT_CLOCK_REF].clk); if (!rate) { dev_err(pvt->dev, "Invalid reference clock rate\n"); return -ENODEV; } +#endif /* * Make sure all interrupts and controller are disabled so not to * accidentally have ISR executed before the driver data is fully * initialized. Clear the IRQ status as well. */ - pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_ALL, PVT_INTR_ALL); - pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); - readl(pvt->regs + PVT_CLR_INTR); - readl(pvt->regs + PVT_DATA); + pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_ALL, PVT_INTR_ALL); + pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, 0); + pvt_readl(pvt, PVT_CLR_INTR); + pvt_readl(pvt, PVT_DATA); /* Setup default sensor mode, timeout and temperature trim. */ pvt_set_mode(pvt, pvt_info[pvt->sensor].mode); @@ -1038,6 +1090,7 @@ static int pvt_init_iface(struct pvt_hwmon *pvt) * polled. In that case the formulae will look a bit different: * Ttotal = 5 * (N / Fclk + Tmin) */ +#if defined(BT1_PVT_DIRECT_REG_ACCESS) #if defined(CONFIG_SENSORS_BT1_PVT_ALARMS) pvt->timeout = ktime_set(PVT_SENSORS_NUM * PVT_TOUT_DEF, 0); pvt->timeout = ktime_divns(pvt->timeout, rate); @@ -1047,6 +1100,9 @@ static int pvt_init_iface(struct pvt_hwmon *pvt) pvt->timeout = ktime_divns(pvt->timeout, rate); pvt->timeout = ktime_add_ns(pvt->timeout, PVT_TOUT_MIN); #endif +#else + pvt->timeout = ktime_set(0, PVT_TOUT_MIN * PVT_SENSORS_NUM); +#endif trim = PVT_TRIM_DEF; if (!of_property_read_u32(pvt->dev->of_node, @@ -1103,8 +1159,8 @@ static void pvt_disable_iface(void *data) struct pvt_hwmon *pvt = data; mutex_lock(&pvt->iface_mtx); - pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); - pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_DVALID, + pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, 0); + pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_DVALID, PVT_INTR_DVALID); mutex_unlock(&pvt->iface_mtx); } @@ -1126,8 +1182,8 @@ static int pvt_enable_iface(struct pvt_hwmon *pvt) * which theoretically may cause races. */ mutex_lock(&pvt->iface_mtx); - pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_DVALID, 0); - pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, PVT_CTRL_EN); + pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_DVALID, 0); + pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, PVT_CTRL_EN); mutex_unlock(&pvt->iface_mtx); return 0; @@ -1184,6 +1240,7 @@ static int pvt_probe(struct platform_device *pdev) static const struct of_device_id pvt_of_match[] = { { .compatible = "baikal,bt1-pvt" }, + { .compatible = "baikal,pvt" }, { } }; MODULE_DEVICE_TABLE(of, pvt_of_match); diff --git a/drivers/hwmon/bt1-pvt.h b/drivers/hwmon/bt1-pvt.h index 93b8dd5e7c94..0cea95b01c13 100644 --- a/drivers/hwmon/bt1-pvt.h +++ b/drivers/hwmon/bt1-pvt.h @@ -101,6 +101,13 @@ # define PVT_TOUT_DEF 0 #endif +#define BAIKAL_SMC_PVT_ID 0x82000001 +#define PVT_READ 0 +#define PVT_WRITE 1 +#ifndef CONFIG_ARM64 +#define BT1_PVT_DIRECT_REG_ACCESS +#endif + /* * enum pvt_sensor_type - Baikal-T1 PVT sensor types (correspond to each PVT * sampling mode) @@ -217,6 +224,7 @@ struct pvt_hwmon { enum pvt_sensor_type sensor; struct pvt_cache cache[PVT_SENSORS_NUM]; ktime_t timeout; + int pvt_id; }; /* diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index dce392839017..746565ec723e 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -545,7 +545,7 @@ config I2C_DESIGNWARE_PLATFORM tristate "Synopsys DesignWare Platform" depends on (ACPI && COMMON_CLK) || !ACPI select I2C_DESIGNWARE_CORE - select MFD_SYSCON if MIPS_BAIKAL_T1 + select MFD_SYSCON if MIPS_BAIKAL_T1 || ARCH_BAIKAL help If you say yes to this option, support will be included for the Synopsys DesignWare I2C adapter. diff --git a/drivers/input/serio/Kconfig b/drivers/input/serio/Kconfig index f39b7b3f7942..8e6b8b3ef478 100644 --- a/drivers/input/serio/Kconfig +++ b/drivers/input/serio/Kconfig @@ -293,6 +293,16 @@ config SERIO_SUN4I_PS2 To compile this driver as a module, choose M here: the module will be called sun4i-ps2. +config SERIO_TPLATFORMS + tristate "T-Plaftorms serio port support" + depends on I2C || SPI + help + This selects support for PS/2 ports emulated by EC found on + Baikal-M-based Mini-ITX board. + + To compile this driver as a module, choose M here: the + module will be called tp_serio. + config SERIO_GPIO_PS2 tristate "GPIO PS/2 bit banging driver" depends on GPIOLIB diff --git a/drivers/input/serio/Makefile b/drivers/input/serio/Makefile index 6d97bad7b844..a47319040c19 100644 --- a/drivers/input/serio/Makefile +++ b/drivers/input/serio/Makefile @@ -32,4 +32,5 @@ obj-$(CONFIG_SERIO_OLPC_APSP) += olpc_apsp.o obj-$(CONFIG_HYPERV_KEYBOARD) += hyperv-keyboard.o obj-$(CONFIG_SERIO_SUN4I_PS2) += sun4i-ps2.o obj-$(CONFIG_SERIO_GPIO_PS2) += ps2-gpio.o +obj-$(CONFIG_SERIO_TPLATFORMS) += tp_serio.o obj-$(CONFIG_USERIO) += userio.o diff --git a/drivers/input/serio/tp_serio.c b/drivers/input/serio/tp_serio.c new file mode 100644 index 000000000000..f2b0f78ffaa4 --- /dev/null +++ b/drivers/input/serio/tp_serio.c @@ -0,0 +1,749 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * T-Platforms serio port driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MODULE_DESCRIPTION("T-Platforms serio port driver"); +MODULE_LICENSE("GPL"); + +#define TP_SERIO_CHUNK_SIZE 4 +#define TP_SERIO_SPI_SPEED_DEFAULT 500000 +#define TP_SERIO_TX_QUEUE_SIZE 64 +#define TP_SERIO_REQUEST_DELAY 2 +#define TP_SERIO_POLL_READ_DELAY_MIN 1 +#define TP_SERIO_POLL_READ_DELAY_MAX 2 +#define TP_SERIO_POLL_WRITE_DELAY 1 +#define TP_SERIO_POLL_ERROR_DELAY 100 +#define TP_SERIO_POLL_READ_TIMEOUT 8 +#define TP_SERIO_POLL_WAIT_TIMEOUT 100 +#define TP_SERIO_CMD_QUERY 0xFC +#define TP_SERIO_CMD_RESET 0xFE + +static const unsigned char tp_serio_cmd_reset_response[] = { + TP_SERIO_CMD_RESET, 'P', 'S', '2' +}; + +struct tp_serio_tx { + bool has_data; + unsigned char data; +}; + +struct tp_serio_port { + struct serio *serio; + struct tp_serio_data *drv; + struct tp_serio_tx tx; + unsigned int id; + bool registered; +}; + +struct tp_serio_data { + struct i2c_client *dev_i2c; + struct spi_device *dev_spi; + struct task_struct *poll_task; + wait_queue_head_t poll_wq; + bool poll_ready; + int rx_irq; + unsigned int num_ports; + struct tp_serio_port *ports; +}; + +struct tp_serio_driver { +#if defined(CONFIG_I2C) + struct i2c_driver i2c; +#endif +#if defined(CONFIG_SPI) + struct spi_driver spi; +#endif +}; + +#if defined(CONFIG_I2C) +static int tp_serio_i2c_write(struct tp_serio_data *drv, + size_t size, void *data) +{ + struct i2c_msg m; + + m.addr = drv->dev_i2c->addr; + m.flags = 0; + m.len = size; + m.buf = data; + return i2c_transfer(drv->dev_i2c->adapter, &m, 1); +} + +static int tp_serio_i2c_read(struct tp_serio_data *drv, + size_t size, void *data) +{ + struct i2c_msg m; + + m.addr = drv->dev_i2c->addr; + m.flags = I2C_M_RD; + m.len = size; + m.buf = data; + return i2c_transfer(drv->dev_i2c->adapter, &m, 1); +} +#endif + +#if defined(CONFIG_SPI) +static int tp_serio_spi_write(struct tp_serio_data *drv, + size_t size, void *data) +{ + struct spi_transfer t = { + .speed_hz = TP_SERIO_SPI_SPEED_DEFAULT, + .tx_buf = data, + .len = size, + }; + struct spi_message m; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + return spi_sync(drv->dev_spi, &m); +} + +static int tp_serio_spi_read(struct tp_serio_data *drv, + size_t size, void *data) +{ + struct spi_transfer t = { + .speed_hz = TP_SERIO_SPI_SPEED_DEFAULT, + .rx_buf = data, + .len = size, + }; + struct spi_message m; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + return spi_sync(drv->dev_spi, &m); +} +#endif + +static int tp_serio_request(struct tp_serio_data *drv, + unsigned char cmd, + unsigned char *response) +{ + int result; + size_t size; + unsigned char message[TP_SERIO_CHUNK_SIZE]; + + result = -ENODEV; + memset(message, 0, sizeof(message)); + message[0] = cmd; +#if defined(CONFIG_SPI) + if (drv->dev_spi != NULL) { + size = sizeof(message); + result = tp_serio_spi_write(drv, size, message); + } else +#endif +#if defined(CONFIG_I2C) + if (drv->dev_i2c != NULL) { + size = 1; + result = tp_serio_i2c_write(drv, size, message); + } +#endif + ; + if (result < 0) + return result; + usleep_range(TP_SERIO_REQUEST_DELAY * 1000, + TP_SERIO_REQUEST_DELAY * 1000); +#if defined(CONFIG_I2C) + if (drv->dev_i2c != NULL) + result = tp_serio_i2c_read(drv, TP_SERIO_CHUNK_SIZE, response); + else +#endif +#if defined(CONFIG_SPI) + if (drv->dev_spi != NULL) + result = tp_serio_spi_read(drv, TP_SERIO_CHUNK_SIZE, response); +#endif + ; + return result; +} + +static int tp_serio_data_read(struct tp_serio_data *drv) +{ + int result; + size_t size; + size_t index; + size_t dbg_len; + char dbg_line[256]; + unsigned int port_id; + unsigned char message[TP_SERIO_CHUNK_SIZE]; + + memset(message, 0, sizeof(message)); + result = -ENODEV; +#if defined(CONFIG_I2C) + if (drv->dev_i2c != NULL) + result = tp_serio_i2c_read(drv, sizeof(message), message); + else +#endif +#if defined(CONFIG_SPI) + if (drv->dev_spi != NULL) + result = tp_serio_spi_read(drv, sizeof(message), message); +#endif + ; + if (result < 0) + return result; + +#if 0 + snprintf(dbg_line, ARRAY_SIZE(dbg_line) - 1, "raw read:"); + for (index = 0; index < ARRAY_SIZE(message); index++) { + dbg_len = strlen(dbg_line); + snprintf(dbg_line + dbg_len, + ARRAY_SIZE(dbg_line) - 1 - dbg_len, + " %02x", message[index]); + } +#if defined(CONFIG_I2C) + if (drv->dev_i2c != NULL) + dev_dbg(&drv->dev_i2c->dev, "%s\n", dbg_line); + else +#endif +#if defined(CONFIG_SPI) + if (drv->dev_spi != NULL) + dev_dbg(&drv->dev_spi->dev, "%s\n", dbg_line); +#endif + ; +#endif + + result = 0; + size = message[0] & 0x0F; + port_id = (message[0] >> 4) & 0x0F; + if ((size > 0) && (port_id < drv->num_ports)) { + snprintf(dbg_line, ARRAY_SIZE(dbg_line) - 1, + "port %u read:", port_id); + + if (size > (ARRAY_SIZE(message) - 1)) { + size = ARRAY_SIZE(message) - 1; + result = 1; + } + for (index = 0; index < size; index++) { + dbg_len = strlen(dbg_line); + snprintf(dbg_line + dbg_len, + ARRAY_SIZE(dbg_line) - 1 - dbg_len, + " %02x", message[index + 1]); + serio_interrupt(drv->ports[port_id].serio, + message[index + 1], 0); + } +#if defined(CONFIG_I2C) + if (drv->dev_i2c != NULL) + dev_dbg(&drv->dev_i2c->dev, "%s\n", dbg_line); + else +#endif +#if defined(CONFIG_SPI) + if (drv->dev_spi != NULL) + dev_dbg(&drv->dev_spi->dev, "%s\n", dbg_line); +#endif + ; + } + return result; +} + +static int tp_serio_data_write(struct tp_serio_data *drv, + u8 id, unsigned char data) +{ + int result; + size_t size; + unsigned char message[TP_SERIO_CHUNK_SIZE]; + struct tp_serio_port *port = drv->ports + id; + + result = -ENODEV; + memset(message, 0, sizeof(message)); + message[0] = (port->id << 4) | 0x01; + message[1] = data; +#if defined(CONFIG_SPI) + if (drv->dev_spi != NULL) { + size = sizeof(message); + dev_dbg(&drv->dev_spi->dev, + "port %u write: %02x\n", port->id, data); + result = tp_serio_spi_write(drv, size, message); + } else +#endif +#if defined(CONFIG_I2C) + if (drv->dev_i2c != NULL) { + size = 2; + dev_dbg(&drv->dev_i2c->dev, + "port %u write: %02x\n", port->id, data); + result = tp_serio_i2c_write(drv, size, message); + } +#endif + ; + return result; +} + +static void tp_serio_trigger_tx(struct tp_serio_data *drv) +{ + drv->poll_ready = true; + wake_up(&drv->poll_wq); +} + +static int tp_serio_write(struct serio *serio, unsigned char data) +{ + int result = -EINVAL; + struct tp_serio_data *drv; + struct tp_serio_port *port = (struct tp_serio_port *)serio->port_data; + + if (port != NULL) { + drv = port->drv; + if (port->tx.has_data) { + result = -ENOMEM; + } else { + port->tx.data = data; + port->tx.has_data = true; + result = 0; + } + tp_serio_trigger_tx(drv); + } + return result; +} + +static int tp_serio_start(struct serio *serio) +{ + struct tp_serio_port *port = (struct tp_serio_port *)serio->port_data; + + if (port != NULL) + port->registered = true; + return 0; +} + +static void tp_serio_stop(struct serio *serio) +{ + struct tp_serio_port *port = (struct tp_serio_port *)serio->port_data; + + if (port != NULL) + port->registered = false; +} + +static int tp_serio_create_port(struct tp_serio_data *drv, unsigned int id) +{ + struct serio *serio; + struct device *dev; + +#if defined(CONFIG_SPI) + if (drv->dev_spi != NULL) { + dev = &drv->dev_spi->dev; + } else +#endif +#if defined(CONFIG_I2C) + if (drv->dev_i2c != NULL) { + dev = &drv->dev_i2c->dev; + } else +#endif + { + return -ENODEV; + } + serio = devm_kzalloc(dev, sizeof(struct serio), GFP_KERNEL); + if (!serio) + return -ENOMEM; + strlcpy(serio->name, "tp_serio", sizeof(serio->name)); +#if defined(CONFIG_SPI) + if (drv->dev_spi != NULL) { + snprintf(serio->phys, sizeof(serio->phys), + "%s/port%u", dev_name(&drv->dev_spi->dev), id); + } else +#endif +#if defined(CONFIG_I2C) + if (drv->dev_i2c != NULL) { + snprintf(serio->phys, sizeof(serio->phys), + "%s/port%u", dev_name(&drv->dev_i2c->dev), id); + } +#endif + ; + serio->id.type = SERIO_8042; + serio->write = tp_serio_write; + serio->start = tp_serio_start; + serio->stop = tp_serio_stop; + serio->port_data = drv->ports + id; + drv->ports[id].serio = serio; + drv->ports[id].drv = drv; + drv->ports[id].id = id; + drv->ports[id].registered = false; + drv->ports[id].tx.has_data = false; + drv->ports[id].tx.data = 0x00; + return 0; +} + +static void tp_serio_destroy_port(struct tp_serio_data *drv, unsigned int id) +{ + if (drv->ports[id].registered) + serio_unregister_port(drv->ports[id].serio); +} + +static void tp_serio_read_error(struct tp_serio_data *drv, int error) +{ +#if defined(CONFIG_I2C) + if (drv->dev_i2c != NULL) + dev_dbg(&drv->dev_i2c->dev, + "i2c read failed: %d\n", error); + else +#endif +#if defined(CONFIG_SPI) + if (drv->dev_spi != NULL) + dev_dbg(&drv->dev_spi->dev, + "spi read failed: %d\n", error); +#endif + ; + msleep_interruptible(TP_SERIO_POLL_ERROR_DELAY); +} + +static void tp_serio_serio_process_tx(struct tp_serio_data *drv) +{ + unsigned int index; + + for (index = 0; index < drv->num_ports; index++) { + if (drv->ports[index].tx.has_data) { + tp_serio_data_write(drv, index, + drv->ports[index].tx.data); + drv->ports[index].tx.has_data = false; + usleep_range(TP_SERIO_POLL_WRITE_DELAY * 1000, + TP_SERIO_POLL_WRITE_DELAY * 1000); + } + } +} + +static int tp_serio_serio_process_rx(struct tp_serio_data *drv) +{ + int ret; + + do { + ret = tp_serio_data_read(drv); + usleep_range(TP_SERIO_POLL_READ_DELAY_MIN * 1000, + TP_SERIO_POLL_READ_DELAY_MAX * 1000); + } while (ret > 0); + if ((ret < 0) && (ret != -EAGAIN)) + tp_serio_read_error(drv, ret); + return ret; +} + +static int tp_serio_poll(void *data) +{ + struct tp_serio_data *drv = (struct tp_serio_data *)data; + const unsigned int poll_timeout = (drv->rx_irq < 0) ? + TP_SERIO_POLL_READ_TIMEOUT : + TP_SERIO_POLL_WAIT_TIMEOUT; + + while (!kthread_should_stop()) { + drv->poll_ready = false; + tp_serio_serio_process_tx(drv); + + if (drv->rx_irq < 0) + while (tp_serio_serio_process_rx(drv)) + ; + + wait_event_interruptible_timeout(drv->poll_wq, drv->poll_ready, + msecs_to_jiffies(poll_timeout)); + } + return 0; +} + +static irqreturn_t tp_serio_alert_handler(int irq, void *dev_id) +{ + struct tp_serio_data *drv = (struct tp_serio_data *)dev_id; + + while (tp_serio_serio_process_rx(drv)) + ; + return IRQ_HANDLED; +} + +static int tp_serio_device_reset(struct tp_serio_data *drv) +{ + int result; + unsigned char response[TP_SERIO_CHUNK_SIZE]; + + memset(response, 0, sizeof(response)); + result = tp_serio_request(drv, TP_SERIO_CMD_RESET, response); + if (result < 0) + return result; + if (!memcmp(response, tp_serio_cmd_reset_response, sizeof(response))) + result = 0; + else + result = -EINVAL; + return result; +} + +static int tp_serio_device_query(struct tp_serio_data *drv) +{ + int result; + unsigned char response[TP_SERIO_CHUNK_SIZE]; + + memset(response, 0, sizeof(response)); + result = tp_serio_request(drv, TP_SERIO_CMD_QUERY, response); + if (result < 0) + return result; + if (response[0] == TP_SERIO_CMD_QUERY) { + drv->num_ports = response[1]; + result = 0; + } else { + result = -EINVAL; + } + return result; +} + +#if defined(CONFIG_I2C) +static int tp_serio_probe_i2c(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct tp_serio_data *drv; + unsigned int index; + unsigned int free_index; + int error; + int irq; + struct serio *s; + + drv = devm_kzalloc(&client->dev, sizeof(*drv), GFP_KERNEL); + if (drv == NULL) + return -ENOMEM; + drv->dev_i2c = client; +#if defined(CONFIG_SPI) + drv->dev_spi = NULL; +#endif + if (tp_serio_device_reset(drv) < 0) { + dev_err(&client->dev, "no compatible device found at %s\n", + dev_name(&client->dev)); + return -ENODEV; + } + error = tp_serio_device_query(drv); + if (error || (drv->num_ports == 0)) { + dev_err(&client->dev, "no available ports found at %s\n", + dev_name(&client->dev)); + return -ENODEV; + } + drv->ports = devm_kzalloc(&client->dev, + sizeof(struct tp_serio_port) * drv->num_ports, + GFP_KERNEL); + if (drv->ports == NULL) + return -ENOMEM; + for (index = 0; index < drv->num_ports; index++) { + error = tp_serio_create_port(drv, index); + if (error) + goto err_out; + } + init_waitqueue_head(&drv->poll_wq); + drv->poll_ready = false; + drv->rx_irq = -1; + dev_set_drvdata(&client->dev, drv); + + for (index = 0; index < drv->num_ports; index++) { + s = drv->ports[index].serio; + dev_info(&client->dev, "%s port at %s\n", s->name, s->phys); + serio_register_port(s); + } + + if (client->dev.of_node != NULL) { + irq = of_irq_get(client->dev.of_node, 0); + if (irq >= 0) { + drv->rx_irq = irq; + error = devm_request_threaded_irq(&client->dev, irq, + NULL, tp_serio_alert_handler, + IRQF_TRIGGER_LOW | IRQF_ONESHOT, + "tp_serio", drv); + if (error) { + dev_set_drvdata(&client->dev, NULL); + index = drv->num_ports; + goto err_out; + } else { + tp_serio_alert_handler(drv->rx_irq, drv); + } + } + } + drv->poll_task = kthread_run(tp_serio_poll, drv, + "tp_serio i2c"); + return 0; +err_out: + for (free_index = 0; free_index < index; free_index++) + tp_serio_destroy_port(drv, free_index); + return error; +} + +static int tp_serio_remove_i2c(struct i2c_client *client) +{ + struct tp_serio_data *drv = + (struct tp_serio_data *)dev_get_drvdata(&client->dev); + unsigned int index; + + if (drv != NULL) { + kthread_stop(drv->poll_task); + for (index = 0; index < drv->num_ports; index++) + tp_serio_destroy_port(drv, index); + dev_set_drvdata(&client->dev, NULL); + } + return 0; +} +#endif + +#if defined(CONFIG_SPI) +static int tp_serio_probe_spi(struct spi_device *spi) +{ + struct tp_serio_data *drv; + unsigned int index; + unsigned int free_index; + int error; + int irq; + struct serio *s; + + drv = devm_kzalloc(&spi->dev, sizeof(*drv), GFP_KERNEL); + if (drv == NULL) + return -ENOMEM; +#if defined(CONFIG_I2C) + drv->dev_i2c = NULL; +#endif + drv->dev_spi = spi; + if (tp_serio_device_reset(drv) < 0) { + dev_err(&spi->dev, "no compatible device found at %s\n", + dev_name(&spi->dev)); + return -ENODEV; + } + error = tp_serio_device_query(drv); + if (error || (drv->num_ports == 0)) { + dev_err(&spi->dev, "no available ports found at %s\n", + dev_name(&spi->dev)); + return -ENODEV; + } + drv->ports = devm_kzalloc(&spi->dev, + sizeof(struct tp_serio_port) * drv->num_ports, + GFP_KERNEL); + if (drv->ports == NULL) + return -ENOMEM; + for (index = 0; index < drv->num_ports; index++) { + error = tp_serio_create_port(drv, index); + if (error) + goto err_out; + } + init_waitqueue_head(&drv->poll_wq); + drv->poll_ready = false; + drv->rx_irq = -1; + spi_set_drvdata(spi, drv); + + for (index = 0; index < drv->num_ports; index++) { + s = drv->ports[index].serio; + dev_info(&spi->dev, "%s port at %s\n", s->name, s->phys); + serio_register_port(s); + } + + if (spi->dev.of_node != NULL) { + irq = of_irq_get(spi->dev.of_node, 0); + if (irq >= 0) { + drv->rx_irq = irq; + error = devm_request_threaded_irq(&spi->dev, irq, + NULL, tp_serio_alert_handler, + IRQF_TRIGGER_LOW | IRQF_ONESHOT, + "tp_serio", drv); + if (error) { + spi_set_drvdata(spi, NULL); + index = drv->num_ports; + goto err_out; + } else { + tp_serio_alert_handler(drv->rx_irq, drv); + } + } + } + drv->poll_task = kthread_run(tp_serio_poll, drv, + "tp_serio spi"); + return 0; +err_out: + for (free_index = 0; free_index < index; free_index++) + tp_serio_destroy_port(drv, free_index); + return error; +} + +static int tp_serio_remove_spi(struct spi_device *spi) +{ + struct tp_serio_data *drv = + (struct tp_serio_data *)spi_get_drvdata(spi); + unsigned int index; + + if (drv != NULL) { + kthread_stop(drv->poll_task); + for (index = 0; index < drv->num_ports; index++) + tp_serio_destroy_port(drv, index); + spi_set_drvdata(spi, NULL); + } + return 0; +} +#endif + +static int tp_serio_register(struct tp_serio_driver *driver) +{ + int res = 0; +#if defined(CONFIG_I2C) + res = i2c_register_driver(THIS_MODULE, &driver->i2c); +#endif +#if defined(CONFIG_SPI) + if (res == 0) + res = spi_register_driver(&driver->spi); +#endif + return res; +} + +static void tp_serio_unregister(struct tp_serio_driver *driver) +{ +#if defined(CONFIG_SPI) + spi_unregister_driver(&driver->spi); +#endif +#if defined(CONFIG_I2C) + i2c_del_driver(&driver->i2c); +#endif +} + +static const struct of_device_id tp_serio_of_ids[] = { + { + .compatible = "tp,tp_serio", + }, + { } +}; +MODULE_DEVICE_TABLE(of, tp_serio_of_ids); + +#if defined(CONFIG_I2C) +static const struct i2c_device_id tp_serio_i2c_ids[] = { + { + .name = "tp_serio", + }, + { } +}; +MODULE_DEVICE_TABLE(i2c, tp_serio_i2c_ids); +#endif + +#if defined(CONFIG_SPI) +static const struct spi_device_id tp_serio_spi_ids[] = { + { + .name = "tp_serio", + }, + { } +}; +MODULE_DEVICE_TABLE(spi, tp_serio_spi_ids); +#endif + +static struct tp_serio_driver tp_serio_drv = { +#if defined(CONFIG_I2C) + { + .driver = { + .name = "tp_serio", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(tp_serio_of_ids) + }, + .probe = tp_serio_probe_i2c, + .remove = tp_serio_remove_i2c, + .id_table = tp_serio_i2c_ids + }, +#endif +#if defined(CONFIG_SPI) + { + .driver = { + .name = "tp_serio", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(tp_serio_of_ids) + }, + .probe = tp_serio_probe_spi, + .remove = tp_serio_remove_spi, + .id_table = tp_serio_spi_ids + } +#endif +}; + +module_driver(tp_serio_drv, tp_serio_register, tp_serio_unregister) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 0f5a49fc7c9e..b7cae77bae01 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -470,6 +470,24 @@ config HISI_HIKEY_USB switching between the dual-role USB-C port and the USB-A host ports using only one USB controller. +config TP_BMC + tristate "TF307/TF306 board management controller" + depends on I2C && SYSFS + depends on OF + select PINCTRL + select GENERIC_PINCONF + select SERIO + default y if ARCH_BAIKAL + help + Say Y here if you want to build a driver for BMC devices embedded into + some boards with Baikal BE-M1000 and BE-T1000 processors. The device main + purpose is the CPU kick-starting as well as some additional side-way + functionality like power on/off buttons state tracing and full device + powering off. + + If you choose to build module, its name will be tp-bmc. If unsure, + say N here. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index a086197af544..ae7bd2a8c813 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -59,3 +59,4 @@ obj-$(CONFIG_UACCE) += uacce/ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o obj-$(CONFIG_HI6421V600_IRQ) += hi6421v600-irq.o +obj-$(CONFIG_TP_BMC) += tp_bmc.o diff --git a/drivers/misc/tp_bmc.c b/drivers/misc/tp_bmc.c new file mode 100644 index 000000000000..0b320d3ffae4 --- /dev/null +++ b/drivers/misc/tp_bmc.c @@ -0,0 +1,747 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum I2C_REGS { + R_ID1 = 0, + R_ID2, + R_ID3, + R_ID4, + R_SOFTOFF_RQ, + R_PWROFF_RQ, + R_PWRBTN_STATE, + R_VERSION1, + R_VERSION2, + R_BOOTREASON, + R_BOOTREASON_ARG, + R_SCRATCH1, + R_SCRATCH2, + R_SCRATCH3, + R_SCRATCH4, + R_CAP, + R_GPIODIR0, + R_GPIODIR1, + R_GPIODIR2, + R_COUNT +}; + +#define BMC_ID1_VAL 0x49 +#define BMC_ID2_VAL 0x54 +#define BMC_ID3_VAL 0x58 +#define BMC_ID4_VAL0 0x32 +#define BMC_ID4_VAL1 0x2 + +#define BMC_VERSION1 0 +#define BMC_VERSION2 2 +#define BMC_VERSION2_3 3 + +#define BMC_CAP_PWRBTN 0x1 +#define BMC_CAP_TOUCHPAD 0x2 +#define BMC_CAP_RTC 0x4 +#define BMC_CAP_FRU 0x8 +#define BMC_CAP_GPIODIR 0x10 + +#define BMC_SERIO_BUFSIZE 7 + +#define POLL_JIFFIES 100 + +struct bmc_poll_data { + struct i2c_client *c; +}; + +static struct i2c_client *bmc_i2c; +static struct i2c_client *rtc_i2c; +static struct i2c_driver mitx2_bmc_i2c_driver; +static struct input_dev *button_dev; +static struct bmc_poll_data poll_data; +static struct task_struct *polling_task; +#ifdef CONFIG_SERIO +static struct i2c_client *serio_i2c; +static struct task_struct *touchpad_task; +#endif +static u8 bmc_proto_version[3]; +static u8 bmc_bootreason[2]; +static u8 bmc_scratch[4]; +static int bmc_cap; +static const char input_name[] = "BMC input dev"; +static u8 prev_ret; + +/* BMC RTC */ +static int +bmc_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct i2c_client *client = to_i2c_client(dev); + uint8_t rtc_buf[8]; + struct i2c_msg msg; + int t; + int rc; + + msg.addr = client->addr; + msg.flags = I2C_M_RD; + msg.len = 8; + msg.buf = rtc_buf; + rc = i2c_transfer(client->adapter, &msg, 1); + if (rc != 1) { + dev_err(dev, "rtc_read_time: i2c_transfer error %d\n", rc); + return rc; + } + + tm->tm_sec = bcd2bin(rtc_buf[0] & 0x7f); + tm->tm_min = bcd2bin(rtc_buf[1] & 0x7f); + tm->tm_hour = bcd2bin(rtc_buf[2] & 0x3f); + if (rtc_buf[3] & (1 << 6)) /* PM */ + tm->tm_hour += 12; + tm->tm_mday = bcd2bin(rtc_buf[4] & 0x3f); + tm->tm_mon = bcd2bin(rtc_buf[5] & 0x1f); + t = rtc_buf[5] >> 5; + tm->tm_wday = (t == 7) ? 0 : t; + tm->tm_year = bcd2bin(rtc_buf[6]) + 100; /* year since 1900 */ + tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); + tm->tm_isdst = 0; + + return rtc_valid_tm(tm); +} + +static int +bmc_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct i2c_client *client = to_i2c_client(dev); + uint8_t rtc_buf[8]; + struct i2c_msg msg; + int rc; + uint8_t seconds, minutes, hours, wday, mday, month, years; + + seconds = bin2bcd(tm->tm_sec); + minutes = bin2bcd(tm->tm_min); + hours = bin2bcd(tm->tm_hour); + wday = tm->tm_wday ? tm->tm_wday : 0x7; + mday = bin2bcd(tm->tm_mday); + month = bin2bcd(tm->tm_mon); + years = bin2bcd(tm->tm_year % 100); + + /* Need sanity check??? */ + rtc_buf[0] = seconds; + rtc_buf[1] = minutes; + rtc_buf[2] = hours; + rtc_buf[3] = 0; + rtc_buf[4] = mday; + rtc_buf[5] = month | (wday << 5); + rtc_buf[6] = years; + rtc_buf[7] = 0; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = 8; + msg.buf = rtc_buf; + dev_dbg(dev, "rtc_set_time: %08x-%08x\n", *(uint32_t *)&rtc_buf[0], + *(uint32_t *)&rtc_buf[4]); + rc = i2c_transfer(client->adapter, &msg, 1); + if (rc != 1) + dev_err(dev, "i2c write: %d\n", rc); + + return (rc == 1) ? 0 : -EIO; +} + +static const struct rtc_class_ops +bmc_rtc_ops = { + .read_time = bmc_rtc_read_time, + .set_time = bmc_rtc_set_time, +}; + +#ifdef CONFIG_SERIO +/* BMC serio (PS/2 touchpad) interface */ + +static int bmc_serio_write(struct serio *id, unsigned char val) +{ + struct i2c_client *client = id->port_data; + uint8_t buf[4]; + struct i2c_msg msg; + int rc; + + buf[0] = val; + msg.addr = client->addr; + msg.flags = 0; + msg.len = 1; + msg.buf = buf; + dev_dbg(&client->dev, "bmc_serio_write: %02x\n", val); + rc = i2c_transfer(client->adapter, &msg, 1); + if (rc != 1) + dev_err(&client->dev, "i2c write: %d\n", rc); + + return (rc == 1) ? 0 : -EIO; +} + +/* returns: -1 on error, +1 if more data available, 0 otherwise */ +static int bmc_serio_read(struct i2c_client *client) +{ + struct serio *serio = dev_get_drvdata(&client->dev); + int i, rc, cnt; + uint8_t buf[BMC_SERIO_BUFSIZE]; + struct i2c_msg msg; + + msg.addr = client->addr; + msg.flags = I2C_M_RD; + msg.len = BMC_SERIO_BUFSIZE; + msg.buf = buf; + rc = i2c_transfer(client->adapter, &msg, 1); + if (rc != 1) { + dev_err(&client->dev, "bmc_serio_read: i2c_transfer error %d\n", rc); + return -1; + } + + cnt = buf[0]; + rc = 0; + if (cnt > BMC_SERIO_BUFSIZE - 1) { + cnt = BMC_SERIO_BUFSIZE - 1; + rc = 1; + } + + for (i = 0; i < cnt; i++) { + serio_interrupt(serio, buf[i + 1], 0); + } + + return 0; +} + +int +touchpad_poll_fn(void *data) { + int ret; + + while (1) { + if (kthread_should_stop()) + break; + while ((ret = bmc_serio_read(serio_i2c)) > 0) + ; + if (ret < 0) { + msleep_interruptible(10000); + } + msleep_interruptible(10); + } + return 0; +} +#endif /* CONFIG_SERIO */ + +#ifdef CONFIG_PINCTRL +static uint8_t bmc_pincf_state [3]; +#define BMC_NPINS (sizeof(bmc_pincf_state) * 8) + +static struct pinctrl_pin_desc bmc_pin_desc[BMC_NPINS] = { + PINCTRL_PIN(0, "P0"), + PINCTRL_PIN(1, "P1"), + PINCTRL_PIN(2, "P2"), + PINCTRL_PIN(3, "P3"), + PINCTRL_PIN(4, "P4"), + PINCTRL_PIN(5, "P5"), + PINCTRL_PIN(6, "P6"), + PINCTRL_PIN(7, "P7"), + PINCTRL_PIN(8, "P8"), + PINCTRL_PIN(9, "P9"), + PINCTRL_PIN(10, "P10"), + PINCTRL_PIN(11, "P11"), + PINCTRL_PIN(12, "P12"), + PINCTRL_PIN(13, "P13"), + PINCTRL_PIN(14, "P14"), + PINCTRL_PIN(15, "P15"), + PINCTRL_PIN(16, "P16"), + PINCTRL_PIN(17, "P17"), + PINCTRL_PIN(18, "P18"), + PINCTRL_PIN(19, "P19"), + PINCTRL_PIN(20, "P20"), + PINCTRL_PIN(21, "P21"), + PINCTRL_PIN(22, "P22"), + PINCTRL_PIN(23, "P23"), +}; + +#define PCTRL_DEV "bmc_pinctrl" + +static int bmc_pin_config_get(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *config) +{ + int idx, bit; + + if (pin > BMC_NPINS) + return -EINVAL; + + idx = pin >> 3; + bit = pin & 7; + + *config = !!(bmc_pincf_state[idx] & (1 << bit)); + return 0; +} + +static int bmc_pin_config_set(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *config, + unsigned nc) +{ + int idx, bit; + enum pin_config_param param; + int arg; + + if (pin > BMC_NPINS) + return -EINVAL; + + idx = pin >> 3; + bit = pin & 7; + + param = pinconf_to_config_param (*config); + arg = pinconf_to_config_argument (*config); + if (param != PIN_CONFIG_OUTPUT) + return -EINVAL; + + if (arg) + bmc_pincf_state[idx] |= (1 << bit); + else + bmc_pincf_state[idx] &= ~(1 << bit); +dev_dbg(&bmc_i2c->dev, "bmc_pin_config_set: pin %u, dir %lu\n", pin, *config); + + return i2c_smbus_write_byte_data(bmc_i2c, R_GPIODIR0 + idx, bmc_pincf_state[idx]); +} + +void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned long config); + +void pinctrl_utils_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps); + +static const struct pinconf_ops bmc_confops = { + .pin_config_get = bmc_pin_config_get, + .pin_config_set = bmc_pin_config_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +static int bmc_groups_count(struct pinctrl_dev *pctldev) +{ + return 0; +} + +static const char *bmc_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return NULL; +} + +static const struct pinctrl_ops bmc_ctrl_ops = { + .get_groups_count = bmc_groups_count, + .get_group_name = bmc_group_name, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_free_map, +}; + +static struct pinctrl_desc bmc_pincrtl_desc = { + .name = PCTRL_DEV, + .pins = bmc_pin_desc, + .pctlops = &bmc_ctrl_ops, + .npins = BMC_NPINS, + .confops = &bmc_confops, +}; + +static struct pinctrl_dev *bmc_pinctrl_dev; + +static int bmc_pinctrl_register(struct device *dev) +{ + struct pinctrl_dev *pctrl_dev; + struct platform_device *pbdev; + + pbdev = platform_device_alloc(PCTRL_DEV, -1); + pbdev->dev.parent = dev; + pbdev->dev.of_node = of_find_node_by_name(dev->of_node, "bmc_pinctrl"); + platform_device_add(pbdev); + pctrl_dev = devm_pinctrl_register(&pbdev->dev, &bmc_pincrtl_desc, NULL); + if (IS_ERR(pctrl_dev)) { + dev_err(&pbdev->dev, "Can't register pinctrl (%ld)\n", PTR_ERR(pctrl_dev)); + return PTR_ERR(pctrl_dev); + } else { + dev_info(&pbdev->dev, "BMC pinctrl registered\n"); + bmc_pinctrl_dev = pctrl_dev; + } + /* reset all pins to default state */ + i2c_smbus_write_byte_data(to_i2c_client(dev), R_GPIODIR0, 0); + i2c_smbus_write_byte_data(to_i2c_client(dev), R_GPIODIR1, 0); + i2c_smbus_write_byte_data(to_i2c_client(dev), R_GPIODIR2, 0); + return 0; +} + +static void bmc_pinctrl_unregister(void) +{ + if (bmc_pinctrl_dev) + devm_pinctrl_unregister(&bmc_i2c->dev, bmc_pinctrl_dev); +} + +#endif + +void +bmc_pwroff_rq(void) { + int ret = 0; + + dev_info(&bmc_i2c->dev, "Write reg R_PWROFF_RQ\n"); + ret = i2c_smbus_write_byte_data(bmc_i2c, R_PWROFF_RQ, 0x01); + dev_info(&bmc_i2c->dev, "ret: %i\n", ret); +} + +int +pwroff_rq_poll_fn(void *data) { + int ret; + + while (1) { + if (kthread_should_stop()) + break; + dev_dbg(&poll_data.c->dev, "Polling\n"); + ret = i2c_smbus_read_byte_data(poll_data.c, R_SOFTOFF_RQ); + dev_dbg(&poll_data.c->dev, "Polling returned: %i\n", ret); + if (prev_ret != ret) { + dev_info(&poll_data.c->dev, "key change [%i]\n", ret); + if (ret < 0) { + dev_err(&poll_data.c->dev, + "Could not read register %x\n", + R_SOFTOFF_RQ); + return -EIO; + } else if (ret != 0) { + dev_info(&poll_data.c->dev, + "PWROFF \"irq\" detected [%i]\n", ret); + input_event(button_dev, EV_KEY, KEY_POWER, 1); + } else { + input_event(button_dev, EV_KEY, KEY_POWER, 0); + } + input_sync(button_dev); + } + prev_ret = ret; + + msleep_interruptible(100); + } + do_exit(1); + return 0; +} + +static int +mitx2_bmc_validate(struct i2c_client *client) { + int ret = 0; + int i = 0; + static const u8 regs[] = {R_ID1, R_ID2, R_ID3}; + static const u8 vals[] = {BMC_ID1_VAL, BMC_ID2_VAL, BMC_ID3_VAL}; + + bmc_proto_version[0] = 0; + bmc_proto_version[1] = 0; + bmc_proto_version[2] = 0; + + for (i = 0; i < ARRAY_SIZE(regs); i++) { + ret = i2c_smbus_read_byte_data(client, regs[i]); + if (ret < 0) { + dev_err(&client->dev, "Could not read register %x\n", + regs[i]); + return -EIO; + } + if (ret != vals[i]) { + dev_err(&client->dev, + "Bad value [0x%02x] in register 0x%02x, should be [0x%02x]\n", + ret, regs[i], vals[i]); + + return -ENODEV; + } + } + ret = i2c_smbus_read_byte_data(client, R_ID4); + if (ret < 0) { + dev_err(&client->dev, "Could not read register %x\n", R_ID4); + return -EIO; + } + if (ret == BMC_ID4_VAL0) { + bmc_proto_version[0] = 0; + } else if (ret == BMC_ID4_VAL1) { + bmc_proto_version[0] = 2; + ret = i2c_smbus_read_byte_data(client, R_VERSION1); + if (ret < 0) { + dev_err(&client->dev, "Could not read register %x\n", + R_VERSION1); + return -EIO; + } + bmc_proto_version[1] = ret; + ret = i2c_smbus_read_byte_data(client, R_VERSION2); + if (ret < 0) { + dev_err(&client->dev, "Could not read register %x\n", + R_VERSION2); + return -EIO; + } + bmc_proto_version[2] = ret; + ret = i2c_smbus_read_byte_data(client, R_BOOTREASON); + if (ret < 0) { + dev_err(&client->dev, "Could not read register %x\n", + R_BOOTREASON); + return -EIO; + } + bmc_bootreason[0] = ret; + dev_info(&client->dev, "BMC bootreason[0]->%i\n", ret); + ret = i2c_smbus_read_byte_data(client, R_BOOTREASON_ARG); + if (ret < 0) { + dev_err(&client->dev, "Could not read register %x\n", + R_BOOTREASON_ARG); + return -EIO; + } + bmc_bootreason[1] = ret; + dev_info(&client->dev, "BMC bootreason[1]->%i\n", ret); + for (i = R_SCRATCH1; i <= R_SCRATCH4; i++) { + ret = i2c_smbus_read_byte_data(client, i); + if (ret < 0) { + dev_err(&client->dev, + "Could not read register %x\n", i); + return -EIO; + } + bmc_scratch[i - R_SCRATCH1] = ret; + } + if (bmc_proto_version[2] >= BMC_VERSION2_3) { + ret = i2c_smbus_read_byte_data(client, R_CAP); + if (ret >= 0) + bmc_cap = ret; + dev_info(&client->dev, + "BMC extended capabilities %x\n", bmc_cap); + } else { + bmc_cap = BMC_CAP_PWRBTN; + } + } else { + dev_err(&client->dev, "Bad value [0x%02x] in register 0x%02x\n", + ret, R_ID4); + return -ENODEV; + } + dev_info(&client->dev, "BMC seems to be valid\n"); + return 0; +} + +static int +bmc_create_client_devices(struct device *bmc_dev) +{ + int ret = 0; + struct rtc_device *rtc_dev; + struct i2c_client *client = to_i2c_client(bmc_dev); + int client_addr = client->addr + 1; + + if (bmc_cap & BMC_CAP_TOUCHPAD) { +#ifdef CONFIG_SERIO + struct serio *serio; + serio_i2c = i2c_new_ancillary_device(client, + "bmc_serio", client_addr); + if (IS_ERR(serio_i2c)) { + dev_err(&client->dev, "Can't get serio secondary\n"); + serio_i2c = NULL; + ret = -ENOMEM; + goto fail; + } + serio = devm_kzalloc(&serio_i2c->dev, sizeof(struct serio), GFP_KERNEL); + if (!serio) { + dev_err(&serio_i2c->dev, "Can't allocate serio\n"); + ret = -ENOMEM; + i2c_unregister_device(serio_i2c); + serio_i2c = NULL; + goto skip_tp; + } + serio->write = bmc_serio_write; + serio->port_data = serio_i2c; + serio->id.type = SERIO_PS_PSTHRU; + serio_register_port(serio); + dev_set_drvdata(&serio_i2c->dev, serio); + touchpad_task = kthread_run(touchpad_poll_fn, NULL, "BMC serio poll task"); + +skip_tp: +#endif + client_addr++; + } + + if (bmc_cap & BMC_CAP_RTC) { + rtc_i2c = i2c_new_ancillary_device(client, + "bmc_rtc", client_addr); + if (IS_ERR(rtc_i2c)) { + dev_err(&client->dev, "Can't get RTC secondary\n"); + rtc_i2c = NULL; + ret = -ENOMEM; + goto fail; + } + + rtc_dev = devm_rtc_device_register(&rtc_i2c->dev, "bmc_rtc", + &bmc_rtc_ops, THIS_MODULE); + if (IS_ERR(rtc_dev)) { + ret = PTR_ERR(rtc_dev); + dev_err(&client->dev, "Failed to register RTC device: %d\n", + ret); + i2c_unregister_device(rtc_i2c); + rtc_i2c = NULL; + } +fail: + client_addr++; + } + +#ifdef CONFIG_PINCTRL + if (bmc_cap & BMC_CAP_GPIODIR || 1 /*vvv*/) + bmc_pinctrl_register(bmc_dev); +#endif + + return ret; +} + +static int +mitx2_bmc_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int err = 0; + int i = 0; + + dev_info(&client->dev, "mitx2 bmc probe\n"); + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) + return -ENODEV; + + for (i = 0; i < 10; i++) { + err = mitx2_bmc_validate(client); + if (!err) + break; + msleep_interruptible(20); + } + if (err) + return err; + + if (bmc_cap & BMC_CAP_PWRBTN) { + button_dev = input_allocate_device(); + if (!button_dev) { + dev_err(&client->dev, "Not enough memory\n"); + return -ENOMEM; + } + + button_dev->id.bustype = BUS_I2C; + button_dev->dev.parent = &client->dev; + button_dev->name = input_name; + button_dev->phys = "bmc-input0"; + button_dev->evbit[0] = BIT_MASK(EV_KEY); + button_dev->keybit[BIT_WORD(KEY_POWER)] = BIT_MASK(KEY_POWER); + + err = input_register_device(button_dev); + if (err) { + dev_err(&client->dev, "Failed to register device\n"); + input_free_device(button_dev); + return err; + } + + dev_info(&client->dev, "Starting polling thread\n"); + poll_data.c = client; + polling_task = kthread_run(pwroff_rq_poll_fn, NULL, "BMC poll task"); + } + + if (bmc_cap || 1 /*vvv*/) + err = bmc_create_client_devices(&client->dev); + + bmc_i2c = client; + /* register as poweroff handler */ + pm_power_off = bmc_pwroff_rq; + + return 0; +} + +static int +mitx2_bmc_i2c_remove(struct i2c_client *client) +{ +#ifdef CONFIG_SERIO + struct serio *serio; +#endif + + if (button_dev) { + kthread_stop(polling_task); + input_unregister_device(button_dev); + } +#ifdef CONFIG_SERIO + if (serio_i2c) { + kthread_stop(touchpad_task); + serio = dev_get_drvdata(&serio_i2c->dev); + serio_unregister_port(serio); + i2c_unregister_device(serio_i2c); + } +#endif + if (rtc_i2c) + i2c_unregister_device(rtc_i2c); +#ifdef CONFIG_PINCTRL + bmc_pinctrl_unregister(); +#endif + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id mitx2_bmc_of_match[] = { + { .compatible = "tp,mitx2-bmc" }, + {} +}; +MODULE_DEVICE_TABLE(of, mitx2_bmc_of_match); +#endif + +static const struct i2c_device_id mitx2_bmc_i2c_id[] = { + { "mitx2_bmc", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, mitx2_bmc_i2c_id); + +static ssize_t +version_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%i.%i.%i\n", bmc_proto_version[0], + bmc_proto_version[1], bmc_proto_version[2]); +} + +static struct kobj_attribute version_attribute = + __ATTR(version, 0664, version_show, NULL); + +static ssize_t +bootreason_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%i\n", (bmc_bootreason[0] | + (bmc_bootreason[1] << 8))); +} + +static struct kobj_attribute bootreason_attribute = + __ATTR(bootreason, 0664, bootreason_show, NULL); + +static ssize_t +scratch_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%i\n", (bmc_scratch[0] | (bmc_scratch[1] << 8) | + (bmc_scratch[2] << 16) | (bmc_scratch[3] << 24))); +} + +static struct kobj_attribute scratch_attribute = + __ATTR(scratch, 0664, scratch_show, NULL); + +static struct attribute *bmc_attrs[] = { + &version_attribute.attr, + &bootreason_attribute.attr, + &scratch_attribute.attr, + NULL, +}; + +ATTRIBUTE_GROUPS(bmc); + +static struct i2c_driver mitx2_bmc_i2c_driver = { + .driver = { + .name = "mitx2-bmc", + .of_match_table = of_match_ptr(mitx2_bmc_of_match), + .groups = bmc_groups, + }, + .probe = mitx2_bmc_i2c_probe, + .remove = mitx2_bmc_i2c_remove, + .id_table = mitx2_bmc_i2c_id, +}; +module_i2c_driver(mitx2_bmc_i2c_driver); + +MODULE_AUTHOR("Konstantin Kirik"); +MODULE_DESCRIPTION("mITX2 BMC driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("serial:bmc"); diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 929cfc22cd0c..9981153b8dfe 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -66,6 +66,16 @@ config DWMAC_ANARION This selects the Anarion SoC glue layer support for the stmmac driver. +config DWMAC_BAIKAL + tristate "Baikal Electronics DWMAC support" + default y if MIPS_BAIKAL || ARCH_BAIKAL + depends on OF + help + Support for Baikal Electronics DWMAC Ethernet. + + This selects the Baikal-T/M SoC glue layer support for the stmmac + device driver. + config DWMAC_INGENIC tristate "Ingenic MAC support" default MACH_INGENIC diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index d4e12e9ace4f..ad138062e199 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -14,6 +14,7 @@ stmmac-$(CONFIG_STMMAC_SELFTESTS) += stmmac_selftests.o # Ordering matters. Generic driver must be last. obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o obj-$(CONFIG_DWMAC_ANARION) += dwmac-anarion.o +obj-$(CONFIG_DWMAC_BAIKAL) += dwmac-baikal.o obj-$(CONFIG_DWMAC_INGENIC) += dwmac-ingenic.o obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-baikal.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-baikal.c new file mode 100644 index 000000000000..2826eb35210a --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-baikal.c @@ -0,0 +1,230 @@ +/* + * Baikal Electronics SoCs DWMAC glue layer + * + * Copyright (C) 2015,2016 Baikal Electronics JSC + * Author: + * Dmitry Dunaev + * All bugs by Alexey Sheplyakov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +#include "stmmac.h" +#include "stmmac_platform.h" +#include "common.h" +#include "dwmac_dma.h" +#include "dwmac1000_dma.h" + +#define MAC_GPIO 0x000000e0 /* GPIO register */ +#define MAC_GPIO_GPO0 (1 << 8) /* 0-output port */ + +struct baikal_dwmac { + struct device *dev; + struct clk *tx2_clk; +}; + +static void clear_phy_reset(void __iomem *ioaddr) +{ + u32 value; + value = readl(ioaddr + MAC_GPIO); + value |= MAC_GPIO_GPO0; + writel(value, ioaddr + MAC_GPIO); +} + +static int baikal_dwmac_dma_reset(void __iomem *ioaddr) +{ + int err; + u32 value = readl(ioaddr + DMA_BUS_MODE); + + /* DMA SW reset */ + value |= DMA_BUS_MODE_SFT_RESET; + writel(value, ioaddr + DMA_BUS_MODE); + + udelay(10); + clear_phy_reset(ioaddr); + pr_info("PHY re-inited for Baikal DWMAC\n"); + + err = readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, + !(value & DMA_BUS_MODE_SFT_RESET), + 10000, 1000000); + if (err) + return -EBUSY; + + return 0; +} + +static const struct stmmac_dma_ops baikal_dwmac_dma_ops = { + .reset = baikal_dwmac_dma_reset, + .init = dwmac1000_dma_init, + .init_rx_chan = dwmac1000_dma_init_rx, + .init_tx_chan = dwmac1000_dma_init_tx, + .axi = dwmac1000_dma_axi, + .dump_regs = dwmac1000_dump_dma_regs, + .dma_rx_mode = dwmac1000_dma_operation_mode_rx, + .dma_tx_mode = dwmac1000_dma_operation_mode_tx, + .enable_dma_transmission = dwmac_enable_dma_transmission, + .enable_dma_irq = dwmac_enable_dma_irq, + .disable_dma_irq = dwmac_disable_dma_irq, + .start_tx = dwmac_dma_start_tx, + .stop_tx = dwmac_dma_stop_tx, + .start_rx = dwmac_dma_start_rx, + .stop_rx = dwmac_dma_stop_rx, + .dma_interrupt = dwmac_dma_interrupt, + .get_hw_feature = dwmac1000_get_hw_feature, + .rx_watchdog = dwmac1000_rx_watchdog, +}; + +static struct mac_device_info* baikal_dwmac_setup(void *ppriv) +{ + struct mac_device_info *mac, *old_mac; + struct stmmac_priv *priv = ppriv; + int ret; + + mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); + if (!mac) + return NULL; + + clear_phy_reset(priv->ioaddr); + + mac->dma = &baikal_dwmac_dma_ops; + old_mac = priv->hw; + priv->hw = mac; + ret = dwmac1000_setup(priv); + priv->hw = old_mac; + if (ret) { + dev_err(priv->device, "dwmac1000_setup: error %d", ret); + return NULL; + } + return mac; +} + +static void baikal_dwmac_fix_mac_speed(void *priv, unsigned int speed) +{ + struct baikal_dwmac *dwmac = priv; + unsigned long tx2_clk_freq = 0; + dev_info(dwmac->dev, "fix_mac_speed new speed %u\n", speed); + switch (speed) { + case SPEED_1000: + tx2_clk_freq = 250000000; + break; + case SPEED_100: + tx2_clk_freq = 50000000; + break; + case SPEED_10: + tx2_clk_freq = 5000000; + break; + } + if (dwmac->tx2_clk && tx2_clk_freq != 0) { + dev_info(dwmac->dev, "setting TX2 clock frequency to %lu\n", tx2_clk_freq); + clk_set_rate(dwmac->tx2_clk, tx2_clk_freq); + + } + +} + + +static int dwmac_baikal_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct baikal_dwmac *dwmac; + int ret; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + if (ret) { + dev_warn(&pdev->dev, "No suitable DMA available\n"); + return ret; + } + + if (pdev->dev.of_node) { + plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) { + dev_err(&pdev->dev, "dt configuration failed\n"); + return PTR_ERR(plat_dat); + } + } else { + plat_dat = dev_get_platdata(&pdev->dev); + if (!plat_dat) { + dev_err(&pdev->dev, "no platform data provided\n"); + return -EINVAL; + } + + /* Set default value for multicast hash bins */ + plat_dat->multicast_filter_bins = HASH_TABLE_SIZE; + + /* Set default value for unicast filter entries */ + plat_dat->unicast_filter_entries = 1; + } + + dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); + if (!dwmac) { + ret = -ENOMEM; + goto err_remove_config_dt; + } + + dwmac->dev = &pdev->dev; + dwmac->tx2_clk = devm_clk_get(dwmac->dev, "tx2_clk"); + if (IS_ERR(dwmac->tx2_clk)) { + dev_warn(&pdev->dev, "coldn't get TX2 clock\n"); + dwmac->tx2_clk = NULL; + } + plat_dat->fix_mac_speed = baikal_dwmac_fix_mac_speed; + plat_dat->bsp_priv = dwmac; + + plat_dat->has_gmac = 1; + plat_dat->enh_desc = 1; + plat_dat->tx_coe = 1; + plat_dat->rx_coe = 1; + // TODO: set CSR correct clock in dts! + plat_dat->clk_csr = 3; + plat_dat->setup = baikal_dwmac_setup; + + dev_info(&pdev->dev, "Baikal Electronics DWMAC glue driver\n"); + + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + goto err_remove_config_dt; + + return 0; + +err_remove_config_dt: + stmmac_remove_config_dt(pdev, plat_dat); + + return ret; +} + +static const struct of_device_id dwmac_baikal_match[] = { + { .compatible = "be,dwmac-3.710"}, + { .compatible = "be,dwmac"}, + { } +}; +MODULE_DEVICE_TABLE(of, dwmac_baikal_match); + +static struct platform_driver dwmac_baikal_driver = { + .probe = dwmac_baikal_probe, + .remove = stmmac_pltfr_remove, + .driver = { + .name = "baikal-dwmac", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = of_match_ptr(dwmac_baikal_match), + }, +}; +module_platform_driver(dwmac_baikal_driver); + +MODULE_DESCRIPTION("Baikal dwmac glue driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c index 76edb9b72675..7b8a955d98a9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c @@ -563,3 +563,4 @@ int dwmac1000_setup(struct stmmac_priv *priv) return 0; } +EXPORT_SYMBOL_GPL(dwmac1000_setup); diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c index f5581db0ba9b..40844816426e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c @@ -16,7 +16,7 @@ #include "dwmac1000.h" #include "dwmac_dma.h" -static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) +void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) { u32 value = readl(ioaddr + DMA_AXI_BUS_MODE); int i; @@ -69,9 +69,10 @@ static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) writel(value, ioaddr + DMA_AXI_BUS_MODE); } +EXPORT_SYMBOL_GPL(dwmac1000_dma_axi); -static void dwmac1000_dma_init(void __iomem *ioaddr, - struct stmmac_dma_cfg *dma_cfg, int atds) +void dwmac1000_dma_init(void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, int atds) { u32 value = readl(ioaddr + DMA_BUS_MODE); int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; @@ -109,22 +110,25 @@ static void dwmac1000_dma_init(void __iomem *ioaddr, /* Mask interrupts by writing to CSR7 */ writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); } +EXPORT_SYMBOL_GPL(dwmac1000_dma_init); -static void dwmac1000_dma_init_rx(void __iomem *ioaddr, - struct stmmac_dma_cfg *dma_cfg, - dma_addr_t dma_rx_phy, u32 chan) +void dwmac1000_dma_init_rx(void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_rx_phy, u32 chan) { /* RX descriptor base address list must be written into DMA CSR3 */ writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR); } +EXPORT_SYMBOL_GPL(dwmac1000_dma_init_rx); -static void dwmac1000_dma_init_tx(void __iomem *ioaddr, - struct stmmac_dma_cfg *dma_cfg, - dma_addr_t dma_tx_phy, u32 chan) +void dwmac1000_dma_init_tx(void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_tx_phy, u32 chan) { /* TX descriptor base address list must be written into DMA CSR4 */ writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR); } +EXPORT_SYMBOL_GPL(dwmac1000_dma_init_tx); static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz) { @@ -147,8 +151,8 @@ static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz) return csr6; } -static void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode, - u32 channel, int fifosz, u8 qmode) +void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode, + u32 channel, int fifosz, u8 qmode) { u32 csr6 = readl(ioaddr + DMA_CONTROL); @@ -174,9 +178,10 @@ static void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode, writel(csr6, ioaddr + DMA_CONTROL); } +EXPORT_SYMBOL_GPL(dwmac1000_dma_operation_mode_rx); -static void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode, - u32 channel, int fifosz, u8 qmode) +void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode, + u32 channel, int fifosz, u8 qmode) { u32 csr6 = readl(ioaddr + DMA_CONTROL); @@ -207,8 +212,9 @@ static void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode, writel(csr6, ioaddr + DMA_CONTROL); } +EXPORT_SYMBOL_GPL(dwmac1000_dma_operation_mode_tx); -static void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) +void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) { int i; @@ -217,9 +223,10 @@ static void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) reg_space[DMA_BUS_MODE / 4 + i] = readl(ioaddr + DMA_BUS_MODE + i * 4); } +EXPORT_SYMBOL_GPL(dwmac1000_dump_dma_regs); -static int dwmac1000_get_hw_feature(void __iomem *ioaddr, - struct dma_features *dma_cap) +int dwmac1000_get_hw_feature(void __iomem *ioaddr, + struct dma_features *dma_cap) { u32 hw_cap = readl(ioaddr + DMA_HW_FEATURE); @@ -262,12 +269,14 @@ static int dwmac1000_get_hw_feature(void __iomem *ioaddr, return 0; } +EXPORT_SYMBOL_GPL(dwmac1000_get_hw_feature); -static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt, - u32 queue) +void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt, + u32 queue) { writel(riwt, ioaddr + DMA_RX_WATCHDOG); } +EXPORT_SYMBOL_GPL(dwmac1000_rx_watchdog); const struct stmmac_dma_ops dwmac1000_dma_ops = { .reset = dwmac_dma_reset, diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.h new file mode 100644 index 000000000000..2fb93c53ca4a --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DWMAC1000_DMA_H__ +#define __DWMAC1000_DMA_H__ +#include "dwmac1000.h" + +void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi); +void dwmac1000_dma_init(void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, int atds); +void dwmac1000_dma_init_rx(void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_rx_phy, u32 chan); +void dwmac1000_dma_init_tx(void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_tx_phy, u32 chan); +void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode, + u32 channel, int fifosz, u8 qmode); +void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode, + u32 channel, int fifosz, u8 qmode); +void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space); + +int dwmac1000_get_hw_feature(void __iomem *ioaddr, + struct dma_features *dma_cap); + +void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan); +#endif /* __DWMAC1000_DMA_H__ */ diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c index caa4bfc4c1d6..2d8d1b0e2b98 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c @@ -31,6 +31,7 @@ void dwmac_enable_dma_transmission(void __iomem *ioaddr) { writel(1, ioaddr + DMA_XMT_POLL_DEMAND); } +EXPORT_SYMBOL_GPL(dwmac_enable_dma_transmission); void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) { @@ -43,6 +44,7 @@ void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) writel(value, ioaddr + DMA_INTR_ENA); } +EXPORT_SYMBOL_GPL(dwmac_enable_dma_irq); void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) { @@ -55,6 +57,7 @@ void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) writel(value, ioaddr + DMA_INTR_ENA); } +EXPORT_SYMBOL_GPL(dwmac_disable_dma_irq); void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) { @@ -62,6 +65,7 @@ void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) value |= DMA_CONTROL_ST; writel(value, ioaddr + DMA_CONTROL); } +EXPORT_SYMBOL_GPL(dwmac_dma_start_tx); void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) { @@ -69,6 +73,7 @@ void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) value &= ~DMA_CONTROL_ST; writel(value, ioaddr + DMA_CONTROL); } +EXPORT_SYMBOL_GPL(dwmac_dma_stop_tx); void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) { @@ -76,6 +81,7 @@ void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) value |= DMA_CONTROL_SR; writel(value, ioaddr + DMA_CONTROL); } +EXPORT_SYMBOL_GPL(dwmac_dma_start_rx); void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) { @@ -83,6 +89,7 @@ void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) value &= ~DMA_CONTROL_SR; writel(value, ioaddr + DMA_CONTROL); } +EXPORT_SYMBOL_GPL(dwmac_dma_stop_rx); #ifdef DWMAC_DMA_DEBUG static void show_tx_process_state(unsigned int status) @@ -230,6 +237,7 @@ int dwmac_dma_interrupt(void __iomem *ioaddr, return ret; } +EXPORT_SYMBOL_GPL(dwmac_dma_interrupt); void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr) { diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c index a5d150c5f3d8..651ae4a97283 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c @@ -346,6 +346,63 @@ err_disable_clks: return ret; } +#define MAC_GPIO 0xe0 /* GPIO register */ +#define MAC_GPIO_GPO0 (1 << 8) /* 0-output port */ + +#if IS_ENABLED(CONFIG_STMMAC_PLATFORM) && IS_ENABLED(CONFIG_OF) +/** + * Reset the MII bus via MAC GP out pin + */ +static int stmmac_mdio_reset_gp_out(struct stmmac_priv *priv) { + u32 value, high, low; + u32 delays[3] = { 0, 0, 0 }; + bool active_low = false; + struct device_node *np = priv->device->of_node; + + if (!np) + return -ENODEV; + + if (!of_property_read_bool(np, "snps,reset-gp-out")) { + dev_warn(priv->device, "snps,reset-gp-out is not set\n"); + return -ENODEV; + } + + active_low = of_property_read_bool(np, "snsps,reset-active-low"); + of_property_read_u32_array(np, "snps,reset-delays-us", delays, 3); + + value = readl(priv->ioaddr + MAC_GPIO); + if (active_low) { + high = value | MAC_GPIO_GPO0; + low = value & ~MAC_GPIO_GPO0; + } else { + high = value & ~MAC_GPIO_GPO0; + low = value | MAC_GPIO_GPO0; + } + + writel(high, priv->ioaddr + MAC_GPIO); + if (delays[0]) + msleep(DIV_ROUND_UP(delays[0], 1000)); + + writel(low, priv->ioaddr + MAC_GPIO); + if (delays[1]) + msleep(DIV_ROUND_UP(delays[1], 1000)); + + writel(high, priv->ioaddr + MAC_GPIO); + if (delays[2]) + msleep(DIV_ROUND_UP(delays[2], 1000)); + + /* Clear PHY reset */ + udelay(10); + value = readl(priv->ioaddr + MAC_GPIO); + value |= MAC_GPIO_GPO0; + writel(value, priv->ioaddr + MAC_GPIO); + mdelay(1000); + dev_info(priv->device, "mdio reset completed\n"); + return 0; + return -ENODEV; +} +#endif + /** * stmmac_mdio_reset * @bus: points to the mii_bus structure @@ -361,13 +418,20 @@ int stmmac_mdio_reset(struct mii_bus *bus) #ifdef CONFIG_OF if (priv->device->of_node) { struct gpio_desc *reset_gpio; + bool need_reset_gp_out; u32 delays[3] = { 0, 0, 0 }; reset_gpio = devm_gpiod_get_optional(priv->device, "snps,reset", GPIOD_OUT_LOW); - if (IS_ERR(reset_gpio)) - return PTR_ERR(reset_gpio); + if (IS_ERR(reset_gpio)) { + need_reset_gp_out = of_property_read_bool(priv->device->of_node, + "snps,reset-gp-out"); + if (need_reset_gp_out) + return stmmac_mdio_reset_gp_out(priv); + else + return PTR_ERR(reset_gpio); + } device_property_read_u32_array(priv->device, "snps,reset-delays-us", diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 74d8e1dc125f..0c1eb09f3910 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -840,18 +840,37 @@ static int get_phy_c22_id(struct mii_bus *bus, int addr, u32 *phy_id) int fwnode_get_phy_id(struct fwnode_handle *fwnode, u32 *phy_id) { unsigned int upper, lower; - const char *cp; - int ret; - - ret = fwnode_property_read_string(fwnode, "compatible", &cp); - if (ret) - return ret; - - if (sscanf(cp, "ethernet-phy-id%4x.%4x", &upper, &lower) != 2) - return -EINVAL; + const char **compat; + int ret, count, i; + + /* FIXME: where is fwnode_property_for_each_string? */ + count = fwnode_property_read_string_array(fwnode, "compatible", NULL, 0); + if (count < 0) + return count; + else if (count == 0) + return -ENODATA; + + compat = kcalloc(count, sizeof(*compat), GFP_KERNEL); + if (!compat) + return -ENOMEM; + ret = fwnode_property_read_string_array(fwnode, "compatible", compat, count); + if (ret < 0) + goto out; - *phy_id = ((upper & GENMASK(15, 0)) << 16) | (lower & GENMASK(15, 0)); - return 0; + ret = -EINVAL; + for (i = 0; i < count; i++) { + pr_info("%s: considering '%s'\n", __func__, compat[i]); + if (sscanf(compat[i], "ethernet-phy-id%4x.%4x", &upper, &lower) != 2) + continue; + else { + *phy_id = ((upper & GENMASK(15, 0)) << 16) | (lower & GENMASK(15, 0)); + ret = 0; + break; + } + } +out: + kfree(compat); + return ret; } EXPORT_SYMBOL(fwnode_get_phy_id); diff --git a/drivers/rtc/rtc-efi.c b/drivers/rtc/rtc-efi.c index 138c5e0046c8..af232802278f 100644 --- a/drivers/rtc/rtc-efi.c +++ b/drivers/rtc/rtc-efi.c @@ -17,6 +17,7 @@ #include #include #include +#include #define EFI_ISDST (EFI_TIME_ADJUST_DAYLIGHT|EFI_TIME_IN_DAYLIGHT) @@ -257,6 +258,14 @@ static int __init efi_rtc_probe(struct platform_device *dev) efi_time_t eft; efi_time_cap_t cap; +#ifdef CONFIG_OF + /* efi.get_time is not always safe to call since some UEFI + * implementations do not privde get_time at runtime. */ + if (of_device_is_compatible(of_root, "baikal,baikal-m")) { + dev_err(&dev->dev, "Baikal-M UEFI has no get_time\n"); + return -ENODEV; + } +#endif /* First check if the RTC is usable */ if (efi.get_time(&eft, &cap) != EFI_SUCCESS) return -ENODEV; diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index 53f57c3b9f42..37299176c16a 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -329,14 +329,17 @@ dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, struct ktermios *old) { - unsigned long newrate = tty_termios_baud_rate(termios) * 16; + unsigned long baud = tty_termios_baud_rate(termios); + unsigned long newrate = baud * 16; struct dw8250_data *d = to_dw8250_data(p->private_data); long rate; int ret; clk_disable_unprepare(d->clk); rate = clk_round_rate(d->clk, newrate); - if (rate > 0) { + if (rate > baud * 17 || rate < baud * 15) { + ret = -EINVAL; /* cannot set rate with acceptable accuracy */ + } else if (rate > 0) { /* * Note that any clock-notifer worker will block in * serial8250_update_uartclk() until we are done. diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c index 71fd620c5161..63d6e4b05720 100644 --- a/drivers/usb/dwc3/dwc3-of-simple.c +++ b/drivers/usb/dwc3/dwc3-of-simple.c @@ -177,6 +177,8 @@ static const struct of_device_id of_dwc3_simple_match[] = { { .compatible = "allwinner,sun50i-h6-dwc3" }, { .compatible = "hisilicon,hi3670-dwc3" }, { .compatible = "intel,keembay-dwc3" }, + { .compatible = "baikal,baikal-dwc3" }, + { .compatible = "be,baikal-dwc3" }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, of_dwc3_simple_match); diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c index 80cc1f0f502b..5eef99a14ae1 100644 --- a/kernel/power/suspend.c +++ b/kernel/power/suspend.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "power.h" @@ -238,6 +239,17 @@ EXPORT_SYMBOL_GPL(suspend_valid_only_mem); static bool sleep_state_supported(suspend_state_t state) { +#ifdef CONFIG_OF + if (of_device_is_compatible(of_root, "baikal,baikal-m")) { + /* XXX: there are no wakeup sources except RTC and Ethernet + * on BE-M1000 based boards. In other words, no way to wakeup + * system via the keyboard or power button. + * Thus even s2idle is unusable on BE-M1000 systems. + */ + pr_info("%s: no useful wakeup sources on Baikal-M", __func__); + return false; + } +#endif return state == PM_SUSPEND_TO_IDLE || valid_state(state); } diff --git a/sound/soc/dwc/dwc-i2s.c b/sound/soc/dwc/dwc-i2s.c index 5cb58929090d..7f714f05fff0 100644 --- a/sound/soc/dwc/dwc-i2s.c +++ b/sound/soc/dwc/dwc-i2s.c @@ -100,6 +100,7 @@ static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream, static irqreturn_t i2s_irq_handler(int irq, void *dev_id) { + unsigned int rxor_count; struct dw_i2s_dev *dev = dev_id; bool irq_valid = false; u32 isr[4]; @@ -136,9 +137,13 @@ static irqreturn_t i2s_irq_handler(int irq, void *dev_id) irq_valid = true; } - /* Error Handling: TX */ + /* Error Handling: RX */ if (isr[i] & ISR_RXFO) { - dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i); + rxor_count = READ_ONCE(dev->rx_overrun_count); + if (!(rxor_count & 0x3ff)) + dev_dbg(dev->dev, "RX overrun (ch_id=%d)\n", i); + rxor_count++; + WRITE_ONCE(dev->rx_overrun_count, rxor_count); irq_valid = true; } } @@ -622,7 +627,8 @@ static int dw_i2s_probe(struct platform_device *pdev) const struct i2s_platform_data *pdata = pdev->dev.platform_data; struct dw_i2s_dev *dev; struct resource *res; - int ret, irq; + int ret, irq, irq_count; + unsigned idx; struct snd_soc_dai_driver *dw_i2s_dai; const char *clk_id; @@ -642,13 +648,23 @@ static int dw_i2s_probe(struct platform_device *pdev) dev->dev = &pdev->dev; - irq = platform_get_irq_optional(pdev, 0); - if (irq >= 0) { - ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0, - pdev->name, dev); - if (ret < 0) { - dev_err(&pdev->dev, "failed to request irq\n"); - return ret; + irq_count = platform_irq_count(pdev); + if (irq_count < 0) /* - EPROBE_DEFER */ + return irq_count; + else if (!irq_count) { + dev_err(&pdev->dev, "no IRQs found for device\n"); + return -ENODEV; + } + + for (idx = 0; idx < (unsigned)irq_count; idx++) { + irq = platform_get_irq_optional(pdev, idx); + if (irq >= 0) { + ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0, + pdev->name, dev); + if (ret < 0) { + dev_err(&pdev->dev, "failed to request irq\n"); + return ret; + } } } diff --git a/sound/soc/dwc/local.h b/sound/soc/dwc/local.h index 1c361eb6127e..1d6b6fd870ca 100644 --- a/sound/soc/dwc/local.h +++ b/sound/soc/dwc/local.h @@ -117,6 +117,7 @@ struct dw_i2s_dev { bool *period_elapsed); unsigned int tx_ptr; unsigned int rx_ptr; + unsigned int rx_overrun_count; }; #if IS_ENABLED(CONFIG_SND_DESIGNWARE_PCM)