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839b6a86b6
Information about config values was taken from: From 804820df7bcb3d53a33ecd074b1eac277e938f24 Mon Sep 17 00:00:00 2001 From: Alexey Sheplyakov <asheplyakov@altlinux.org> Date: Thu, 4 Feb 2021 19:35:14 +0400 Subject: [PATCH] config-aarch64: adjusted for Baikal-M (MBM1.0 board) * DW_APB_TIMER=y, DW_APB_TIMER_OF=y: SoC clocks * SERIAL_8250_DW=y: serial console * I2C_DESIGNWARE_CORE=y, I2C_DESIGNWARE_PLATFORM=y: BMC (board management controller) and RTC (Real Time Clock) are connected via I2C. * GPIO_DWAPB=y: device (PCIe, PHY, etc) reset/configuration * RTC_DRV_PCF2127=y: RTC compiled in so the kernel automatically sets the system time from the hardware clock * TP_BMC=y: amongst other things handles the power button * DRM_BAIKAL_VDU=m, DRM_BAIKAL_HDMI=m: video unit and HDMI transmitter * CMA_SIZE_MBYTES=256: video display unit and GPU use system RAM, hence CMA should reserve enough (contiguous) memory. Note: CMA reserves memory during very early init, hence the size has to be hard-coded into CONFIG * MALI_MIDGARD=m: GPU driver, kernel side of proprietary mali blob. Note: kernel mode code is GPLv2, so it's fine to distribute it. * SENSORS_BT1_PVT=m: hardware temperature/voltage sensors * PCI_BAIKAL=m: PCIe root complex. Compiled as a module since takes ages (60 seconds or so) to probe the hardware. If compiled in substantially increases the boot time, and machine is completely unresponsive during probing PCIe. When built as a module probing executes concurrently with other boot activities (unless booting from a PCIe device) * STMMAC_ETH=m, STMMAC_PLATFORM=m, DWMAC_BAIKAL=m: Ethernet driver
253 lines
9.1 KiB
Diff
253 lines
9.1 KiB
Diff
From ddbb6264ac1a4216a1b965b4ddc0d7cb31fe3d99 Mon Sep 17 00:00:00 2001
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From: Alexey Sheplyakov <asheplyakov@altlinux.org>
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Date: Wed, 3 Jun 2020 20:22:29 +0400
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Subject: [PATCH 605/625] ethernet: stmmac: made dwmac1000_* DMA functions
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available for reuse
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Some variants of dwmac hardware (in particular the one in the BE-M1000
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SoC) need custom DMA reset, and can reuse other dwmac1000 DMA functions.
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(cherry picked from commit f8e6ec3642eb28e7b74c0a7875310d7354895c8a)
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---
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.../ethernet/stmicro/stmmac/dwmac1000_core.c | 1 +
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.../ethernet/stmicro/stmmac/dwmac1000_dma.c | 45 +++++++++++--------
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.../ethernet/stmicro/stmmac/dwmac1000_dma.h | 26 +++++++++++
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.../net/ethernet/stmicro/stmmac/dwmac_lib.c | 8 ++++
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4 files changed, 62 insertions(+), 18 deletions(-)
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create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.h
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diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
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index fc8759f146c7..bf4f79ef3b22 100644
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
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@@ -563,3 +563,4 @@ int dwmac1000_setup(struct stmmac_priv *priv)
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return 0;
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}
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+EXPORT_SYMBOL_GPL(dwmac1000_setup);
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diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
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index 2bac49b49f73..d27d5292550a 100644
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
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@@ -16,7 +16,7 @@
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#include "dwmac1000.h"
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#include "dwmac_dma.h"
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-static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
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+void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
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{
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u32 value = readl(ioaddr + DMA_AXI_BUS_MODE);
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int i;
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@@ -69,9 +69,10 @@ static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
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writel(value, ioaddr + DMA_AXI_BUS_MODE);
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}
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+EXPORT_SYMBOL_GPL(dwmac1000_dma_axi);
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-static void dwmac1000_dma_init(void __iomem *ioaddr,
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- struct stmmac_dma_cfg *dma_cfg, int atds)
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+void dwmac1000_dma_init(void __iomem *ioaddr,
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+ struct stmmac_dma_cfg *dma_cfg, int atds)
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{
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u32 value = readl(ioaddr + DMA_BUS_MODE);
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int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
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@@ -109,22 +110,25 @@ static void dwmac1000_dma_init(void __iomem *ioaddr,
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/* Mask interrupts by writing to CSR7 */
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writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
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}
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+EXPORT_SYMBOL_GPL(dwmac1000_dma_init);
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-static void dwmac1000_dma_init_rx(void __iomem *ioaddr,
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- struct stmmac_dma_cfg *dma_cfg,
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- dma_addr_t dma_rx_phy, u32 chan)
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+void dwmac1000_dma_init_rx(void __iomem *ioaddr,
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+ struct stmmac_dma_cfg *dma_cfg,
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+ dma_addr_t dma_rx_phy, u32 chan)
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{
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/* RX descriptor base address list must be written into DMA CSR3 */
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writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);
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}
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+EXPORT_SYMBOL_GPL(dwmac1000_dma_init_rx);
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-static void dwmac1000_dma_init_tx(void __iomem *ioaddr,
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- struct stmmac_dma_cfg *dma_cfg,
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- dma_addr_t dma_tx_phy, u32 chan)
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+void dwmac1000_dma_init_tx(void __iomem *ioaddr,
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+ struct stmmac_dma_cfg *dma_cfg,
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+ dma_addr_t dma_tx_phy, u32 chan)
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{
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/* TX descriptor base address list must be written into DMA CSR4 */
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writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);
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}
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+EXPORT_SYMBOL_GPL(dwmac1000_dma_init_tx);
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static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
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{
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@@ -147,8 +151,8 @@ static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
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return csr6;
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}
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-static void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode,
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- u32 channel, int fifosz, u8 qmode)
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+void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode,
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+ u32 channel, int fifosz, u8 qmode)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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@@ -174,9 +178,10 @@ static void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode,
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writel(csr6, ioaddr + DMA_CONTROL);
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}
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+EXPORT_SYMBOL_GPL(dwmac1000_dma_operation_mode_rx);
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-static void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode,
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- u32 channel, int fifosz, u8 qmode)
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+void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode,
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+ u32 channel, int fifosz, u8 qmode)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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@@ -207,8 +212,9 @@ static void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode,
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writel(csr6, ioaddr + DMA_CONTROL);
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}
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+EXPORT_SYMBOL_GPL(dwmac1000_dma_operation_mode_tx);
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-static void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
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+void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
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{
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int i;
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@@ -217,9 +223,10 @@ static void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
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reg_space[DMA_BUS_MODE / 4 + i] =
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readl(ioaddr + DMA_BUS_MODE + i * 4);
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}
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+EXPORT_SYMBOL_GPL(dwmac1000_dump_dma_regs);
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-static void dwmac1000_get_hw_feature(void __iomem *ioaddr,
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- struct dma_features *dma_cap)
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+void dwmac1000_get_hw_feature(void __iomem *ioaddr,
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+ struct dma_features *dma_cap)
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{
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u32 hw_cap = readl(ioaddr + DMA_HW_FEATURE);
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@@ -253,12 +260,14 @@ static void dwmac1000_get_hw_feature(void __iomem *ioaddr,
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/* Alternate (enhanced) DESC mode */
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dma_cap->enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
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}
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+EXPORT_SYMBOL_GPL(dwmac1000_get_hw_feature);
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-static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt,
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- u32 number_chan)
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+void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt,
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+ u32 number_chan)
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{
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writel(riwt, ioaddr + DMA_RX_WATCHDOG);
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}
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+EXPORT_SYMBOL_GPL(dwmac1000_rx_watchdog);
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const struct stmmac_dma_ops dwmac1000_dma_ops = {
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.reset = dwmac_dma_reset,
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diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.h
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new file mode 100644
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index 000000000000..b1e39a109f31
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--- /dev/null
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.h
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@@ -0,0 +1,26 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+
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+#ifndef __DWMAC1000_DMA_H__
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+#define __DWMAC1000_DMA_H__
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+#include "dwmac1000.h"
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+
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+void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi);
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+void dwmac1000_dma_init(void __iomem *ioaddr,
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+ struct stmmac_dma_cfg *dma_cfg, int atds);
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+void dwmac1000_dma_init_rx(void __iomem *ioaddr,
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+ struct stmmac_dma_cfg *dma_cfg,
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+ dma_addr_t dma_rx_phy, u32 chan);
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+void dwmac1000_dma_init_tx(void __iomem *ioaddr,
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+ struct stmmac_dma_cfg *dma_cfg,
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+ dma_addr_t dma_tx_phy, u32 chan);
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+void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode,
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+ u32 channel, int fifosz, u8 qmode);
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+void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode,
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+ u32 channel, int fifosz, u8 qmode);
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+void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space);
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+
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+void dwmac1000_get_hw_feature(void __iomem *ioaddr,
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+ struct dma_features *dma_cap);
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+
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+void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan);
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+#endif /* __DWMAC1000_DMA_H__ */
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diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
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index 57a53a600aa5..e391285a2158 100644
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
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@@ -31,6 +31,7 @@ void dwmac_enable_dma_transmission(void __iomem *ioaddr)
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{
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writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
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}
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+EXPORT_SYMBOL_GPL(dwmac_enable_dma_transmission);
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void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
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{
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@@ -43,6 +44,7 @@ void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
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writel(value, ioaddr + DMA_INTR_ENA);
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}
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+EXPORT_SYMBOL_GPL(dwmac_enable_dma_irq);
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void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
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{
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@@ -55,6 +57,7 @@ void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
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writel(value, ioaddr + DMA_INTR_ENA);
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}
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+EXPORT_SYMBOL_GPL(dwmac_disable_dma_irq);
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void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
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{
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@@ -62,6 +65,7 @@ void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
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value |= DMA_CONTROL_ST;
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writel(value, ioaddr + DMA_CONTROL);
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}
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+EXPORT_SYMBOL_GPL(dwmac_dma_start_tx);
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void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
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{
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@@ -69,6 +73,7 @@ void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
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value &= ~DMA_CONTROL_ST;
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writel(value, ioaddr + DMA_CONTROL);
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}
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+EXPORT_SYMBOL_GPL(dwmac_dma_stop_tx);
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void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
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{
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@@ -76,6 +81,7 @@ void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
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value |= DMA_CONTROL_SR;
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writel(value, ioaddr + DMA_CONTROL);
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}
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+EXPORT_SYMBOL_GPL(dwmac_dma_start_rx);
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void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
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{
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@@ -83,6 +89,7 @@ void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
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value &= ~DMA_CONTROL_SR;
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writel(value, ioaddr + DMA_CONTROL);
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}
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+EXPORT_SYMBOL_GPL(dwmac_dma_stop_rx);
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#ifdef DWMAC_DMA_DEBUG
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static void show_tx_process_state(unsigned int status)
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@@ -224,6 +231,7 @@ int dwmac_dma_interrupt(void __iomem *ioaddr,
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return ret;
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}
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+EXPORT_SYMBOL_GPL(dwmac_dma_interrupt);
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void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr)
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{
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--
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2.31.1
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