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https://abf.rosa.ru/djam/kernel-5.15.git
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54 lines
2.2 KiB
Diff
54 lines
2.2 KiB
Diff
From ac048f806b24c33a331673c6b00f7482adc5b7a0 Mon Sep 17 00:00:00 2001
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From: Alexey Sheplyakov <asheplyakov@basealt.ru>
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Date: Tue, 11 Jan 2022 15:49:19 +0400
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Subject: [PATCH 619/634] [rejected] serial: 8250_dw: verify clock rate in
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dw8250_set_termios
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Refuse to change the clock rate if clk_round_rate() returns
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a rate which is way too off (i.e. by more than 1/16 from the one
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necessary for a given baud rate). In particular this happens if
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the requested rate is below the minimum supported by the clock.
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Fixes the UART console on Baikal-M SoC. Without this patch the
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console gets garbled immediately after loading the driver.
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dw8250_set_termios tries to configure the baud rate (115200),
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and calls clk_round_rate to figure out the supported rate closest
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to 1843200 Hz (which is 115200 * 16). However the (SoC-specific)
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clock driver returns 4705882 Hz. This frequency is way too off,
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hence after setting it the console gets garbled.
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Signed-off-by: Alexey Sheplyakov <asheplyakov@basealt.ru>
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Signed-off-by: Vadim V. Vlasov <vadim.vlasov@elpitech.ru>
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Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>
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---
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drivers/tty/serial/8250/8250_dw.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
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index 49559731b..b6d21ac44 100644
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--- a/drivers/tty/serial/8250/8250_dw.c
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+++ b/drivers/tty/serial/8250/8250_dw.c
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@@ -329,14 +329,15 @@ dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
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static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
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struct ktermios *old)
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{
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- unsigned long newrate = tty_termios_baud_rate(termios) * 16;
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+ unsigned long baud = tty_termios_baud_rate(termios);
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+ unsigned long newrate = baud * 16;
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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long rate;
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int ret;
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clk_disable_unprepare(d->clk);
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rate = clk_round_rate(d->clk, newrate);
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- if (rate > 0) {
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+ if (rate > 0 && rate >= baud * 15 && rate <= baud * 17) {
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/*
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* Premilinary set the uartclk to the new clock rate so the
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* clock update event handler caused by the clk_set_rate()
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--
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2.33.2
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