From ddbb6264ac1a4216a1b965b4ddc0d7cb31fe3d99 Mon Sep 17 00:00:00 2001 From: Alexey Sheplyakov Date: Wed, 3 Jun 2020 20:22:29 +0400 Subject: [PATCH 605/625] ethernet: stmmac: made dwmac1000_* DMA functions available for reuse Some variants of dwmac hardware (in particular the one in the BE-M1000 SoC) need custom DMA reset, and can reuse other dwmac1000 DMA functions. (cherry picked from commit f8e6ec3642eb28e7b74c0a7875310d7354895c8a) --- .../ethernet/stmicro/stmmac/dwmac1000_core.c | 1 + .../ethernet/stmicro/stmmac/dwmac1000_dma.c | 45 +++++++++++-------- .../ethernet/stmicro/stmmac/dwmac1000_dma.h | 26 +++++++++++ .../net/ethernet/stmicro/stmmac/dwmac_lib.c | 8 ++++ 4 files changed, 62 insertions(+), 18 deletions(-) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.h diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c index fc8759f146c7..bf4f79ef3b22 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c @@ -563,3 +563,4 @@ int dwmac1000_setup(struct stmmac_priv *priv) return 0; } +EXPORT_SYMBOL_GPL(dwmac1000_setup); diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c index 2bac49b49f73..d27d5292550a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c @@ -16,7 +16,7 @@ #include "dwmac1000.h" #include "dwmac_dma.h" -static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) +void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) { u32 value = readl(ioaddr + DMA_AXI_BUS_MODE); int i; @@ -69,9 +69,10 @@ static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) writel(value, ioaddr + DMA_AXI_BUS_MODE); } +EXPORT_SYMBOL_GPL(dwmac1000_dma_axi); -static void dwmac1000_dma_init(void __iomem *ioaddr, - struct stmmac_dma_cfg *dma_cfg, int atds) +void dwmac1000_dma_init(void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, int atds) { u32 value = readl(ioaddr + DMA_BUS_MODE); int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; @@ -109,22 +110,25 @@ static void dwmac1000_dma_init(void __iomem *ioaddr, /* Mask interrupts by writing to CSR7 */ writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); } +EXPORT_SYMBOL_GPL(dwmac1000_dma_init); -static void dwmac1000_dma_init_rx(void __iomem *ioaddr, - struct stmmac_dma_cfg *dma_cfg, - dma_addr_t dma_rx_phy, u32 chan) +void dwmac1000_dma_init_rx(void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_rx_phy, u32 chan) { /* RX descriptor base address list must be written into DMA CSR3 */ writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR); } +EXPORT_SYMBOL_GPL(dwmac1000_dma_init_rx); -static void dwmac1000_dma_init_tx(void __iomem *ioaddr, - struct stmmac_dma_cfg *dma_cfg, - dma_addr_t dma_tx_phy, u32 chan) +void dwmac1000_dma_init_tx(void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_tx_phy, u32 chan) { /* TX descriptor base address list must be written into DMA CSR4 */ writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR); } +EXPORT_SYMBOL_GPL(dwmac1000_dma_init_tx); static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz) { @@ -147,8 +151,8 @@ static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz) return csr6; } -static void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode, - u32 channel, int fifosz, u8 qmode) +void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode, + u32 channel, int fifosz, u8 qmode) { u32 csr6 = readl(ioaddr + DMA_CONTROL); @@ -174,9 +178,10 @@ static void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode, writel(csr6, ioaddr + DMA_CONTROL); } +EXPORT_SYMBOL_GPL(dwmac1000_dma_operation_mode_rx); -static void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode, - u32 channel, int fifosz, u8 qmode) +void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode, + u32 channel, int fifosz, u8 qmode) { u32 csr6 = readl(ioaddr + DMA_CONTROL); @@ -207,8 +212,9 @@ static void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode, writel(csr6, ioaddr + DMA_CONTROL); } +EXPORT_SYMBOL_GPL(dwmac1000_dma_operation_mode_tx); -static void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) +void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) { int i; @@ -217,9 +223,10 @@ static void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) reg_space[DMA_BUS_MODE / 4 + i] = readl(ioaddr + DMA_BUS_MODE + i * 4); } +EXPORT_SYMBOL_GPL(dwmac1000_dump_dma_regs); -static void dwmac1000_get_hw_feature(void __iomem *ioaddr, - struct dma_features *dma_cap) +void dwmac1000_get_hw_feature(void __iomem *ioaddr, + struct dma_features *dma_cap) { u32 hw_cap = readl(ioaddr + DMA_HW_FEATURE); @@ -253,12 +260,14 @@ static void dwmac1000_get_hw_feature(void __iomem *ioaddr, /* Alternate (enhanced) DESC mode */ dma_cap->enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; } +EXPORT_SYMBOL_GPL(dwmac1000_get_hw_feature); -static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt, - u32 number_chan) +void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt, + u32 number_chan) { writel(riwt, ioaddr + DMA_RX_WATCHDOG); } +EXPORT_SYMBOL_GPL(dwmac1000_rx_watchdog); const struct stmmac_dma_ops dwmac1000_dma_ops = { .reset = dwmac_dma_reset, diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.h new file mode 100644 index 000000000000..b1e39a109f31 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DWMAC1000_DMA_H__ +#define __DWMAC1000_DMA_H__ +#include "dwmac1000.h" + +void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi); +void dwmac1000_dma_init(void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, int atds); +void dwmac1000_dma_init_rx(void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_rx_phy, u32 chan); +void dwmac1000_dma_init_tx(void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_tx_phy, u32 chan); +void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode, + u32 channel, int fifosz, u8 qmode); +void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode, + u32 channel, int fifosz, u8 qmode); +void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space); + +void dwmac1000_get_hw_feature(void __iomem *ioaddr, + struct dma_features *dma_cap); + +void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan); +#endif /* __DWMAC1000_DMA_H__ */ diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c index 57a53a600aa5..e391285a2158 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c @@ -31,6 +31,7 @@ void dwmac_enable_dma_transmission(void __iomem *ioaddr) { writel(1, ioaddr + DMA_XMT_POLL_DEMAND); } +EXPORT_SYMBOL_GPL(dwmac_enable_dma_transmission); void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) { @@ -43,6 +44,7 @@ void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) writel(value, ioaddr + DMA_INTR_ENA); } +EXPORT_SYMBOL_GPL(dwmac_enable_dma_irq); void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) { @@ -55,6 +57,7 @@ void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) writel(value, ioaddr + DMA_INTR_ENA); } +EXPORT_SYMBOL_GPL(dwmac_disable_dma_irq); void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) { @@ -62,6 +65,7 @@ void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) value |= DMA_CONTROL_ST; writel(value, ioaddr + DMA_CONTROL); } +EXPORT_SYMBOL_GPL(dwmac_dma_start_tx); void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) { @@ -69,6 +73,7 @@ void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) value &= ~DMA_CONTROL_ST; writel(value, ioaddr + DMA_CONTROL); } +EXPORT_SYMBOL_GPL(dwmac_dma_stop_tx); void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) { @@ -76,6 +81,7 @@ void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) value |= DMA_CONTROL_SR; writel(value, ioaddr + DMA_CONTROL); } +EXPORT_SYMBOL_GPL(dwmac_dma_start_rx); void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) { @@ -83,6 +89,7 @@ void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) value &= ~DMA_CONTROL_SR; writel(value, ioaddr + DMA_CONTROL); } +EXPORT_SYMBOL_GPL(dwmac_dma_stop_rx); #ifdef DWMAC_DMA_DEBUG static void show_tx_process_state(unsigned int status) @@ -224,6 +231,7 @@ int dwmac_dma_interrupt(void __iomem *ioaddr, return ret; } +EXPORT_SYMBOL_GPL(dwmac_dma_interrupt); void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr) { -- 2.31.1