diff --git a/0601-Baikal-M-Kconfig-defconfig.patch b/0601-Baikal-M-Kconfig-defconfig.patch new file mode 100644 index 0000000..e10113d --- /dev/null +++ b/0601-Baikal-M-Kconfig-defconfig.patch @@ -0,0 +1,4476 @@ +From 02e6274c8efcdf126d9a71a7e30a3e05e60c5c52 Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Fri, 20 Mar 2020 13:54:11 +0400 +Subject: [PATCH 601/625] Baikal-M: Kconfig, defconfig + +--- + arch/arm64/Kconfig.platforms | 13 + + arch/arm64/configs/baikal_minimal_defconfig | 4418 +++++++++++++++++++ + drivers/i2c/busses/Kconfig | 2 +- + 3 files changed, 4432 insertions(+), 1 deletion(-) + create mode 100644 arch/arm64/configs/baikal_minimal_defconfig + +diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms +index 5c4ac1c9f4e0..78423bfc808e 100644 +--- a/arch/arm64/Kconfig.platforms ++++ b/arch/arm64/Kconfig.platforms +@@ -29,6 +29,19 @@ config ARCH_ALPINE + This enables support for the Annapurna Labs Alpine + Soc family. + ++config ARCH_BAIKAL ++ bool "Baikal Electronics Baikal-M SOC Family" ++ select GPIOLIB ++ select PINCTRL ++ select OF_GPIO ++ select GPIO_SYSFS ++ select GPIO_DWAPB ++ select GPIO_GENERIC ++ select DW_APB_TIMER ++ select DW_APB_TIMER_OF ++ help ++ This enables support for Baikal Electronics Baikal-M SOC Family ++ + config ARCH_BCM2835 + bool "Broadcom BCM2835 family" + select TIMER_OF +diff --git a/arch/arm64/configs/baikal_minimal_defconfig b/arch/arm64/configs/baikal_minimal_defconfig +new file mode 100644 +index 000000000000..95443474fd9b +--- /dev/null ++++ b/arch/arm64/configs/baikal_minimal_defconfig +@@ -0,0 +1,4418 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm64 5.6.0 Kernel Configuration ++# ++ ++# ++# Compiler: aarch64-linux-gnu-gcc (Ubuntu/Linaro 7.5.0-3ubuntu1~18.04) 7.5.0 ++# ++CONFIG_CC_IS_GCC=y ++CONFIG_GCC_VERSION=70500 ++CONFIG_CLANG_VERSION=0 ++CONFIG_CC_CAN_LINK=y ++CONFIG_CC_HAS_ASM_GOTO=y ++CONFIG_CC_HAS_ASM_INLINE=y ++CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_TABLE_SORT=y ++CONFIG_THREAD_INFO_IN_TASK=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_BUILD_SALT="" ++CONFIG_DEFAULT_HOSTNAME="" ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++CONFIG_CROSS_MEMORY_ATTACH=y ++# CONFIG_USELIB is not set ++CONFIG_AUDIT=y ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++CONFIG_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y ++CONFIG_GENERIC_IRQ_MIGRATION=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_CHIP=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_GENERIC_MSI_IRQ=y ++CONFIG_GENERIC_MSI_IRQ_DOMAIN=y ++CONFIG_IRQ_MSI_IOMMU=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++# CONFIG_GENERIC_IRQ_DEBUGFS is not set ++# end of IRQ subsystem ++ ++CONFIG_GENERIC_IRQ_MULTI_HANDLER=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++# CONFIG_NO_HZ is not set ++CONFIG_HIGH_RES_TIMERS=y ++# end of Timers subsystem ++ ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_PREEMPTION=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y ++CONFIG_TASKSTATS=y ++CONFIG_TASK_DELAY_ACCT=y ++CONFIG_TASK_XACCT=y ++CONFIG_TASK_IO_ACCOUNTING=y ++CONFIG_PSI=y ++# CONFIG_PSI_DEFAULT_DISABLED is not set ++# end of CPU/Task time and stats accounting ++ ++CONFIG_CPU_ISOLATION=y ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++CONFIG_TREE_SRCU=y ++CONFIG_TASKS_RCU=y ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_NEED_SEGCBLIST=y ++# end of RCU Subsystem ++ ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++# CONFIG_IKHEADERS is not set ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++ ++# ++# Scheduler features ++# ++# CONFIG_UCLAMP_TASK is not set ++# end of Scheduler features ++ ++CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y ++CONFIG_CC_HAS_INT128=y ++CONFIG_ARCH_SUPPORTS_INT128=y ++CONFIG_CGROUPS=y ++CONFIG_PAGE_COUNTER=y ++CONFIG_MEMCG=y ++CONFIG_MEMCG_SWAP=y ++CONFIG_MEMCG_SWAP_ENABLED=y ++CONFIG_MEMCG_KMEM=y ++CONFIG_BLK_CGROUP=y ++CONFIG_CGROUP_WRITEBACK=y ++CONFIG_CGROUP_SCHED=y ++CONFIG_FAIR_GROUP_SCHED=y ++CONFIG_CFS_BANDWIDTH=y ++# CONFIG_RT_GROUP_SCHED is not set ++CONFIG_CGROUP_PIDS=y ++# CONFIG_CGROUP_RDMA is not set ++CONFIG_CGROUP_FREEZER=y ++# CONFIG_CGROUP_HUGETLB is not set ++CONFIG_CPUSETS=y ++CONFIG_PROC_PID_CPUSET=y ++CONFIG_CGROUP_DEVICE=y ++CONFIG_CGROUP_CPUACCT=y ++CONFIG_CGROUP_PERF=y ++# CONFIG_CGROUP_BPF is not set ++# CONFIG_CGROUP_DEBUG is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++CONFIG_USER_NS=y ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_SCHED_AUTOGROUP=y ++# CONFIG_SYSFS_DEPRECATED is not set ++CONFIG_RELAY=y ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++CONFIG_RD_LZMA=y ++CONFIG_RD_XZ=y ++CONFIG_RD_LZO=y ++CONFIG_RD_LZ4=y ++CONFIG_BOOT_CONFIG=y ++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_HAVE_UID16=y ++CONFIG_SYSCTL_EXCEPTION_TRACE=y ++CONFIG_BPF=y ++# CONFIG_EXPERT is not set ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++CONFIG_SYSFS_SYSCALL=y ++CONFIG_FHANDLE=y ++CONFIG_POSIX_TIMERS=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_FUTEX_PI=y ++CONFIG_HAVE_FUTEX_CMPXCHG=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_IO_URING=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_MEMBARRIER=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_BPF_SYSCALL=y ++CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y ++# CONFIG_BPF_JIT_ALWAYS_ON is not set ++CONFIG_BPF_JIT_DEFAULT_ON=y ++CONFIG_USERFAULTFD=y ++CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y ++CONFIG_RSEQ=y ++# CONFIG_EMBEDDED is not set ++CONFIG_HAVE_PERF_EVENTS=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# end of Kernel Performance Events And Counters ++ ++CONFIG_VM_EVENT_COUNTERS=y ++# CONFIG_COMPAT_BRK is not set ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++CONFIG_SLAB_MERGE_DEFAULT=y ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set ++CONFIG_PROFILING=y ++CONFIG_TRACEPOINTS=y ++# end of General setup ++ ++CONFIG_ARM64=y ++CONFIG_64BIT=y ++CONFIG_MMU=y ++CONFIG_ARM64_PAGE_SHIFT=12 ++CONFIG_ARM64_CONT_SHIFT=4 ++CONFIG_ARCH_MMAP_RND_BITS_MIN=18 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=33 ++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 ++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CSUM=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_ZONE_DMA32=y ++CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y ++CONFIG_SMP=y ++CONFIG_KERNEL_MODE_NEON=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_PGTABLE_LEVELS=4 ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_ARCH_PROC_KCORE_TEXT=y ++ ++# ++# Platform selection ++# ++# CONFIG_ARCH_ACTIONS is not set ++# CONFIG_ARCH_AGILEX is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_ALPINE is not set ++CONFIG_ARCH_BAIKAL=y ++# CONFIG_ARCH_BCM2835 is not set ++# CONFIG_ARCH_BCM_IPROC is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_BITMAIN is not set ++# CONFIG_ARCH_BRCMSTB is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_K3 is not set ++# CONFIG_ARCH_LAYERSCAPE is not set ++# CONFIG_ARCH_LG1K is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_MEDIATEK is not set ++# CONFIG_ARCH_MESON is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALTEK is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_S32 is not set ++# CONFIG_ARCH_SEATTLE is not set ++# CONFIG_ARCH_STRATIX10 is not set ++# CONFIG_ARCH_SYNQUACER is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_SPRD is not set ++# CONFIG_ARCH_THUNDER is not set ++# CONFIG_ARCH_THUNDER2 is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_XGENE is not set ++# CONFIG_ARCH_ZX is not set ++CONFIG_ARCH_NR_GPIO=32 ++# CONFIG_ARCH_ZYNQMP is not set ++# end of Platform selection ++ ++# ++# Kernel Features ++# ++ ++# ++# ARM errata workarounds via the alternatives framework ++# ++CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y ++CONFIG_ARM64_ERRATUM_826319=y ++CONFIG_ARM64_ERRATUM_827319=y ++CONFIG_ARM64_ERRATUM_824069=y ++CONFIG_ARM64_ERRATUM_819472=y ++CONFIG_ARM64_ERRATUM_832075=y ++CONFIG_ARM64_ERRATUM_845719=y ++CONFIG_ARM64_ERRATUM_843419=y ++CONFIG_ARM64_ERRATUM_1024718=y ++CONFIG_ARM64_ERRATUM_1418040=y ++CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT_VHE=y ++CONFIG_ARM64_ERRATUM_1165522=y ++CONFIG_ARM64_ERRATUM_1530923=y ++CONFIG_ARM64_ERRATUM_1286807=y ++CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT_NVHE=y ++CONFIG_ARM64_ERRATUM_1319367=y ++CONFIG_ARM64_ERRATUM_1463225=y ++CONFIG_ARM64_ERRATUM_1542419=y ++CONFIG_CAVIUM_ERRATUM_22375=y ++CONFIG_CAVIUM_ERRATUM_23154=y ++CONFIG_CAVIUM_ERRATUM_27456=y ++CONFIG_CAVIUM_ERRATUM_30115=y ++CONFIG_CAVIUM_TX2_ERRATUM_219=y ++CONFIG_QCOM_FALKOR_ERRATUM_1003=y ++CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y ++CONFIG_QCOM_FALKOR_ERRATUM_1009=y ++CONFIG_QCOM_QDF2400_ERRATUM_0065=y ++CONFIG_SOCIONEXT_SYNQUACER_PREITS=y ++CONFIG_HISILICON_ERRATUM_161600802=y ++CONFIG_QCOM_FALKOR_ERRATUM_E1041=y ++CONFIG_FUJITSU_ERRATUM_010001=y ++# end of ARM errata workarounds via the alternatives framework ++ ++CONFIG_ARM64_4K_PAGES=y ++# CONFIG_ARM64_16K_PAGES is not set ++# CONFIG_ARM64_64K_PAGES is not set ++# CONFIG_ARM64_VA_BITS_39 is not set ++CONFIG_ARM64_VA_BITS_48=y ++CONFIG_ARM64_VA_BITS=48 ++CONFIG_ARM64_PA_BITS_48=y ++CONFIG_ARM64_PA_BITS=48 ++# CONFIG_CPU_BIG_ENDIAN is not set ++CONFIG_CPU_LITTLE_ENDIAN=y ++CONFIG_SCHED_MC=y ++# CONFIG_SCHED_SMT is not set ++CONFIG_NR_CPUS=8 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_NUMA is not set ++CONFIG_HOLES_IN_ZONE=y ++# CONFIG_HZ_100 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++CONFIG_HZ_1000=y ++CONFIG_HZ=1000 ++CONFIG_SCHED_HRTICK=y ++CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y ++CONFIG_ARCH_SPARSEMEM_ENABLE=y ++CONFIG_ARCH_SPARSEMEM_DEFAULT=y ++CONFIG_ARCH_SELECT_MEMORY_MODEL=y ++CONFIG_ARCH_FLATMEM_ENABLE=y ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_SYS_SUPPORTS_HUGETLBFS=y ++CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y ++CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y ++CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y ++CONFIG_SECCOMP=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++CONFIG_KEXEC=y ++CONFIG_KEXEC_FILE=y ++# CONFIG_KEXEC_SIG is not set ++# CONFIG_CRASH_DUMP is not set ++# CONFIG_XEN is not set ++CONFIG_FORCE_MAX_ZONEORDER=11 ++CONFIG_UNMAP_KERNEL_AT_EL0=y ++CONFIG_HARDEN_BRANCH_PREDICTOR=y ++CONFIG_HARDEN_EL2_VECTORS=y ++CONFIG_ARM64_SSBD=y ++CONFIG_RODATA_FULL_DEFAULT_ENABLED=y ++# CONFIG_ARM64_SW_TTBR0_PAN is not set ++CONFIG_ARM64_TAGGED_ADDR_ABI=y ++CONFIG_COMPAT=y ++CONFIG_KUSER_HELPERS=y ++CONFIG_ARMV8_DEPRECATED=y ++CONFIG_SWP_EMULATION=y ++CONFIG_CP15_BARRIER_EMULATION=y ++CONFIG_SETEND_EMULATION=y ++ ++# ++# ARMv8.1 architectural features ++# ++CONFIG_ARM64_HW_AFDBM=y ++CONFIG_ARM64_PAN=y ++CONFIG_ARM64_LSE_ATOMICS=y ++CONFIG_ARM64_USE_LSE_ATOMICS=y ++CONFIG_ARM64_VHE=y ++# end of ARMv8.1 architectural features ++ ++# ++# ARMv8.2 architectural features ++# ++CONFIG_ARM64_UAO=y ++# CONFIG_ARM64_PMEM is not set ++CONFIG_ARM64_RAS_EXTN=y ++CONFIG_ARM64_CNP=y ++# end of ARMv8.2 architectural features ++ ++# ++# ARMv8.3 architectural features ++# ++CONFIG_ARM64_PTR_AUTH=y ++# end of ARMv8.3 architectural features ++ ++# ++# ARMv8.5 architectural features ++# ++CONFIG_ARM64_E0PD=y ++CONFIG_ARCH_RANDOM=y ++# end of ARMv8.5 architectural features ++ ++CONFIG_ARM64_SVE=y ++CONFIG_ARM64_MODULE_PLTS=y ++# CONFIG_ARM64_PSEUDO_NMI is not set ++# CONFIG_RANDOMIZE_BASE is not set ++# end of Kernel Features ++ ++# ++# Boot options ++# ++CONFIG_CMDLINE="" ++CONFIG_EFI_STUB=y ++CONFIG_EFI=y ++CONFIG_DMI=y ++# end of Boot options ++ ++CONFIG_SYSVIPC_COMPAT=y ++CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++CONFIG_HIBERNATE_CALLBACKS=y ++CONFIG_HIBERNATION=y ++CONFIG_PM_STD_PARTITION="" ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++# CONFIG_PM_WAKELOCKS is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_CPU_PM=y ++# CONFIG_ENERGY_MODEL is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_ARCH_HIBERNATION_HEADER=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# end of Power management options ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Idle ++# ++CONFIG_CPU_IDLE=y ++CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y ++CONFIG_CPU_IDLE_GOV_LADDER=y ++CONFIG_CPU_IDLE_GOV_MENU=y ++# CONFIG_CPU_IDLE_GOV_TEO is not set ++CONFIG_DT_IDLE_STATES=y ++ ++# ++# ARM CPU Idle Drivers ++# ++CONFIG_ARM_CPUIDLE=y ++# CONFIG_ARM_PSCI_CPUIDLE is not set ++# end of ARM CPU Idle Drivers ++# end of CPU Idle ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++# CONFIG_CPU_FREQ_STAT is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=m ++CONFIG_CPU_FREQ_GOV_USERSPACE=m ++CONFIG_CPU_FREQ_GOV_ONDEMAND=m ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m ++CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y ++ ++# ++# CPU frequency scaling drivers ++# ++CONFIG_CPUFREQ_DT=m ++CONFIG_CPUFREQ_DT_PLATDEV=y ++# CONFIG_QORIQ_CPUFREQ is not set ++# end of CPU Frequency scaling ++# end of CPU Power Management ++ ++# ++# Firmware Drivers ++# ++# CONFIG_ARM_SCMI_PROTOCOL is not set ++# CONFIG_ARM_SCPI_PROTOCOL is not set ++# CONFIG_ARM_SDE_INTERFACE is not set ++CONFIG_DMIID=y ++# CONFIG_DMI_SYSFS is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++CONFIG_ARM_PSCI_FW=y ++# CONFIG_ARM_PSCI_CHECKER is not set ++# CONFIG_GOOGLE_FIRMWARE is not set ++ ++# ++# EFI (Extensible Firmware Interface) Support ++# ++CONFIG_EFI_VARS=y ++CONFIG_EFI_ESRT=y ++CONFIG_EFI_VARS_PSTORE=y ++# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set ++CONFIG_EFI_PARAMS_FROM_FDT=y ++CONFIG_EFI_RUNTIME_WRAPPERS=y ++CONFIG_EFI_ARMSTUB=y ++CONFIG_EFI_ARMSTUB_DTB_LOADER=y ++CONFIG_EFI_BOOTLOADER_CONTROL=y ++# CONFIG_EFI_CAPSULE_LOADER is not set ++# CONFIG_EFI_TEST is not set ++# CONFIG_RESET_ATTACK_MITIGATION is not set ++# CONFIG_EFI_DISABLE_PCI_DMA is not set ++# end of EFI (Extensible Firmware Interface) Support ++ ++CONFIG_EFI_EARLYCON=y ++ ++# ++# Tegra firmware driver ++# ++# end of Tegra firmware driver ++# end of Firmware Drivers ++ ++CONFIG_ARCH_SUPPORTS_ACPI=y ++# CONFIG_ACPI is not set ++# CONFIG_VIRTUALIZATION is not set ++# CONFIG_ARM64_CRYPTO is not set ++ ++# ++# General architecture-dependent options ++# ++CONFIG_CRASH_CORE=y ++CONFIG_KEXEC_CORE=y ++CONFIG_KPROBES=y ++CONFIG_JUMP_LABEL=y ++CONFIG_STATIC_KEYS_SELFTEST=y ++CONFIG_UPROBES=y ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_KRETPROBES=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_ARCH_HAS_FORTIFY_SOURCE=y ++CONFIG_ARCH_HAS_KEEPINITRD=y ++CONFIG_ARCH_HAS_SET_MEMORY=y ++CONFIG_ARCH_HAS_SET_DIRECT_MAP=y ++CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y ++CONFIG_HAVE_ASM_MODVERSIONS=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_RSEQ=y ++CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y ++CONFIG_MMU_GATHER_TABLE_FREE=y ++CONFIG_MMU_GATHER_RCU_TABLE_FREE=y ++CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y ++CONFIG_HAVE_CMPXCHG_LOCAL=y ++CONFIG_HAVE_CMPXCHG_DOUBLE=y ++CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_SECCOMP_FILTER=y ++CONFIG_HAVE_ARCH_STACKLEAK=y ++CONFIG_HAVE_STACKPROTECTOR=y ++CONFIG_CC_HAS_STACKPROTECTOR_NONE=y ++CONFIG_STACKPROTECTOR=y ++CONFIG_STACKPROTECTOR_STRONG=y ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y ++CONFIG_HAVE_ARCH_HUGE_VMAP=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_RELA=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_ARCH_MMAP_RND_BITS=18 ++CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y ++CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 ++CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y ++CONFIG_HAVE_COPY_THREAD_TLS=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_COMPAT_OLD_SIGACTION=y ++CONFIG_COMPAT_32BIT_TIME=y ++CONFIG_HAVE_ARCH_VMAP_STACK=y ++CONFIG_VMAP_STACK=y ++CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y ++CONFIG_STRICT_KERNEL_RWX=y ++CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y ++CONFIG_STRICT_MODULE_RWX=y ++CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y ++CONFIG_ARCH_USE_MEMREMAP_PROT=y ++# CONFIG_LOCK_EVENT_COUNTS is not set ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++# end of GCOV-based kernel profiling ++ ++CONFIG_PLUGIN_HOSTCC="" ++CONFIG_HAVE_GCC_PLUGINS=y ++# end of General architecture-dependent options ++ ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++CONFIG_MODULE_COMPRESS=y ++#CONFIG_MODULE_COMPRESS_GZIP is not set ++CONFIG_MODULE_COMPRESS_XZ=y ++# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++CONFIG_BLK_RQ_ALLOC_TIME=y ++CONFIG_BLK_SCSI_REQUEST=y ++CONFIG_BLK_CGROUP_RWSTAT=y ++CONFIG_BLK_DEV_BSG=y ++CONFIG_BLK_DEV_BSGLIB=y ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_DEV_ZONED is not set ++CONFIG_BLK_DEV_THROTTLING=y ++# CONFIG_BLK_DEV_THROTTLING_LOW is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++CONFIG_BLK_WBT=y ++CONFIG_BLK_CGROUP_IOLATENCY=y ++CONFIG_BLK_CGROUP_IOCOST=y ++CONFIG_BLK_WBT_MQ=y ++# CONFIG_BLK_DEBUG_FS is not set ++# CONFIG_BLK_SED_OPAL is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_AIX_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++CONFIG_EFI_PARTITION=y ++# CONFIG_SYSV68_PARTITION is not set ++# CONFIG_CMDLINE_PARTITION is not set ++# end of Partition Types ++ ++CONFIG_BLOCK_COMPAT=y ++CONFIG_BLK_MQ_PCI=y ++CONFIG_BLK_PM=y ++ ++# ++# IO Schedulers ++# ++CONFIG_MQ_IOSCHED_DEADLINE=y ++CONFIG_MQ_IOSCHED_KYBER=y ++CONFIG_IOSCHED_BFQ=y ++CONFIG_BFQ_GROUP_IOSCHED=y ++# CONFIG_BFQ_CGROUP_DEBUG is not set ++# end of IO Schedulers ++ ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_MUTEX_SPIN_ON_OWNER=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y ++CONFIG_QUEUED_SPINLOCKS=y ++CONFIG_ARCH_USE_QUEUED_RWLOCKS=y ++CONFIG_QUEUED_RWLOCKS=y ++CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y ++CONFIG_FREEZER=y ++ ++# ++# Executable file formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_COMPAT_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++CONFIG_BINFMT_MISC=m ++CONFIG_COREDUMP=y ++# end of Executable file formats ++ ++# ++# Memory Management options ++# ++CONFIG_SELECT_MEMORY_MODEL=y ++# CONFIG_FLATMEM_MANUAL is not set ++CONFIG_SPARSEMEM_MANUAL=y ++CONFIG_SPARSEMEM=y ++CONFIG_HAVE_MEMORY_PRESENT=y ++CONFIG_SPARSEMEM_EXTREME=y ++CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y ++CONFIG_SPARSEMEM_VMEMMAP=y ++CONFIG_HAVE_FAST_GUP=y ++CONFIG_ARCH_KEEP_MEMBLOCK=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_MEMORY_HOTPLUG is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++CONFIG_CONTIG_ALLOC=y ++CONFIG_PHYS_ADDR_T_64BIT=y ++CONFIG_BOUNCE=y ++CONFIG_KSM=y ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y ++# CONFIG_MEMORY_FAILURE is not set ++CONFIG_TRANSPARENT_HUGEPAGE=y ++# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set ++CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y ++CONFIG_TRANSPARENT_HUGE_PAGECACHE=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_FRONTSWAP=y ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=7 ++CONFIG_ZSWAP=y ++CONFIG_ZPOOL=y ++CONFIG_ZBUD=m ++CONFIG_Z3FOLD=m ++CONFIG_ZSMALLOC=m ++# CONFIG_PGTABLE_MAPPING is not set ++# CONFIG_ZSMALLOC_STAT is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_ARCH_HAS_PTE_DEVMAP=y ++# CONFIG_PERCPU_STATS is not set ++# CONFIG_GUP_BENCHMARK is not set ++# CONFIG_READ_ONLY_THP_FOR_FS is not set ++CONFIG_ARCH_HAS_PTE_SPECIAL=y ++# end of Memory Management options ++ ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++CONFIG_PACKET_DIAG=m ++CONFIG_UNIX=y ++CONFIG_UNIX_SCM=y ++CONFIG_UNIX_DIAG=m ++# CONFIG_TLS is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++# CONFIG_XDP_SOCKETS is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++# CONFIG_IP_ADVANCED_ROUTER is not set ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++CONFIG_NET_IP_TUNNEL=m ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_IPVTI is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_NET_FOU_IP_TUNNELS is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++CONFIG_INET_TUNNEL=m ++CONFIG_INET_DIAG=m ++CONFIG_INET_TCP_DIAG=m ++CONFIG_INET_UDP_DIAG=m ++CONFIG_INET_RAW_DIAG=m ++CONFIG_INET_DIAG_DESTROY=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++CONFIG_IPV6=m ++CONFIG_IPV6_ROUTER_PREF=y ++CONFIG_IPV6_ROUTE_INFO=y ++CONFIG_IPV6_OPTIMISTIC_DAD=y ++# CONFIG_INET6_AH is not set ++# CONFIG_INET6_ESP is not set ++# CONFIG_INET6_IPCOMP is not set ++# CONFIG_IPV6_MIP6 is not set ++CONFIG_INET6_TUNNEL=m ++# CONFIG_IPV6_VTI is not set ++CONFIG_IPV6_SIT=m ++CONFIG_IPV6_SIT_6RD=y ++CONFIG_IPV6_NDISC_NODETYPE=y ++CONFIG_IPV6_TUNNEL=m ++# CONFIG_IPV6_MULTIPLE_TABLES is not set ++# CONFIG_IPV6_MROUTE is not set ++# CONFIG_IPV6_SEG6_LWTUNNEL is not set ++# CONFIG_IPV6_SEG6_HMAC is not set ++# CONFIG_MPTCP is not set ++# CONFIG_NETWORK_SECMARK is not set ++CONFIG_NET_PTP_CLASSIFY=y ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_BPFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++CONFIG_STP=m ++CONFIG_GARP=m ++CONFIG_MRP=m ++CONFIG_BRIDGE=m ++CONFIG_BRIDGE_IGMP_SNOOPING=y ++CONFIG_BRIDGE_VLAN_FILTERING=y ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++CONFIG_VLAN_8021Q=m ++CONFIG_VLAN_8021Q_GVRP=y ++CONFIG_VLAN_8021Q_MVRP=y ++# CONFIG_DECNET is not set ++CONFIG_LLC=m ++# CONFIG_LLC2 is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_6LOWPAN is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_DNS_RESOLVER is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++CONFIG_NETLINK_DIAG=m ++# CONFIG_MPLS is not set ++# CONFIG_NET_NSH is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++CONFIG_BPF_JIT=y ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_NET_DROP_MONITOR is not set ++# end of Network testing ++# end of Networking options ++ ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_PSAMPLE is not set ++# CONFIG_NET_IFE is not set ++# CONFIG_LWTUNNEL is not set ++CONFIG_DST_CACHE=y ++CONFIG_GRO_CELLS=y ++CONFIG_PAGE_POOL=y ++# CONFIG_FAILOVER is not set ++CONFIG_ETHTOOL_NETLINK=y ++CONFIG_HAVE_EBPF_JIT=y ++ ++# ++# Device Drivers ++# ++CONFIG_ARM_AMBA=y ++CONFIG_HAVE_PCI=y ++CONFIG_PCI=y ++CONFIG_PCI_DOMAINS=y ++CONFIG_PCI_DOMAINS_GENERIC=y ++CONFIG_PCI_SYSCALL=y ++CONFIG_PCIEPORTBUS=y ++CONFIG_HOTPLUG_PCI_PCIE=y ++CONFIG_PCIEAER=y ++# CONFIG_PCIEAER_INJECT is not set ++CONFIG_PCIE_ECRC=y ++CONFIG_PCIEASPM=y ++CONFIG_PCIEASPM_DEFAULT=y ++# CONFIG_PCIEASPM_POWERSAVE is not set ++# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set ++# CONFIG_PCIEASPM_PERFORMANCE is not set ++CONFIG_PCIE_PME=y ++# CONFIG_PCIE_DPC is not set ++CONFIG_PCIE_PTM=y ++# CONFIG_PCIE_BW is not set ++CONFIG_PCI_MSI=y ++CONFIG_PCI_MSI_IRQ_DOMAIN=y ++CONFIG_PCI_QUIRKS=y ++# CONFIG_PCI_DEBUG is not set ++CONFIG_PCI_REALLOC_ENABLE_AUTO=y ++CONFIG_PCI_STUB=m ++# CONFIG_PCI_PF_STUB is not set ++CONFIG_PCI_ATS=y ++CONFIG_PCI_IOV=y ++CONFIG_PCI_PRI=y ++CONFIG_PCI_PASID=y ++CONFIG_PCI_LABEL=y ++CONFIG_HOTPLUG_PCI=y ++# CONFIG_HOTPLUG_PCI_CPCI is not set ++# CONFIG_HOTPLUG_PCI_SHPC is not set ++ ++# ++# PCI controller drivers ++# ++# CONFIG_PCI_FTPCI100 is not set ++# CONFIG_PCI_HOST_GENERIC is not set ++# CONFIG_PCIE_XILINX is not set ++# CONFIG_PCI_XGENE is not set ++# CONFIG_PCIE_ALTERA is not set ++# CONFIG_PCI_HOST_THUNDER_PEM is not set ++# CONFIG_PCI_HOST_THUNDER_ECAM is not set ++CONFIG_PCI_BAIKAL=m ++ ++# ++# DesignWare PCI Core Support ++# ++CONFIG_PCIE_DW=y ++CONFIG_PCIE_DW_HOST=y ++CONFIG_PCIE_DW_PLAT=y ++CONFIG_PCIE_DW_PLAT_HOST=y ++# CONFIG_PCIE_DW_PLAT_EP is not set ++# CONFIG_PCI_HISI is not set ++# CONFIG_PCIE_KIRIN is not set ++# CONFIG_PCI_MESON is not set ++# CONFIG_PCIE_AL is not set ++# end of DesignWare PCI Core Support ++ ++# ++# Cadence PCIe controllers support ++# ++# CONFIG_PCIE_CADENCE_PLAT_HOST is not set ++# CONFIG_PCIE_CADENCE_PLAT_EP is not set ++# end of Cadence PCIe controllers support ++# end of PCI controller drivers ++ ++# ++# PCI Endpoint ++# ++CONFIG_PCI_ENDPOINT=y ++# CONFIG_PCI_ENDPOINT_CONFIGFS is not set ++# CONFIG_PCI_EPF_TEST is not set ++# end of PCI Endpoint ++ ++# ++# PCI switch controller drivers ++# ++# CONFIG_PCI_SW_SWITCHTEC is not set ++# end of PCI switch controller drivers ++ ++# CONFIG_PCCARD is not set ++# CONFIG_RAPIDIO is not set ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++ ++# ++# Firmware loader ++# ++CONFIG_FW_LOADER=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER is not set ++# CONFIG_FW_LOADER_COMPRESS is not set ++CONFIG_FW_CACHE=y ++# end of Firmware loader ++ ++CONFIG_ALLOW_DEV_COREDUMP=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set ++CONFIG_GENERIC_CPU_AUTOPROBE=y ++CONFIG_GENERIC_CPU_VULNERABILITIES=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_REGMAP_MMIO=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_DMA_FENCE_TRACE is not set ++CONFIG_GENERIC_ARCH_TOPOLOGY=y ++# end of Generic Driver Options ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_MOXTET is not set ++# CONFIG_SIMPLE_PM_BUS is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# end of Bus devices ++ ++CONFIG_CONNECTOR=m ++# CONFIG_GNSS is not set ++CONFIG_MTD=m ++# CONFIG_MTD_TESTS is not set ++ ++# ++# Partition parsers ++# ++# CONFIG_MTD_AR7_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=m ++CONFIG_MTD_OF_PARTS=m ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++# end of Partition parsers ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=m ++CONFIG_MTD_BLOCK=m ++# CONFIG_MTD_BLOCK_RO is not set ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_SWAP is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++CONFIG_MTD_JEDECPROBE=m ++CONFIG_MTD_GEN_PROBE=m ++# CONFIG_MTD_CFI_ADV_OPTIONS is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_INTELEXT is not set ++# CONFIG_MTD_CFI_AMDSTD is not set ++# CONFIG_MTD_CFI_STAA is not set ++CONFIG_MTD_CFI_UTIL=m ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++# end of RAM/ROM/Flash chip drivers ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PHYSMAP is not set ++# CONFIG_MTD_INTEL_VR_NOR is not set ++# CONFIG_MTD_PLATRAM is not set ++# end of Mapping drivers for chip access ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_PMC551 is not set ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_MCHP23K256 is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++# end of Self-contained MTD device drivers ++ ++# CONFIG_MTD_ONENAND is not set ++# CONFIG_MTD_RAW_NAND is not set ++# CONFIG_MTD_SPI_NAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# end of LPDDR & LPDDR2 PCM memory drivers ++ ++CONFIG_MTD_SPI_NOR=m ++CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y ++# CONFIG_SPI_CADENCE_QUADSPI is not set ++# CONFIG_SPI_MTK_QUADSPI is not set ++# CONFIG_MTD_UBI is not set ++# CONFIG_MTD_HYPERBUS is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_KOBJ=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++CONFIG_CDROM=m ++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set ++CONFIG_ZRAM=m ++# CONFIG_ZRAM_WRITEBACK is not set ++# CONFIG_ZRAM_MEMORY_TRACKING is not set ++# CONFIG_BLK_DEV_UMEM is not set ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_DRBD is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_SKD is not set ++# CONFIG_BLK_DEV_SX8 is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=16384 ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_RBD is not set ++# CONFIG_BLK_DEV_RSXX is not set ++ ++# ++# NVME Support ++# ++CONFIG_NVME_CORE=m ++CONFIG_BLK_DEV_NVME=m ++# CONFIG_NVME_MULTIPATH is not set ++# CONFIG_NVME_HWMON is not set ++# CONFIG_NVME_FC is not set ++# CONFIG_NVME_TCP is not set ++# CONFIG_NVME_TARGET is not set ++# end of NVME Support ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_PHANTOM is not set ++# CONFIG_TIFM_CORE is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_HP_ILO is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_PCI_ENDPOINT_TEST is not set ++# CONFIG_XILINX_SDFEC is not set ++# CONFIG_PVPANIC is not set ++CONFIG_TP_BMC=y ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++CONFIG_EEPROM_AT25=m ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++# CONFIG_EEPROM_IDT_89HPESX is not set ++# CONFIG_EEPROM_EE1004 is not set ++# end of EEPROM support ++ ++# CONFIG_CB710_CORE is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# end of Texas Instruments shared transport line discipline ++ ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC & related support ++# ++# CONFIG_VOP_BUS is not set ++# end of Intel MIC & related support ++ ++# CONFIG_GENWQE is not set ++# CONFIG_ECHO is not set ++# CONFIG_MISC_ALCOR_PCI is not set ++# CONFIG_MISC_RTSX_PCI is not set ++# CONFIG_MISC_RTSX_USB is not set ++# CONFIG_HABANA_AI is not set ++# end of Misc devices ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_PROC_FS is not set ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++CONFIG_BLK_DEV_SR=m ++CONFIG_BLK_DEV_SR_VENDOR=y ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++CONFIG_SCSI_CONSTANTS=y ++# CONFIG_SCSI_LOGGING is not set ++CONFIG_SCSI_SCAN_ASYNC=y ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# end of SCSI Transports ++ ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++# end of SCSI device support ++ ++CONFIG_HAVE_PATA_PLATFORM=y ++CONFIG_ATA=y ++CONFIG_ATA_VERBOSE_ERROR=y ++CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# ++CONFIG_SATA_AHCI=y ++CONFIG_SATA_MOBILE_LPM_POLICY=0 ++CONFIG_SATA_AHCI_PLATFORM=y ++# CONFIG_AHCI_CEVA is not set ++# CONFIG_AHCI_QORIQ is not set ++# CONFIG_SATA_INIC162X is not set ++# CONFIG_SATA_ACARD_AHCI is not set ++# CONFIG_SATA_SIL24 is not set ++# CONFIG_ATA_SFF is not set ++CONFIG_MD=y ++CONFIG_BLK_DEV_MD=m ++# CONFIG_MD_LINEAR is not set ++CONFIG_MD_RAID0=m ++CONFIG_MD_RAID1=m ++CONFIG_MD_RAID10=m ++CONFIG_MD_RAID456=m ++# CONFIG_MD_MULTIPATH is not set ++# CONFIG_MD_FAULTY is not set ++# CONFIG_BCACHE is not set ++CONFIG_BLK_DEV_DM_BUILTIN=y ++CONFIG_BLK_DEV_DM=m ++# CONFIG_DM_DEBUG is not set ++CONFIG_DM_BUFIO=m ++# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set ++CONFIG_DM_BIO_PRISON=m ++CONFIG_DM_PERSISTENT_DATA=m ++# CONFIG_DM_UNSTRIPED is not set ++CONFIG_DM_CRYPT=m ++CONFIG_DM_SNAPSHOT=m ++CONFIG_DM_THIN_PROVISIONING=m ++# CONFIG_DM_CACHE is not set ++# CONFIG_DM_WRITECACHE is not set ++# CONFIG_DM_ERA is not set ++# CONFIG_DM_CLONE is not set ++CONFIG_DM_MIRROR=m ++# CONFIG_DM_LOG_USERSPACE is not set ++CONFIG_DM_RAID=m ++CONFIG_DM_ZERO=m ++# CONFIG_DM_MULTIPATH is not set ++# CONFIG_DM_DELAY is not set ++# CONFIG_DM_DUST is not set ++CONFIG_DM_UEVENT=y ++# CONFIG_DM_FLAKEY is not set ++# CONFIG_DM_VERITY is not set ++# CONFIG_DM_SWITCH is not set ++# CONFIG_DM_LOG_WRITES is not set ++# CONFIG_DM_INTEGRITY is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_FIREWIRE_NOSY is not set ++# end of IEEE 1394 (FireWire) support ++ ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++CONFIG_NET_CORE=y ++CONFIG_BONDING=m ++CONFIG_DUMMY=m ++# CONFIG_WIREGUARD is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_NET_FC is not set ++# CONFIG_NET_TEAM is not set ++CONFIG_MACVLAN=m ++CONFIG_MACVTAP=m ++CONFIG_IPVLAN=m ++CONFIG_IPVTAP=m ++# CONFIG_VXLAN is not set ++# CONFIG_GENEVE is not set ++# CONFIG_GTP is not set ++# CONFIG_MACSEC is not set ++# CONFIG_NETCONSOLE is not set ++CONFIG_TUN=m ++CONFIG_TAP=m ++# CONFIG_TUN_VNET_CROSS_LE is not set ++CONFIG_VETH=m ++CONFIG_NLMON=m ++# CONFIG_ARCNET is not set ++ ++# ++# Distributed Switch Architecture drivers ++# ++# end of Distributed Switch Architecture drivers ++ ++CONFIG_ETHERNET=y ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_NET_VENDOR_ADAPTEC is not set ++# CONFIG_NET_VENDOR_AGERE is not set ++# CONFIG_NET_VENDOR_ALACRITECH is not set ++# CONFIG_NET_VENDOR_ALTEON is not set ++# CONFIG_ALTERA_TSE is not set ++# CONFIG_NET_VENDOR_AMAZON is not set ++# CONFIG_NET_VENDOR_AMD is not set ++# CONFIG_NET_VENDOR_AQUANTIA is not set ++# CONFIG_NET_VENDOR_ARC is not set ++# CONFIG_NET_VENDOR_ATHEROS is not set ++# CONFIG_NET_VENDOR_AURORA is not set ++# CONFIG_NET_VENDOR_BROADCOM is not set ++# CONFIG_NET_VENDOR_BROCADE is not set ++# CONFIG_NET_VENDOR_CADENCE is not set ++# CONFIG_NET_VENDOR_CAVIUM is not set ++# CONFIG_NET_VENDOR_CHELSIO is not set ++# CONFIG_NET_VENDOR_CISCO is not set ++# CONFIG_NET_VENDOR_CORTINA is not set ++# CONFIG_DNET is not set ++# CONFIG_NET_VENDOR_DEC is not set ++# CONFIG_NET_VENDOR_DLINK is not set ++# CONFIG_NET_VENDOR_EMULEX is not set ++# CONFIG_NET_VENDOR_EZCHIP is not set ++# CONFIG_NET_VENDOR_GOOGLE is not set ++# CONFIG_NET_VENDOR_HISILICON is not set ++# CONFIG_NET_VENDOR_HUAWEI is not set ++# CONFIG_NET_VENDOR_INTEL is not set ++# CONFIG_JME is not set ++# CONFIG_NET_VENDOR_MARVELL is not set ++# CONFIG_NET_VENDOR_MELLANOX is not set ++# CONFIG_NET_VENDOR_MICREL is not set ++# CONFIG_NET_VENDOR_MICROCHIP is not set ++# CONFIG_NET_VENDOR_MICROSEMI is not set ++# CONFIG_NET_VENDOR_MYRI is not set ++# CONFIG_FEALNX is not set ++# CONFIG_NET_VENDOR_NATSEMI is not set ++# CONFIG_NET_VENDOR_NETERION is not set ++# CONFIG_NET_VENDOR_NETRONOME is not set ++# CONFIG_NET_VENDOR_NI is not set ++# CONFIG_NET_VENDOR_NVIDIA is not set ++# CONFIG_NET_VENDOR_OKI is not set ++# CONFIG_ETHOC is not set ++# CONFIG_NET_VENDOR_PACKET_ENGINES is not set ++# CONFIG_NET_VENDOR_PENSANDO is not set ++# CONFIG_NET_VENDOR_QLOGIC is not set ++# CONFIG_NET_VENDOR_QUALCOMM is not set ++# CONFIG_NET_VENDOR_RDC is not set ++# CONFIG_NET_VENDOR_REALTEK is not set ++# CONFIG_NET_VENDOR_RENESAS is not set ++# CONFIG_NET_VENDOR_ROCKER is not set ++# CONFIG_NET_VENDOR_SAMSUNG is not set ++# CONFIG_NET_VENDOR_SEEQ is not set ++# CONFIG_NET_VENDOR_SOLARFLARE is not set ++# CONFIG_NET_VENDOR_SILAN is not set ++# CONFIG_NET_VENDOR_SIS is not set ++# CONFIG_NET_VENDOR_SMSC is not set ++# CONFIG_NET_VENDOR_SOCIONEXT is not set ++CONFIG_NET_VENDOR_STMICRO=y ++CONFIG_STMMAC_ETH=y ++# CONFIG_STMMAC_SELFTESTS is not set ++CONFIG_STMMAC_PLATFORM=y ++# CONFIG_DWMAC_DWC_QOS_ETH is not set ++CONFIG_DWMAC_GENERIC=y ++CONFIG_DWMAC_BAIKAL=y ++# CONFIG_STMMAC_PCI is not set ++# CONFIG_NET_VENDOR_SUN is not set ++# CONFIG_NET_VENDOR_SYNOPSYS is not set ++# CONFIG_NET_VENDOR_TEHUTI is not set ++# CONFIG_NET_VENDOR_TI is not set ++# CONFIG_NET_VENDOR_VIA is not set ++# CONFIG_NET_VENDOR_WIZNET is not set ++# CONFIG_NET_VENDOR_XILINX is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++CONFIG_MDIO_DEVICE=y ++CONFIG_MDIO_BUS=y ++# CONFIG_MDIO_BCM_UNIMAC is not set ++CONFIG_MDIO_BITBANG=m ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set ++CONFIG_MDIO_GPIO=m ++# CONFIG_MDIO_HISI_FEMAC is not set ++# CONFIG_MDIO_MSCC_MIIM is not set ++# CONFIG_MDIO_OCTEON is not set ++# CONFIG_MDIO_THUNDER is not set ++CONFIG_PHYLINK=y ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_SFP is not set ++# CONFIG_ADIN_PHY is not set ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AX88796B_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_BCM84881_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_CORTINA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83822_PHY is not set ++# CONFIG_DP83TC811_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++# CONFIG_DP83869_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++CONFIG_MARVELL_PHY=m ++# CONFIG_MARVELL_10G_PHY is not set ++CONFIG_MICREL_PHY=m ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROCHIP_T1_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_NXP_TJA11XX_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++CONFIG_REALTEK_PHY=m ++# CONFIG_RENESAS_PHY is not set ++# CONFIG_ROCKCHIP_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++CONFIG_PPP=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_DEFLATE=m ++# CONFIG_PPP_FILTER is not set ++CONFIG_PPP_MPPE=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPPOE=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++# CONFIG_SLIP is not set ++CONFIG_SLHC=m ++# CONFIG_USB_NET_DRIVERS is not set ++# CONFIG_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_VMXNET3 is not set ++# CONFIG_NETDEVSIM is not set ++# CONFIG_NET_FAILOVER is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=m ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ADP5588 is not set ++# CONFIG_KEYBOARD_ADP5589 is not set ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_QT1050 is not set ++# CONFIG_KEYBOARD_QT1070 is not set ++# CONFIG_KEYBOARD_QT2160 is not set ++# CONFIG_KEYBOARD_DLINK_DIR685 is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYBOARD_GPIO_POLLED is not set ++# CONFIG_KEYBOARD_TCA6416 is not set ++# CONFIG_KEYBOARD_TCA8418 is not set ++# CONFIG_KEYBOARD_MATRIX is not set ++# CONFIG_KEYBOARD_LM8333 is not set ++# CONFIG_KEYBOARD_MAX7359 is not set ++# CONFIG_KEYBOARD_MCS is not set ++# CONFIG_KEYBOARD_MPR121 is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_OPENCORES is not set ++# CONFIG_KEYBOARD_SAMSUNG is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_OMAP4 is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_CAP11XX is not set ++# CONFIG_KEYBOARD_BCM is not set ++CONFIG_INPUT_MOUSE=y ++# CONFIG_MOUSE_PS2 is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_AMBAKMI is not set ++# CONFIG_SERIO_PCIPS2 is not set ++# CONFIG_SERIO_LIBPS2 is not set ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_SERIO_GPIO_PS2 is not set ++# CONFIG_USERIO is not set ++# CONFIG_GAMEPORT is not set ++# end of Hardware I/O ports ++# end of Input device support ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_VT_CONSOLE_SLEEP=y ++CONFIG_HW_CONSOLE=y ++CONFIG_VT_HW_CONSOLE_BINDING=y ++CONFIG_UNIX98_PTYS=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_NOZOMI is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++# CONFIG_NULL_TTY is not set ++CONFIG_LDISC_AUTOLOAD=y ++CONFIG_DEVMEM=y ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_EARLYCON=y ++CONFIG_SERIAL_8250=y ++CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y ++# CONFIG_SERIAL_8250_16550A_VARIANTS is not set ++# CONFIG_SERIAL_8250_FINTEK is not set ++CONFIG_SERIAL_8250_CONSOLE=y ++CONFIG_SERIAL_8250_DMA=y ++CONFIG_SERIAL_8250_PCI=y ++CONFIG_SERIAL_8250_EXAR=y ++CONFIG_SERIAL_8250_NR_UARTS=2 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=2 ++CONFIG_SERIAL_8250_EXTENDED=y ++# CONFIG_SERIAL_8250_MANY_PORTS is not set ++# CONFIG_SERIAL_8250_ASPEED_VUART is not set ++# CONFIG_SERIAL_8250_SHARE_IRQ is not set ++# CONFIG_SERIAL_8250_DETECT_IRQ is not set ++# CONFIG_SERIAL_8250_RSA is not set ++CONFIG_SERIAL_8250_DWLIB=y ++CONFIG_SERIAL_8250_FSL=y ++CONFIG_SERIAL_8250_DW=y ++# CONFIG_SERIAL_8250_RT288X is not set ++CONFIG_SERIAL_OF_PLATFORM=y ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_AMBA_PL010 is not set ++# CONFIG_SERIAL_AMBA_PL011 is not set ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_KGDB_NMI is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_CONSOLE_POLL=y ++# CONFIG_SERIAL_JSM is not set ++# CONFIG_SERIAL_SIFIVE is not set ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_RP2 is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_FSL_LINFLEXUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# end of Serial drivers ++ ++CONFIG_SERIAL_MCTRL_GPIO=y ++# CONFIG_SERIAL_DEV_BUS is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=m ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set ++# CONFIG_HW_RANDOM_CAVIUM is not set ++# CONFIG_APPLICOM is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_DEVPORT=y ++# CONFIG_XILLYBUS is not set ++# end of Character devices ++ ++# CONFIG_RANDOM_TRUST_BOOTLOADER is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=m ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_GPMUX is not set ++# CONFIG_I2C_MUX_LTC4306 is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_PINCTRL is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_DEMUX_PINCTRL is not set ++# CONFIG_I2C_MUX_MLXCPLD is not set ++# end of Multiplexer I2C Chip support ++ ++CONFIG_I2C_HELPER_AUTO=y ++CONFIG_I2C_ALGOBIT=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++# CONFIG_I2C_ALI1535 is not set ++# CONFIG_I2C_ALI1563 is not set ++# CONFIG_I2C_ALI15X3 is not set ++# CONFIG_I2C_AMD756 is not set ++# CONFIG_I2C_AMD8111 is not set ++# CONFIG_I2C_I801 is not set ++# CONFIG_I2C_ISCH is not set ++# CONFIG_I2C_PIIX4 is not set ++# CONFIG_I2C_NFORCE2 is not set ++# CONFIG_I2C_NVIDIA_GPU is not set ++# CONFIG_I2C_SIS5595 is not set ++# CONFIG_I2C_SIS630 is not set ++# CONFIG_I2C_SIS96X is not set ++# CONFIG_I2C_VIA is not set ++# CONFIG_I2C_VIAPRO is not set ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CADENCE is not set ++# CONFIG_I2C_CBUS_GPIO is not set ++CONFIG_I2C_DESIGNWARE_CORE=y ++CONFIG_I2C_DESIGNWARE_PLATFORM=y ++# CONFIG_I2C_DESIGNWARE_SLAVE is not set ++# CONFIG_I2C_DESIGNWARE_PCI is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_NOMADIK is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_THUNDERX is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# end of I2C Hardware Bus support ++ ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# end of I2C support ++ ++# CONFIG_I3C is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++CONFIG_SPI_MEM=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++CONFIG_SPI_DESIGNWARE=y ++# CONFIG_SPI_DW_PCI is not set ++CONFIG_SPI_DW_MMIO=y ++# CONFIG_SPI_NXP_FLEXSPI is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PL022 is not set ++# CONFIG_SPI_PXA2XX is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_SIFIVE is not set ++# CONFIG_SPI_MXIC is not set ++# CONFIG_SPI_THUNDERX is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++CONFIG_SPI_SPIDEV=y ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPI_SLAVE is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++CONFIG_PPS=y ++# CONFIG_PPS_DEBUG is not set ++ ++# ++# PPS clients support ++# ++# CONFIG_PPS_CLIENT_KTIMER is not set ++# CONFIG_PPS_CLIENT_LDISC is not set ++# CONFIG_PPS_CLIENT_GPIO is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++CONFIG_PTP_1588_CLOCK=y ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++# CONFIG_PTP_1588_CLOCK_IDTCM is not set ++# end of PTP clock support ++ ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_GENERIC_PINCONF=y ++# CONFIG_DEBUG_PINCTRL is not set ++# CONFIG_PINCTRL_AMD is not set ++# CONFIG_PINCTRL_MCP23S08 is not set ++# CONFIG_PINCTRL_SINGLE is not set ++# CONFIG_PINCTRL_SX150X is not set ++# CONFIG_PINCTRL_STMFX is not set ++# CONFIG_PINCTRL_OCELOT is not set ++# CONFIG_PINCTRL_EQUILIBRIUM is not set ++CONFIG_GPIOLIB=y ++CONFIG_GPIOLIB_FASTPATH_LIMIT=512 ++CONFIG_OF_GPIO=y ++CONFIG_GPIOLIB_IRQCHIP=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_GENERIC=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_CADENCE is not set ++CONFIG_GPIO_DWAPB=y ++# CONFIG_GPIO_EXAR is not set ++# CONFIG_GPIO_FTGPIO010 is not set ++CONFIG_GPIO_GENERIC_PLATFORM=y ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_HLWD is not set ++# CONFIG_GPIO_LOGICVC is not set ++# CONFIG_GPIO_MB86S7X is not set ++# CONFIG_GPIO_PL061 is not set ++# CONFIG_GPIO_SAMA5D2_PIOBU is not set ++# CONFIG_GPIO_SIFIVE is not set ++# CONFIG_GPIO_SYSCON is not set ++# CONFIG_GPIO_XGENE is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_AMD_FCH is not set ++# end of Memory mapped GPIO drivers ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_GW_PLD is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++CONFIG_GPIO_PCF857X=y ++# CONFIG_GPIO_TPIC2810 is not set ++# end of I2C GPIO expanders ++ ++# ++# MFD GPIO expanders ++# ++# end of MFD GPIO expanders ++ ++# ++# PCI GPIO expanders ++# ++# CONFIG_GPIO_BT8XX is not set ++# CONFIG_GPIO_PCI_IDIO_16 is not set ++# CONFIG_GPIO_PCIE_IDIO_24 is not set ++# CONFIG_GPIO_RDC321X is not set ++# end of PCI GPIO expanders ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX3191X is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++# CONFIG_GPIO_XRA1403 is not set ++# end of SPI GPIO expanders ++ ++# ++# USB GPIO expanders ++# ++# end of USB GPIO expanders ++ ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++CONFIG_POWER_RESET=y ++# CONFIG_POWER_RESET_BRCMSTB is not set ++# CONFIG_POWER_RESET_GPIO is not set ++# CONFIG_POWER_RESET_GPIO_RESTART is not set ++# CONFIG_POWER_RESET_LTC2952 is not set ++# CONFIG_POWER_RESET_RESTART is not set ++# CONFIG_POWER_RESET_XGENE is not set ++# CONFIG_POWER_RESET_SYSCON is not set ++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set ++# CONFIG_SYSCON_REBOOT_MODE is not set ++# CONFIG_NVMEM_REBOOT_MODE is not set ++CONFIG_POWER_SUPPLY=y ++# CONFIG_POWER_SUPPLY_DEBUG is not set ++CONFIG_POWER_SUPPLY_HWMON=y ++# CONFIG_PDA_POWER is not set ++# CONFIG_TEST_POWER is not set ++# CONFIG_CHARGER_ADP5061 is not set ++# CONFIG_BATTERY_DS2780 is not set ++# CONFIG_BATTERY_DS2781 is not set ++# CONFIG_BATTERY_DS2782 is not set ++# CONFIG_BATTERY_SBS is not set ++# CONFIG_CHARGER_SBS is not set ++# CONFIG_MANAGER_SBS is not set ++# CONFIG_BATTERY_BQ27XXX is not set ++# CONFIG_BATTERY_MAX17040 is not set ++# CONFIG_BATTERY_MAX17042 is not set ++# CONFIG_CHARGER_MAX8903 is not set ++# CONFIG_CHARGER_LP8727 is not set ++# CONFIG_CHARGER_GPIO is not set ++# CONFIG_CHARGER_LT3651 is not set ++# CONFIG_CHARGER_DETECTOR_MAX14656 is not set ++# CONFIG_CHARGER_BQ2415X is not set ++# CONFIG_CHARGER_BQ24257 is not set ++# CONFIG_CHARGER_BQ24735 is not set ++# CONFIG_CHARGER_BQ25890 is not set ++# CONFIG_CHARGER_SMB347 is not set ++# CONFIG_BATTERY_GAUGE_LTC2941 is not set ++# CONFIG_CHARGER_RT9455 is not set ++CONFIG_HWMON=y ++# CONFIG_HWMON_DEBUG_CHIP is not set ++ ++# ++# Native drivers ++# ++# CONFIG_SENSORS_AD7314 is not set ++# CONFIG_SENSORS_AD7414 is not set ++# CONFIG_SENSORS_AD7418 is not set ++# CONFIG_SENSORS_ADM1021 is not set ++# CONFIG_SENSORS_ADM1025 is not set ++# CONFIG_SENSORS_ADM1026 is not set ++# CONFIG_SENSORS_ADM1029 is not set ++# CONFIG_SENSORS_ADM1031 is not set ++# CONFIG_SENSORS_ADM1177 is not set ++# CONFIG_SENSORS_ADM9240 is not set ++# CONFIG_SENSORS_ADT7310 is not set ++# CONFIG_SENSORS_ADT7410 is not set ++# CONFIG_SENSORS_ADT7411 is not set ++# CONFIG_SENSORS_ADT7462 is not set ++# CONFIG_SENSORS_ADT7470 is not set ++# CONFIG_SENSORS_ADT7475 is not set ++# CONFIG_SENSORS_AS370 is not set ++# CONFIG_SENSORS_ASC7621 is not set ++# CONFIG_SENSORS_ASPEED is not set ++# CONFIG_SENSORS_ATXP1 is not set ++CONFIG_SENSORS_BT1_PVT=m ++# CONFIG_SENSORS_DRIVETEMP is not set ++# CONFIG_SENSORS_DS620 is not set ++# CONFIG_SENSORS_DS1621 is not set ++# CONFIG_SENSORS_I5K_AMB is not set ++# CONFIG_SENSORS_F71805F is not set ++# CONFIG_SENSORS_F71882FG is not set ++# CONFIG_SENSORS_F75375S is not set ++# CONFIG_SENSORS_FTSTEUTATES is not set ++# CONFIG_SENSORS_GL518SM is not set ++# CONFIG_SENSORS_GL520SM is not set ++# CONFIG_SENSORS_G760A is not set ++# CONFIG_SENSORS_G762 is not set ++# CONFIG_SENSORS_GPIO_FAN is not set ++# CONFIG_SENSORS_HIH6130 is not set ++# CONFIG_SENSORS_IT87 is not set ++# CONFIG_SENSORS_JC42 is not set ++# CONFIG_SENSORS_POWR1220 is not set ++# CONFIG_SENSORS_LINEAGE is not set ++# CONFIG_SENSORS_LTC2945 is not set ++# CONFIG_SENSORS_LTC2947_I2C is not set ++# CONFIG_SENSORS_LTC2947_SPI is not set ++# CONFIG_SENSORS_LTC2990 is not set ++# CONFIG_SENSORS_LTC4151 is not set ++# CONFIG_SENSORS_LTC4215 is not set ++# CONFIG_SENSORS_LTC4222 is not set ++# CONFIG_SENSORS_LTC4245 is not set ++# CONFIG_SENSORS_LTC4260 is not set ++# CONFIG_SENSORS_LTC4261 is not set ++# CONFIG_SENSORS_MAX1111 is not set ++# CONFIG_SENSORS_MAX16065 is not set ++# CONFIG_SENSORS_MAX1619 is not set ++# CONFIG_SENSORS_MAX1668 is not set ++# CONFIG_SENSORS_MAX197 is not set ++# CONFIG_SENSORS_MAX31722 is not set ++# CONFIG_SENSORS_MAX31730 is not set ++# CONFIG_SENSORS_MAX6621 is not set ++# CONFIG_SENSORS_MAX6639 is not set ++# CONFIG_SENSORS_MAX6642 is not set ++# CONFIG_SENSORS_MAX6650 is not set ++# CONFIG_SENSORS_MAX6697 is not set ++# CONFIG_SENSORS_MAX31790 is not set ++# CONFIG_SENSORS_MCP3021 is not set ++# CONFIG_SENSORS_TC654 is not set ++# CONFIG_SENSORS_ADCXX is not set ++# CONFIG_SENSORS_LM63 is not set ++# CONFIG_SENSORS_LM70 is not set ++# CONFIG_SENSORS_LM73 is not set ++# CONFIG_SENSORS_LM75 is not set ++# CONFIG_SENSORS_LM77 is not set ++# CONFIG_SENSORS_LM78 is not set ++# CONFIG_SENSORS_LM80 is not set ++# CONFIG_SENSORS_LM83 is not set ++# CONFIG_SENSORS_LM85 is not set ++# CONFIG_SENSORS_LM87 is not set ++# CONFIG_SENSORS_LM90 is not set ++# CONFIG_SENSORS_LM92 is not set ++# CONFIG_SENSORS_LM93 is not set ++# CONFIG_SENSORS_LM95234 is not set ++# CONFIG_SENSORS_LM95241 is not set ++# CONFIG_SENSORS_LM95245 is not set ++# CONFIG_SENSORS_PC87360 is not set ++# CONFIG_SENSORS_PC87427 is not set ++# CONFIG_SENSORS_NTC_THERMISTOR is not set ++# CONFIG_SENSORS_NCT6683 is not set ++# CONFIG_SENSORS_NCT6775 is not set ++# CONFIG_SENSORS_NCT7802 is not set ++# CONFIG_SENSORS_NCT7904 is not set ++# CONFIG_SENSORS_NPCM7XX is not set ++# CONFIG_SENSORS_OCC_P8_I2C is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_PMBUS is not set ++# CONFIG_SENSORS_SHT15 is not set ++# CONFIG_SENSORS_SHT21 is not set ++# CONFIG_SENSORS_SHT3x is not set ++# CONFIG_SENSORS_SHTC1 is not set ++# CONFIG_SENSORS_SIS5595 is not set ++# CONFIG_SENSORS_DME1737 is not set ++# CONFIG_SENSORS_EMC1403 is not set ++# CONFIG_SENSORS_EMC2103 is not set ++# CONFIG_SENSORS_EMC6W201 is not set ++# CONFIG_SENSORS_SMSC47M1 is not set ++# CONFIG_SENSORS_SMSC47M192 is not set ++# CONFIG_SENSORS_SMSC47B397 is not set ++# CONFIG_SENSORS_SCH5627 is not set ++# CONFIG_SENSORS_SCH5636 is not set ++# CONFIG_SENSORS_STTS751 is not set ++# CONFIG_SENSORS_SMM665 is not set ++# CONFIG_SENSORS_ADC128D818 is not set ++# CONFIG_SENSORS_ADS7828 is not set ++# CONFIG_SENSORS_ADS7871 is not set ++# CONFIG_SENSORS_AMC6821 is not set ++# CONFIG_SENSORS_INA209 is not set ++# CONFIG_SENSORS_INA2XX is not set ++# CONFIG_SENSORS_INA3221 is not set ++# CONFIG_SENSORS_TC74 is not set ++# CONFIG_SENSORS_THMC50 is not set ++# CONFIG_SENSORS_TMP102 is not set ++# CONFIG_SENSORS_TMP103 is not set ++# CONFIG_SENSORS_TMP108 is not set ++# CONFIG_SENSORS_TMP401 is not set ++# CONFIG_SENSORS_TMP421 is not set ++# CONFIG_SENSORS_TMP513 is not set ++# CONFIG_SENSORS_VIA686A is not set ++# CONFIG_SENSORS_VT1211 is not set ++# CONFIG_SENSORS_VT8231 is not set ++# CONFIG_SENSORS_W83773G is not set ++# CONFIG_SENSORS_W83781D is not set ++# CONFIG_SENSORS_W83791D is not set ++# CONFIG_SENSORS_W83792D is not set ++# CONFIG_SENSORS_W83793 is not set ++# CONFIG_SENSORS_W83795 is not set ++# CONFIG_SENSORS_W83L785TS is not set ++# CONFIG_SENSORS_W83L786NG is not set ++# CONFIG_SENSORS_W83627HF is not set ++# CONFIG_SENSORS_W83627EHF is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y ++CONFIG_WATCHDOG_OPEN_TIMEOUT=0 ++CONFIG_WATCHDOG_SYSFS=y ++ ++# ++# Watchdog Pretimeout Governors ++# ++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_GPIO_WATCHDOG=m ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_ZIIRAVE_WATCHDOG is not set ++# CONFIG_ARM_SP805_WATCHDOG is not set ++# CONFIG_ARM_SBSA_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++CONFIG_DW_WATCHDOG=m ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_ALIM7101_WDT is not set ++# CONFIG_I6300ESB_WDT is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# PCI-based Watchdog Cards ++# ++# CONFIG_PCIPCWATCHDOG is not set ++# CONFIG_WDTPCI is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_BD9571MWV is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_MADERA is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_LPC_ICH is not set ++# CONFIG_LPC_SCH is not set ++# CONFIG_MFD_JANZ_CMODIO is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77650 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_CPCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_UCB1400_CORE is not set ++# CONFIG_MFD_RDC321X is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++CONFIG_MFD_SYSCON=y ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_TI_LMU is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TI_LP87565 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TQMX86 is not set ++# CONFIG_MFD_VX855 is not set ++# CONFIG_MFD_LOCHNAGAR is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_MFD_ROHM_BD718XX is not set ++# CONFIG_MFD_ROHM_BD70528 is not set ++# CONFIG_MFD_ROHM_BD71828 is not set ++# CONFIG_MFD_STPMIC1 is not set ++# CONFIG_MFD_STMFX is not set ++# end of Multifunction device drivers ++ ++# CONFIG_REGULATOR is not set ++# CONFIG_RC_CORE is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++CONFIG_VGA_ARB=y ++CONFIG_VGA_ARB_MAX_GPUS=16 ++CONFIG_DRM=y ++# CONFIG_DRM_DP_AUX_CHARDEV is not set ++# CONFIG_DRM_DEBUG_MM is not set ++# CONFIG_DRM_DEBUG_SELFTEST is not set ++CONFIG_DRM_KMS_HELPER=y ++CONFIG_DRM_KMS_FB_HELPER=y ++CONFIG_DRM_FBDEV_EMULATION=y ++CONFIG_DRM_FBDEV_OVERALLOC=100 ++# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set ++# CONFIG_DRM_DP_CEC is not set ++CONFIG_DRM_GEM_CMA_HELPER=y ++CONFIG_DRM_KMS_CMA_HELPER=y ++ ++# ++# I2C encoder or helper chips ++# ++# CONFIG_DRM_I2C_CH7006 is not set ++# CONFIG_DRM_I2C_SIL164 is not set ++# CONFIG_DRM_I2C_NXP_TDA998X is not set ++# CONFIG_DRM_I2C_NXP_TDA9950 is not set ++# end of I2C encoder or helper chips ++ ++# ++# ARM devices ++# ++# CONFIG_DRM_HDLCD is not set ++# CONFIG_DRM_MALI_DISPLAY is not set ++# CONFIG_DRM_KOMEDA is not set ++# end of ARM devices ++ ++CONFIG_DRM_BAIKAL_VDU=y ++# CONFIG_DRM_RADEON is not set ++# CONFIG_DRM_AMDGPU is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++# end of ACP (Audio CoProcessor) Configuration ++ ++# CONFIG_DRM_NOUVEAU is not set ++# CONFIG_DRM_VGEM is not set ++# CONFIG_DRM_VKMS is not set ++# CONFIG_DRM_UDL is not set ++# CONFIG_DRM_AST is not set ++# CONFIG_DRM_MGAG200 is not set ++# CONFIG_DRM_CIRRUS_QEMU is not set ++# CONFIG_DRM_RCAR_DW_HDMI is not set ++# CONFIG_DRM_RCAR_LVDS is not set ++CONFIG_DRM_RCAR_WRITEBACK=y ++# CONFIG_DRM_QXL is not set ++# CONFIG_DRM_BOCHS is not set ++CONFIG_DRM_PANEL=y ++ ++# ++# Display Panels ++# ++# CONFIG_DRM_PANEL_ARM_VERSATILE is not set ++CONFIG_DRM_PANEL_LVDS=m ++# CONFIG_DRM_PANEL_SIMPLE is not set ++# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set ++# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set ++# CONFIG_DRM_PANEL_LG_LB035Q02 is not set ++# CONFIG_DRM_PANEL_LG_LG4573 is not set ++# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set ++# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set ++# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set ++# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set ++# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set ++# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set ++# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set ++# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set ++# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set ++# CONFIG_DRM_PANEL_TPO_TPG110 is not set ++# end of Display Panels ++ ++CONFIG_DRM_BRIDGE=y ++CONFIG_DRM_PANEL_BRIDGE=y ++ ++# ++# Display Interface Bridges ++# ++# CONFIG_DRM_CDNS_DSI is not set ++# CONFIG_DRM_DUMB_VGA_DAC is not set ++# CONFIG_DRM_LVDS_CODEC is not set ++CONFIG_DRM_BAIKAL_HDMI=y ++# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set ++# CONFIG_DRM_NXP_PTN3460 is not set ++# CONFIG_DRM_PARADE_PS8622 is not set ++# CONFIG_DRM_SIL_SII8620 is not set ++# CONFIG_DRM_SII902X is not set ++# CONFIG_DRM_SII9234 is not set ++# CONFIG_DRM_THINE_THC63LVD1024 is not set ++# CONFIG_DRM_TOSHIBA_TC358764 is not set ++# CONFIG_DRM_TOSHIBA_TC358767 is not set ++# CONFIG_DRM_TI_TFP410 is not set ++# CONFIG_DRM_TI_SN65DSI86 is not set ++# CONFIG_DRM_ANALOGIX_ANX6345 is not set ++# CONFIG_DRM_ANALOGIX_ANX78XX is not set ++# CONFIG_DRM_I2C_ADV7511 is not set ++CONFIG_DRM_DW_HDMI=y ++CONFIG_DRM_DW_HDMI_AHB_AUDIO=m ++# CONFIG_DRM_DW_HDMI_I2S_AUDIO is not set ++# CONFIG_DRM_DW_HDMI_CEC is not set ++# end of Display Interface Bridges ++ ++# CONFIG_DRM_ETNAVIV is not set ++# CONFIG_DRM_ARCPGU is not set ++# CONFIG_DRM_HISI_HIBMC is not set ++# CONFIG_DRM_HISI_KIRIN is not set ++# CONFIG_DRM_MXSFB is not set ++# CONFIG_DRM_GM12U320 is not set ++# CONFIG_TINYDRM_HX8357D is not set ++# CONFIG_TINYDRM_ILI9225 is not set ++# CONFIG_TINYDRM_ILI9341 is not set ++# CONFIG_TINYDRM_MI0283QT is not set ++# CONFIG_TINYDRM_REPAPER is not set ++# CONFIG_TINYDRM_ST7586 is not set ++# CONFIG_TINYDRM_ST7735R is not set ++# CONFIG_DRM_PL111 is not set ++# CONFIG_DRM_LIMA is not set ++CONFIG_DRM_PANFROST=m ++# CONFIG_DRM_TIDSS is not set ++# CONFIG_DRM_LEGACY is not set ++CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y ++ ++# ++# ARM GPU Configuration ++# ++CONFIG_MALI_MIDGARD=m ++# CONFIG_MALI_GATOR_SUPPORT is not set ++# CONFIG_MALI_MIDGARD_ENABLE_TRACE is not set ++CONFIG_MALI_DEVFREQ=y ++# CONFIG_MALI_DMA_FENCE is not set ++CONFIG_MALI_PLATFORM_NAME="devicetree" ++# CONFIG_MALI_EXPERT is not set ++# CONFIG_MALI_KUTF is not set ++# end of ARM GPU Configuration ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++CONFIG_FB_SYS_FILLRECT=y ++CONFIG_FB_SYS_COPYAREA=y ++CONFIG_FB_SYS_IMAGEBLIT=y ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++CONFIG_FB_SYS_FOPS=y ++CONFIG_FB_DEFERRED_IO=y ++CONFIG_FB_MODE_HELPERS=y ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_CIRRUS is not set ++# CONFIG_FB_PM2 is not set ++# CONFIG_FB_ARMCLCD is not set ++# CONFIG_FB_CYBER2000 is not set ++# CONFIG_FB_ASILIANT is not set ++# CONFIG_FB_IMSTT is not set ++# CONFIG_FB_UVESA is not set ++CONFIG_FB_EFI=y ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_NVIDIA is not set ++# CONFIG_FB_RIVA is not set ++# CONFIG_FB_I740 is not set ++# CONFIG_FB_MATROX is not set ++# CONFIG_FB_RADEON is not set ++# CONFIG_FB_ATY128 is not set ++# CONFIG_FB_ATY is not set ++# CONFIG_FB_S3 is not set ++# CONFIG_FB_SAVAGE is not set ++# CONFIG_FB_SIS is not set ++# CONFIG_FB_NEOMAGIC is not set ++# CONFIG_FB_KYRO is not set ++# CONFIG_FB_3DFX is not set ++# CONFIG_FB_VOODOO1 is not set ++# CONFIG_FB_VT8623 is not set ++# CONFIG_FB_TRIDENT is not set ++# CONFIG_FB_ARK is not set ++# CONFIG_FB_PM3 is not set ++# CONFIG_FB_CARMINE is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_FB_SM712 is not set ++# end of Frame buffer Devices ++ ++# ++# Backlight & LCD device support ++# ++CONFIG_LCD_CLASS_DEVICE=m ++# CONFIG_LCD_L4F00242T03 is not set ++# CONFIG_LCD_LMS283GF05 is not set ++# CONFIG_LCD_LTV350QV is not set ++# CONFIG_LCD_ILI922X is not set ++# CONFIG_LCD_ILI9320 is not set ++# CONFIG_LCD_TDO24M is not set ++# CONFIG_LCD_VGG2432A4 is not set ++# CONFIG_LCD_PLATFORM is not set ++# CONFIG_LCD_AMS369FG06 is not set ++# CONFIG_LCD_LMS501KF03 is not set ++# CONFIG_LCD_HX8357 is not set ++# CONFIG_LCD_OTM3225A is not set ++CONFIG_BACKLIGHT_CLASS_DEVICE=y ++CONFIG_BACKLIGHT_GENERIC=y ++# CONFIG_BACKLIGHT_QCOM_WLED is not set ++# CONFIG_BACKLIGHT_ADP8860 is not set ++# CONFIG_BACKLIGHT_ADP8870 is not set ++# CONFIG_BACKLIGHT_LM3639 is not set ++# CONFIG_BACKLIGHT_GPIO is not set ++# CONFIG_BACKLIGHT_LV5207LP is not set ++# CONFIG_BACKLIGHT_BD6107 is not set ++# CONFIG_BACKLIGHT_ARCXCNN is not set ++# end of Backlight & LCD device support ++ ++CONFIG_VIDEOMODE_HELPERS=y ++CONFIG_HDMI=y ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_DUMMY_CONSOLE_COLUMNS=80 ++CONFIG_DUMMY_CONSOLE_ROWS=25 ++CONFIG_FRAMEBUFFER_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y ++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set ++# end of Console display driver support ++ ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++# end of Graphics support ++ ++CONFIG_SOUND=m ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SOUND_OSS_CORE_PRECLAIM=y ++CONFIG_SND=m ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++CONFIG_SND_DMAENGINE_PCM=m ++CONFIG_SND_HWDEP=m ++CONFIG_SND_SEQ_DEVICE=m ++CONFIG_SND_RAWMIDI=m ++CONFIG_SND_JACK=y ++CONFIG_SND_JACK_INPUT_DEV=y ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=m ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_PCM_OSS_PLUGINS=y ++CONFIG_SND_PCM_TIMER=y ++CONFIG_SND_HRTIMER=m ++CONFIG_SND_DYNAMIC_MINORS=y ++CONFIG_SND_MAX_CARDS=32 ++# CONFIG_SND_SUPPORT_OLD_API is not set ++CONFIG_SND_PROC_FS=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_VMASTER=y ++CONFIG_SND_SEQUENCER=m ++# CONFIG_SND_SEQ_DUMMY is not set ++CONFIG_SND_SEQUENCER_OSS=m ++CONFIG_SND_SEQ_HRTIMER_DEFAULT=y ++CONFIG_SND_SEQ_MIDI_EVENT=m ++CONFIG_SND_SEQ_MIDI=m ++CONFIG_SND_AC97_CODEC=m ++CONFIG_SND_DRIVERS=y ++CONFIG_SND_DUMMY=m ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_VIRMIDI is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++# CONFIG_SND_AC97_POWER_SAVE is not set ++# CONFIG_SND_PCI is not set ++ ++# ++# HD-Audio ++# ++# end of HD-Audio ++ ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++# CONFIG_SND_SPI is not set ++CONFIG_SND_USB=y ++CONFIG_SND_USB_AUDIO=m ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++# CONFIG_SND_USB_POD is not set ++# CONFIG_SND_USB_PODHD is not set ++# CONFIG_SND_USB_TONEPORT is not set ++# CONFIG_SND_USB_VARIAX is not set ++CONFIG_SND_SOC=m ++CONFIG_SND_SOC_AC97_BUS=y ++CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y ++# CONFIG_SND_SOC_AMD_ACP is not set ++# CONFIG_SND_ATMEL_SOC is not set ++CONFIG_SND_DESIGNWARE_I2S=m ++# CONFIG_SND_DESIGNWARE_PCM is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_AUDMIX is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_FSL_MICFIL is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++# end of SoC Audio for Freescale CPUs ++ ++# CONFIG_SND_I2S_HI6210_I2S is not set ++# CONFIG_SND_SOC_IMG is not set ++# CONFIG_SND_SOC_MTK_BTCVSD is not set ++# CONFIG_SND_SOC_SOF_TOPLEVEL is not set ++ ++# ++# STMicroelectronics STM32 SOC audio support ++# ++# end of STMicroelectronics STM32 SOC audio support ++ ++# CONFIG_SND_SOC_XILINX_I2S is not set ++# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set ++# CONFIG_SND_SOC_XILINX_SPDIF is not set ++# CONFIG_SND_SOC_XTFPGA_I2S is not set ++# CONFIG_ZX_TDM is not set ++CONFIG_SND_SOC_I2C_AND_SPI=m ++ ++# ++# CODEC drivers ++# ++CONFIG_SND_SOC_AC97_CODEC=m ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_ADAU1761_I2C is not set ++# CONFIG_SND_SOC_ADAU1761_SPI is not set ++# CONFIG_SND_SOC_ADAU7002 is not set ++# CONFIG_SND_SOC_ADAU7118_HW is not set ++# CONFIG_SND_SOC_ADAU7118_I2C is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4118 is not set ++# CONFIG_SND_SOC_AK4458 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4613 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_AK5558 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_BD28623 is not set ++# CONFIG_SND_SOC_BT_SCO is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS35L33 is not set ++# CONFIG_SND_SOC_CS35L34 is not set ++# CONFIG_SND_SOC_CS35L35 is not set ++# CONFIG_SND_SOC_CS35L36 is not set ++# CONFIG_SND_SOC_CS42L42 is not set ++# CONFIG_SND_SOC_CS42L51_I2C is not set ++# CONFIG_SND_SOC_CS42L52 is not set ++# CONFIG_SND_SOC_CS42L56 is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271_I2C is not set ++# CONFIG_SND_SOC_CS4271_SPI is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_CS43130 is not set ++# CONFIG_SND_SOC_CS4341 is not set ++# CONFIG_SND_SOC_CS4349 is not set ++# CONFIG_SND_SOC_CS53L30 is not set ++# CONFIG_SND_SOC_CX2072X is not set ++# CONFIG_SND_SOC_DA7213 is not set ++# CONFIG_SND_SOC_DMIC is not set ++# CONFIG_SND_SOC_ES7134 is not set ++# CONFIG_SND_SOC_ES7241 is not set ++# CONFIG_SND_SOC_ES8316 is not set ++# CONFIG_SND_SOC_ES8328_I2C is not set ++# CONFIG_SND_SOC_ES8328_SPI is not set ++# CONFIG_SND_SOC_GTM601 is not set ++# CONFIG_SND_SOC_INNO_RK3036 is not set ++# CONFIG_SND_SOC_MAX98088 is not set ++# CONFIG_SND_SOC_MAX98357A is not set ++# CONFIG_SND_SOC_MAX98504 is not set ++# CONFIG_SND_SOC_MAX9867 is not set ++# CONFIG_SND_SOC_MAX98927 is not set ++# CONFIG_SND_SOC_MAX98373 is not set ++# CONFIG_SND_SOC_MAX9860 is not set ++# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM1789_I2C is not set ++# CONFIG_SND_SOC_PCM179X_I2C is not set ++# CONFIG_SND_SOC_PCM179X_SPI is not set ++# CONFIG_SND_SOC_PCM186X_I2C is not set ++# CONFIG_SND_SOC_PCM186X_SPI is not set ++# CONFIG_SND_SOC_PCM3060_I2C is not set ++# CONFIG_SND_SOC_PCM3060_SPI is not set ++# CONFIG_SND_SOC_PCM3168A_I2C is not set ++# CONFIG_SND_SOC_PCM3168A_SPI is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_RK3328 is not set ++# CONFIG_SND_SOC_RT5616 is not set ++# CONFIG_SND_SOC_RT5631 is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++CONFIG_SND_SOC_SPDIF=m ++# CONFIG_SND_SOC_SSM2305 is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA32X is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_STI_SAS is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS2562 is not set ++# CONFIG_SND_SOC_TAS2770 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TAS571X is not set ++# CONFIG_SND_SOC_TAS5720 is not set ++# CONFIG_SND_SOC_TAS6424 is not set ++# CONFIG_SND_SOC_TDA7419 is not set ++# CONFIG_SND_SOC_TFA9879 is not set ++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set ++# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set ++CONFIG_SND_SOC_TLV320AIC3X=m ++# CONFIG_SND_SOC_TS3A227E is not set ++# CONFIG_SND_SOC_TSCS42XX is not set ++# CONFIG_SND_SOC_TSCS454 is not set ++# CONFIG_SND_SOC_UDA1334 is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8524 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8782 is not set ++# CONFIG_SND_SOC_WM8804_I2C is not set ++# CONFIG_SND_SOC_WM8804_SPI is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8904 is not set ++# CONFIG_SND_SOC_WM8960 is not set ++# CONFIG_SND_SOC_WM8962 is not set ++# CONFIG_SND_SOC_WM8974 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_WM8985 is not set ++# CONFIG_SND_SOC_ZX_AUD96P22 is not set ++# CONFIG_SND_SOC_MAX9759 is not set ++# CONFIG_SND_SOC_MT6351 is not set ++# CONFIG_SND_SOC_MT6358 is not set ++# CONFIG_SND_SOC_MT6660 is not set ++# CONFIG_SND_SOC_NAU8540 is not set ++# CONFIG_SND_SOC_NAU8810 is not set ++# CONFIG_SND_SOC_NAU8822 is not set ++# CONFIG_SND_SOC_NAU8824 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# end of CODEC drivers ++ ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SND_AUDIO_GRAPH_CARD is not set ++CONFIG_AC97_BUS=m ++ ++# ++# HID support ++# ++CONFIG_HID=y ++CONFIG_HID_BATTERY_STRENGTH=y ++CONFIG_HIDRAW=y ++CONFIG_UHID=m ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACCUTOUCH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BETOP_FF is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_COUGAR is not set ++# CONFIG_HID_MACALLY is not set ++# CONFIG_HID_PRODIKEYS is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CREATIVE_SB0540 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_VIEWSONIC is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_ITE is not set ++# CONFIG_HID_JABRA is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MALTRON is not set ++# CONFIG_HID_MAYFLASH is not set ++# CONFIG_HID_REDRAGON is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTI is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_RETRODE is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEAM is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_UDRAW_PS3 is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++# end of Special HID drivers ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=y ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y ++# end of USB HID support ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++# end of I2C HID support ++# end of HID support ++ ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ULPI_BUS=y ++# CONFIG_USB_CONN_GPIO is not set ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=y ++CONFIG_USB_PCI=y ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++CONFIG_USB_AUTOSUSPEND_DELAY=2 ++CONFIG_USB_MON=m ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_XHCI_HCD=y ++# CONFIG_USB_XHCI_DBGCAP is not set ++CONFIG_USB_XHCI_PCI=y ++CONFIG_USB_XHCI_PLATFORM=y ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++CONFIG_USB_EHCI_PCI=m ++# CONFIG_USB_EHCI_FSL is not set ++CONFIG_USB_EHCI_HCD_PLATFORM=m ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++CONFIG_USB_OHCI_HCD=m ++CONFIG_USB_OHCI_HCD_PCI=m ++CONFIG_USB_OHCI_HCD_PLATFORM=m ++# CONFIG_USB_UHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++CONFIG_USB_UAS=y ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_CDNS3 is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_ULPI=y ++CONFIG_USB_DWC3_HOST=y ++ ++# ++# Platform Glue Driver Support ++# ++CONFIG_USB_DWC3_HAPS=y ++CONFIG_USB_DWC3_OF_SIMPLE=y ++CONFIG_USB_DWC3_BAIKAL=y ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=m ++CONFIG_USB_SERIAL_GENERIC=y ++CONFIG_USB_SERIAL_SIMPLE=m ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++CONFIG_USB_SERIAL_CH341=m ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++CONFIG_USB_SERIAL_CP210X=m ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++CONFIG_USB_SERIAL_FTDI_SIO=m ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_F81232 is not set ++# CONFIG_USB_SERIAL_F8153X is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_METRO is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MXUPORT is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++CONFIG_USB_SERIAL_PL2303=m ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_QCAUX is not set ++# CONFIG_USB_SERIAL_QUALCOMM is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_SYMBOL is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++CONFIG_USB_SERIAL_WWAN=m ++CONFIG_USB_SERIAL_OPTION=m ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_OPTICON is not set ++# CONFIG_USB_SERIAL_XSENS_MT is not set ++# CONFIG_USB_SERIAL_WISHBONE is not set ++# CONFIG_USB_SERIAL_SSU100 is not set ++# CONFIG_USB_SERIAL_QT2 is not set ++# CONFIG_USB_SERIAL_UPD78F0730 is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HUB_USB251XB is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++# CONFIG_USB_CHAOSKEY is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++CONFIG_USB_ULPI=y ++CONFIG_USB_ULPI_VIEWPORT=y ++# end of USB Physical Layer drivers ++ ++# CONFIG_USB_GADGET is not set ++# CONFIG_TYPEC is not set ++# CONFIG_USB_ROLE_SWITCH is not set ++CONFIG_MMC=m ++CONFIG_PWRSEQ_EMMC=m ++CONFIG_PWRSEQ_SIMPLE=m ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_ARMMMCI is not set ++CONFIG_MMC_SDHCI=m ++# CONFIG_MMC_SDHCI_PCI is not set ++CONFIG_MMC_SDHCI_PLTFM=m ++CONFIG_MMC_SDHCI_OF_ARASAN=m ++# CONFIG_MMC_SDHCI_OF_ASPEED is not set ++CONFIG_MMC_SDHCI_OF_AT91=m ++CONFIG_MMC_SDHCI_OF_DWCMSHC=m ++# CONFIG_MMC_SDHCI_CADENCE is not set ++# CONFIG_MMC_SDHCI_F_SDH30 is not set ++# CONFIG_MMC_SDHCI_MILBEAUT is not set ++# CONFIG_MMC_TIFM_SD is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_CB710 is not set ++# CONFIG_MMC_VIA_SDMMC is not set ++# CONFIG_MMC_DW is not set ++CONFIG_MMC_VUB300=m ++CONFIG_MMC_USHC=m ++# CONFIG_MMC_USDHI6ROL0 is not set ++CONFIG_MMC_CQHCI=m ++# CONFIG_MMC_TOSHIBA_PCI is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MMC_SDHCI_XENON is not set ++# CONFIG_MMC_SDHCI_OMAP is not set ++# CONFIG_MMC_SDHCI_AM654 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++CONFIG_EDAC_SUPPORT=y ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++CONFIG_RTC_NVMEM=y ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++CONFIG_RTC_DRV_ABEOZ9=m ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_ISL12026 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF85363 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV3028 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++# CONFIG_RTC_DRV_SD3078 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++CONFIG_RTC_DRV_PCF2127=y ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_EFI is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_PL030 is not set ++# CONFIG_RTC_DRV_PL031 is not set ++# CONFIG_RTC_DRV_CADENCE is not set ++# CONFIG_RTC_DRV_FTRTC010 is not set ++# CONFIG_RTC_DRV_SNVS is not set ++# CONFIG_RTC_DRV_R7301 is not set ++ ++# ++# HID Sensor RTC drivers ++# ++CONFIG_DMADEVICES=y ++# CONFIG_DMADEVICES_DEBUG is not set ++ ++# ++# DMA Devices ++# ++CONFIG_DMA_ENGINE=y ++CONFIG_DMA_OF=y ++# CONFIG_ALTERA_MSGDMA is not set ++# CONFIG_AMBA_PL08X is not set ++# CONFIG_BCM_SBA_RAID is not set ++# CONFIG_DW_AXI_DMAC is not set ++# CONFIG_FSL_EDMA is not set ++# CONFIG_FSL_QDMA is not set ++# CONFIG_HISI_DMA is not set ++# CONFIG_INTEL_IDMA64 is not set ++# CONFIG_MV_XOR_V2 is not set ++# CONFIG_PL330_DMA is not set ++# CONFIG_PLX_DMA is not set ++# CONFIG_XILINX_DMA is not set ++# CONFIG_XILINX_ZYNQMP_DMA is not set ++# CONFIG_QCOM_HIDMA_MGMT is not set ++# CONFIG_QCOM_HIDMA is not set ++# CONFIG_DW_DMAC is not set ++# CONFIG_DW_DMAC_PCI is not set ++# CONFIG_DW_EDMA is not set ++# CONFIG_DW_EDMA_PCIE is not set ++# CONFIG_SF_PDMA is not set ++ ++# ++# DMA Clients ++# ++# CONFIG_ASYNC_TX_DMA is not set ++# CONFIG_DMATEST is not set ++ ++# ++# DMABUF options ++# ++CONFIG_SYNC_FILE=y ++# CONFIG_SW_SYNC is not set ++# CONFIG_UDMABUF is not set ++# CONFIG_DMABUF_SELFTESTS is not set ++# CONFIG_DMABUF_HEAPS is not set ++# end of DMABUF options ++ ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VFIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++# CONFIG_VIRTIO_MENU is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# end of Microsoft Hyper-V guest support ++ ++# CONFIG_GREYBUS is not set ++# CONFIG_STAGING is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_CHROME_PLATFORMS is not set ++# CONFIG_MELLANOX_PLATFORM is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++CONFIG_COMMON_CLK_VERSATILE=y ++# CONFIG_CLK_SP810 is not set ++# CONFIG_CLK_HSDK is not set ++# CONFIG_COMMON_CLK_MAX9485 is not set ++# CONFIG_COMMON_CLK_SI5341 is not set ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI544 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_XGENE is not set ++# CONFIG_COMMON_CLK_VC5 is not set ++# CONFIG_COMMON_CLK_FIXED_MMIO is not set ++# end of Common Clock Framework ++ ++# CONFIG_HWSPINLOCK is not set ++ ++# ++# Clock Source drivers ++# ++CONFIG_TIMER_OF=y ++CONFIG_TIMER_PROBE=y ++CONFIG_DW_APB_TIMER=y ++CONFIG_DW_APB_TIMER_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y ++# CONFIG_FSL_ERRATUM_A008585 is not set ++CONFIG_HISILICON_ERRATUM_161010101=y ++CONFIG_ARM64_ERRATUM_858921=y ++# CONFIG_MICROCHIP_PIT64B is not set ++# end of Clock Source drivers ++ ++CONFIG_MAILBOX=y ++CONFIG_ARM_MHU=m ++# CONFIG_PLATFORM_MHU is not set ++# CONFIG_PL320_MBOX is not set ++# CONFIG_ALTERA_MBOX is not set ++# CONFIG_MAILBOX_TEST is not set ++CONFIG_IOMMU_IOVA=y ++CONFIG_IOMMU_API=y ++CONFIG_IOMMU_SUPPORT=y ++ ++# ++# Generic IOMMU Pagetable Support ++# ++CONFIG_IOMMU_IO_PGTABLE=y ++CONFIG_IOMMU_IO_PGTABLE_LPAE=y ++# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set ++# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set ++# end of Generic IOMMU Pagetable Support ++ ++# CONFIG_IOMMU_DEBUGFS is not set ++# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set ++CONFIG_OF_IOMMU=y ++CONFIG_IOMMU_DMA=y ++CONFIG_ARM_SMMU=y ++# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set ++CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y ++CONFIG_ARM_SMMU_V3=y ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_REMOTEPROC is not set ++# end of Remoteproc drivers ++ ++# ++# Rpmsg drivers ++# ++# CONFIG_RPMSG_QCOM_GLINK_RPM is not set ++# CONFIG_RPMSG_VIRTIO is not set ++# end of Rpmsg drivers ++ ++# CONFIG_SOUNDWIRE is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Amlogic SoC drivers ++# ++# end of Amlogic SoC drivers ++ ++# ++# Aspeed SoC drivers ++# ++# end of Aspeed SoC drivers ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# end of Broadcom SoC drivers ++ ++# ++# NXP/Freescale QorIQ SoC drivers ++# ++# CONFIG_QUICC_ENGINE is not set ++# CONFIG_FSL_RCPM is not set ++# end of NXP/Freescale QorIQ SoC drivers ++ ++# ++# i.MX SoC drivers ++# ++# end of i.MX SoC drivers ++ ++# ++# Qualcomm SoC drivers ++# ++# end of Qualcomm SoC drivers ++ ++# CONFIG_SOC_TI is not set ++ ++# ++# Xilinx SoC drivers ++# ++# CONFIG_XILINX_VCU is not set ++# end of Xilinx SoC drivers ++# end of SOC (System On Chip) specific Drivers ++ ++CONFIG_PM_DEVFREQ=y ++ ++# ++# DEVFREQ Governors ++# ++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m ++# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set ++# CONFIG_DEVFREQ_GOV_POWERSAVE is not set ++# CONFIG_DEVFREQ_GOV_USERSPACE is not set ++# CONFIG_DEVFREQ_GOV_PASSIVE is not set ++ ++# ++# DEVFREQ Drivers ++# ++# CONFIG_PM_DEVFREQ_EVENT is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_NTB is not set ++# CONFIG_VME_BUS is not set ++# CONFIG_PWM is not set ++ ++# ++# IRQ chip support ++# ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++CONFIG_ARM_GIC_V2M=y ++CONFIG_ARM_GIC_V3=y ++CONFIG_ARM_GIC_V3_ITS=y ++CONFIG_ARM_GIC_V3_ITS_PCI=y ++# CONFIG_AL_FIC is not set ++CONFIG_PARTITION_PERCPU=y ++# end of IRQ chip support ++ ++# CONFIG_IPACK_BUS is not set ++CONFIG_RESET_CONTROLLER=y ++# CONFIG_RESET_BRCMSTB_RESCAL is not set ++# CONFIG_RESET_INTEL_GW is not set ++# CONFIG_RESET_TI_SYSCON is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_PHY_XGENE is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_PHY_CADENCE_DP is not set ++# CONFIG_PHY_CADENCE_DPHY is not set ++# CONFIG_PHY_CADENCE_SIERRA is not set ++# CONFIG_PHY_FSL_IMX8MQ_USB is not set ++# CONFIG_PHY_MIXEL_MIPI_DPHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_PHY_MAPPHONE_MDM6600 is not set ++# CONFIG_PHY_OCELOT_SERDES is not set ++# CONFIG_PHY_QCOM_USB_HS is not set ++# CONFIG_PHY_QCOM_USB_HSIC is not set ++# CONFIG_PHY_TUSB1210 is not set ++# CONFIG_PHY_INTEL_EMMC is not set ++# end of PHY Subsystem ++ ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++# CONFIG_ARM_CCI_PMU is not set ++# CONFIG_ARM_CCN is not set ++CONFIG_ARM_PMU=y ++# CONFIG_ARM_DSU_PMU is not set ++# CONFIG_ARM_SPE_PMU is not set ++# end of Performance monitor support ++ ++CONFIG_RAS=y ++ ++# ++# Android ++# ++# CONFIG_ANDROID is not set ++# end of Android ++ ++# CONFIG_LIBNVDIMM is not set ++# CONFIG_DAX is not set ++CONFIG_NVMEM=y ++CONFIG_NVMEM_SYSFS=y ++ ++# ++# HW tracing support ++# ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++# end of HW tracing support ++ ++# CONFIG_FPGA is not set ++# CONFIG_FSI is not set ++# CONFIG_TEE is not set ++CONFIG_PM_OPP=y ++# CONFIG_SIOX is not set ++# CONFIG_SLIMBUS is not set ++# CONFIG_INTERCONNECT is not set ++# CONFIG_COUNTER is not set ++# end of Device Drivers ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_VALIDATE_FS_PARSER is not set ++CONFIG_FS_IOMAP=y ++# CONFIG_EXT2_FS is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_USE_FOR_EXT2=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++# CONFIG_EXT4_DEBUG is not set ++CONFIG_JBD2=y ++# CONFIG_JBD2_DEBUG is not set ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++# CONFIG_FS_DAX is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_EXPORTFS=y ++CONFIG_EXPORTFS_BLOCK_OPS=y ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++# CONFIG_FS_VERITY is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++CONFIG_FANOTIFY=y ++CONFIG_QUOTA=y ++CONFIG_QUOTA_NETLINK_INTERFACE=y ++CONFIG_PRINT_QUOTA_WARNING=y ++# CONFIG_QUOTA_DEBUG is not set ++CONFIG_QUOTA_TREE=m ++CONFIG_QFMT_V1=m ++CONFIG_QFMT_V2=m ++CONFIG_QUOTACTL=y ++CONFIG_AUTOFS4_FS=y ++CONFIG_AUTOFS_FS=y ++CONFIG_FUSE_FS=m ++# CONFIG_CUSE is not set ++# CONFIG_VIRTIO_FS is not set ++CONFIG_OVERLAY_FS=y ++# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set ++CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y ++# CONFIG_OVERLAY_FS_INDEX is not set ++# CONFIG_OVERLAY_FS_XINO_AUTO is not set ++# CONFIG_OVERLAY_FS_METACOPY is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++# end of Caches ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=y ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_UDF_FS=y ++# end of CD-ROM/DVD Filesystems ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=866 ++CONFIG_FAT_DEFAULT_IOCHARSET="utf8" ++CONFIG_FAT_DEFAULT_UTF8=y ++# CONFIG_NTFS_FS is not set ++# end of DOS/FAT/NT Filesystems ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_KCORE=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++CONFIG_HUGETLBFS=y ++CONFIG_HUGETLB_PAGE=y ++CONFIG_MEMFD_CREATE=y ++CONFIG_ARCH_HAS_GIGANTIC_PAGE=y ++CONFIG_CONFIGFS_FS=m ++CONFIG_EFIVAR_FS=m ++# end of Pseudo filesystems ++ ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_ECRYPT_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_JFFS2_FS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++CONFIG_SQUASHFS_FILE_CACHE=y ++# CONFIG_SQUASHFS_FILE_DIRECT is not set ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++CONFIG_SQUASHFS_XATTR=y ++CONFIG_SQUASHFS_ZLIB=y ++CONFIG_SQUASHFS_LZ4=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++# CONFIG_SQUASHFS_ZSTD is not set ++# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set ++# CONFIG_SQUASHFS_EMBEDDED is not set ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++CONFIG_PSTORE=y ++CONFIG_PSTORE_DEFLATE_COMPRESS=y ++# CONFIG_PSTORE_LZO_COMPRESS is not set ++# CONFIG_PSTORE_LZ4_COMPRESS is not set ++# CONFIG_PSTORE_LZ4HC_COMPRESS is not set ++# CONFIG_PSTORE_842_COMPRESS is not set ++# CONFIG_PSTORE_ZSTD_COMPRESS is not set ++CONFIG_PSTORE_COMPRESS=y ++CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y ++CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" ++# CONFIG_PSTORE_CONSOLE is not set ++# CONFIG_PSTORE_PMSG is not set ++# CONFIG_PSTORE_FTRACE is not set ++# CONFIG_PSTORE_RAM is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++# CONFIG_EROFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V3=m ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=m ++# CONFIG_NFS_SWAP is not set ++CONFIG_NFS_V4_1=y ++CONFIG_NFS_V4_2=y ++CONFIG_PNFS_FILE_LAYOUT=m ++CONFIG_PNFS_BLOCK=m ++CONFIG_PNFS_FLEXFILE_LAYOUT=m ++CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" ++CONFIG_NFS_V4_1_MIGRATION=y ++# CONFIG_NFS_USE_LEGACY_DNS is not set ++CONFIG_NFS_USE_KERNEL_DNS=y ++# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set ++# CONFIG_NFS_V4_2_READ_PLUS is not set ++CONFIG_NFSD=m ++CONFIG_NFSD_V2_ACL=y ++CONFIG_NFSD_V3=y ++CONFIG_NFSD_V3_ACL=y ++CONFIG_NFSD_V4=y ++CONFIG_NFSD_PNFS=y ++CONFIG_NFSD_BLOCKLAYOUT=y ++CONFIG_NFSD_SCSILAYOUT=y ++# CONFIG_NFSD_FLEXFILELAYOUT is not set ++CONFIG_NFSD_V4_2_INTER_SSC=y ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++CONFIG_SUNRPC_GSS=m ++CONFIG_SUNRPC_BACKCHANNEL=y ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS2 is not set ++CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y ++CONFIG_CIFS_WEAK_PW_HASH=y ++CONFIG_CIFS_UPCALL=y ++CONFIG_CIFS_XATTR=y ++CONFIG_CIFS_POSIX=y ++CONFIG_CIFS_DEBUG=y ++# CONFIG_CIFS_DEBUG2 is not set ++# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set ++CONFIG_CIFS_DFS_UPCALL=y ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="utf8" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++CONFIG_NLS_CODEPAGE_866=y ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++# CONFIG_UNICODE is not set ++CONFIG_IO_WQ=y ++# end of File systems ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++# CONFIG_KEYS_REQUEST_CACHE is not set ++CONFIG_PERSISTENT_KEYRINGS=y ++CONFIG_BIG_KEYS=y ++# CONFIG_ENCRYPTED_KEYS is not set ++# CONFIG_KEY_DH_OPERATIONS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++# CONFIG_HARDENED_USERCOPY is not set ++# CONFIG_FORTIFY_SOURCE is not set ++# CONFIG_STATIC_USERMODEHELPER is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" ++ ++# ++# Kernel hardening options ++# ++ ++# ++# Memory initialization ++# ++CONFIG_INIT_STACK_NONE=y ++# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set ++# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set ++# end of Memory initialization ++# end of Kernel hardening options ++# end of Security options ++ ++CONFIG_XOR_BLOCKS=m ++CONFIG_ASYNC_CORE=m ++CONFIG_ASYNC_MEMCPY=m ++CONFIG_ASYNC_XOR=m ++CONFIG_ASYNC_PQ=m ++CONFIG_ASYNC_RAID6_RECOV=m ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_SKCIPHER=y ++CONFIG_CRYPTO_SKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++CONFIG_CRYPTO_ACOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++CONFIG_CRYPTO_GF128MUL=y ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=m ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Public-key cryptography ++# ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++# CONFIG_CRYPTO_ECRDSA is not set ++# CONFIG_CRYPTO_CURVE25519 is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++CONFIG_CRYPTO_GCM=y ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++# CONFIG_CRYPTO_AEGIS128 is not set ++CONFIG_CRYPTO_SEQIV=y ++# CONFIG_CRYPTO_ECHAINIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CFB is not set ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_OFB is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++# CONFIG_CRYPTO_ADIANTUM is not set ++CONFIG_CRYPTO_ESSIV=m ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++CONFIG_CRYPTO_CRC32=m ++# CONFIG_CRYPTO_XXHASH is not set ++# CONFIG_CRYPTO_BLAKE2B is not set ++# CONFIG_CRYPTO_BLAKE2S is not set ++CONFIG_CRYPTO_CRCT10DIF=y ++CONFIG_CRYPTO_GHASH=y ++# CONFIG_CRYPTO_POLY1305 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=m ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_SM3 is not set ++# CONFIG_CRYPTO_STREEBOG is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_TI is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_SM4 is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++# CONFIG_CRYPTO_ZSTD is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++ ++# ++# Crypto library routines ++# ++CONFIG_CRYPTO_LIB_AES=y ++CONFIG_CRYPTO_LIB_ARC4=m ++# CONFIG_CRYPTO_LIB_BLAKE2S is not set ++# CONFIG_CRYPTO_LIB_CHACHA is not set ++# CONFIG_CRYPTO_LIB_CURVE25519 is not set ++CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 ++# CONFIG_CRYPTO_LIB_POLY1305 is not set ++# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_LIB_SHA256=y ++# CONFIG_CRYPTO_HW is not set ++# CONFIG_ASYMMETRIC_KEY_TYPE is not set ++ ++# ++# Certificates for signature checking ++# ++# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set ++# end of Certificates for signature checking ++ ++CONFIG_BINARY_PRINTF=y ++ ++# ++# Library routines ++# ++CONFIG_RAID6_PQ=m ++CONFIG_RAID6_PQ_BENCHMARK=y ++# CONFIG_PACKING is not set ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++# CONFIG_CORDIC is not set ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++CONFIG_ARCH_HAS_FAST_MULTIPLIER=y ++# CONFIG_INDIRECT_PIO is not set ++CONFIG_CRC_CCITT=m ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC64 is not set ++# CONFIG_CRC4 is not set ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=m ++# CONFIG_CRC8 is not set ++CONFIG_XXHASH=y ++CONFIG_AUDIT_GENERIC=y ++CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y ++CONFIG_AUDIT_COMPAT_GENERIC=y ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_LZ4_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++CONFIG_XZ_DEC_X86=y ++CONFIG_XZ_DEC_POWERPC=y ++CONFIG_XZ_DEC_IA64=y ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++CONFIG_XZ_DEC_SPARC=y ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_DECOMPRESS_LZMA=y ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_DECOMPRESS_LZO=y ++CONFIG_DECOMPRESS_LZ4=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_XARRAY_MULTI=y ++CONFIG_ASSOCIATIVE_ARRAY=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_NEED_SG_DMA_LENGTH=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_DMA_ADDR_T_64BIT=y ++CONFIG_DMA_DECLARE_COHERENT=y ++CONFIG_ARCH_HAS_SETUP_DMA_OPS=y ++CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y ++CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y ++CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y ++CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y ++CONFIG_SWIOTLB=y ++CONFIG_DMA_NONCOHERENT_MMAP=y ++CONFIG_DMA_REMAP=y ++CONFIG_DMA_DIRECT_REMAP=y ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=256 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=8 ++# CONFIG_DMA_API_DEBUG is not set ++CONFIG_SGL_ALLOC=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++CONFIG_IRQ_POLL=y ++CONFIG_LIBFDT=y ++CONFIG_UCS2_STRING=y ++CONFIG_HAVE_GENERIC_VDSO=y ++CONFIG_GENERIC_GETTIMEOFDAY=y ++CONFIG_FONT_SUPPORT=y ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_SG_POOL=y ++CONFIG_SBITMAP=y ++# CONFIG_STRING_SELFTEST is not set ++# end of Library routines ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++CONFIG_PRINTK_TIME=y ++# CONFIG_PRINTK_CALLER is not set ++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 ++CONFIG_CONSOLE_LOGLEVEL_QUIET=4 ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_DYNAMIC_DEBUG=y ++CONFIG_SYMBOLIC_ERRNAME=y ++CONFIG_DEBUG_BUGVERBOSE=y ++# end of printk and dmesg options ++ ++# ++# Compile-time checks and compiler options ++# ++# CONFIG_DEBUG_INFO is not set ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=2048 ++CONFIG_STRIP_ASM_SYMS=y ++# CONFIG_READABLE_ASM is not set ++# CONFIG_HEADERS_INSTALL is not set ++CONFIG_OPTIMIZE_INLINING=y ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++CONFIG_ARCH_WANT_FRAME_POINTERS=y ++CONFIG_FRAME_POINTER=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# end of Compile-time checks and compiler options ++ ++# ++# Generic Kernel Debugging Instruments ++# ++CONFIG_MAGIC_SYSRQ=y ++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x01b6 ++CONFIG_MAGIC_SYSRQ_SERIAL=y ++CONFIG_DEBUG_FS=y ++CONFIG_HAVE_ARCH_KGDB=y ++CONFIG_KGDB=y ++CONFIG_KGDB_SERIAL_CONSOLE=y ++# CONFIG_KGDB_TESTS is not set ++CONFIG_KGDB_KDB=y ++CONFIG_KDB_DEFAULT_ENABLE=0x1 ++# CONFIG_KDB_KEYBOARD is not set ++CONFIG_KDB_CONTINUE_CATASTROPHIC=0 ++CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y ++# CONFIG_UBSAN is not set ++CONFIG_UBSAN_ALIGNMENT=y ++# end of Generic Kernel Debugging Instruments ++ ++CONFIG_DEBUG_KERNEL=y ++CONFIG_DEBUG_MISC=y ++ ++# ++# Memory Debugging ++# ++CONFIG_PAGE_EXTENSION=y ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_PAGE_POISONING=y ++CONFIG_PAGE_POISONING_NO_SANITY=y ++# CONFIG_PAGE_POISONING_ZERO is not set ++# CONFIG_DEBUG_PAGE_REF is not set ++# CONFIG_DEBUG_RODATA_TEST is not set ++CONFIG_GENERIC_PTDUMP=y ++# CONFIG_PTDUMP_DEBUGFS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_DEBUG_SLAB is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_SCHED_STACK_END_CHECK=y ++# CONFIG_DEBUG_VM is not set ++CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y ++# CONFIG_DEBUG_VIRTUAL is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++CONFIG_HAVE_ARCH_KASAN=y ++CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y ++CONFIG_CC_HAS_KASAN_GENERIC=y ++# CONFIG_KASAN is not set ++CONFIG_KASAN_STACK=1 ++# end of Memory Debugging ++ ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Oops, Lockups and Hangs ++# ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++CONFIG_LOCKUP_DETECTOR=y ++CONFIG_SOFTLOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 ++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set ++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 ++CONFIG_WQ_WATCHDOG=y ++# end of Debug Oops, Lockups and Hangs ++ ++# ++# Scheduler Debugging ++# ++CONFIG_SCHED_DEBUG=y ++CONFIG_SCHED_INFO=y ++CONFIG_SCHEDSTATS=y ++# end of Scheduler Debugging ++ ++# CONFIG_DEBUG_TIMEKEEPING is not set ++CONFIG_DEBUG_PREEMPT=y ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_LOCK_DEBUGGING_SUPPORT=y ++CONFIG_PROVE_LOCKING=y ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y ++CONFIG_DEBUG_RWSEMS=y ++CONFIG_DEBUG_LOCK_ALLOC=y ++CONFIG_LOCKDEP=y ++# CONFIG_DEBUG_LOCKDEP is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_WW_MUTEX_SELFTEST is not set ++# end of Lock Debugging (spinlocks, mutexes, etc...) ++ ++CONFIG_TRACE_IRQFLAGS=y ++CONFIG_STACKTRACE=y ++# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_HAVE_DEBUG_BUGVERBOSE=y ++ ++# ++# Debug kernel data structures ++# ++CONFIG_DEBUG_LIST=y ++# CONFIG_DEBUG_PLIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_BUG_ON_DATA_CORRUPTION is not set ++# end of Debug kernel data structures ++ ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++CONFIG_PROVE_RCU=y ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_TRACE is not set ++# CONFIG_RCU_EQS_DEBUG is not set ++# end of RCU Debugging ++ ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++CONFIG_LATENCYTOP=y ++CONFIG_NOP_TRACER=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACER_MAX_TRACE=y ++CONFIG_TRACE_CLOCK=y ++CONFIG_RING_BUFFER=y ++CONFIG_EVENT_TRACING=y ++CONFIG_CONTEXT_SWITCH_TRACER=y ++CONFIG_RING_BUFFER_ALLOW_SWAP=y ++CONFIG_PREEMPTIRQ_TRACEPOINTS=y ++CONFIG_TRACING=y ++CONFIG_GENERIC_TRACER=y ++CONFIG_TRACING_SUPPORT=y ++CONFIG_FTRACE=y ++# CONFIG_BOOTTIME_TRACING is not set ++CONFIG_FUNCTION_TRACER=y ++CONFIG_FUNCTION_GRAPH_TRACER=y ++CONFIG_DYNAMIC_FTRACE=y ++# CONFIG_FUNCTION_PROFILER is not set ++CONFIG_STACK_TRACER=y ++# CONFIG_PREEMPTIRQ_EVENTS is not set ++CONFIG_IRQSOFF_TRACER=y ++# CONFIG_PREEMPT_TRACER is not set ++CONFIG_SCHED_TRACER=y ++CONFIG_HWLAT_TRACER=y ++CONFIG_FTRACE_SYSCALLS=y ++CONFIG_TRACER_SNAPSHOT=y ++CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y ++CONFIG_BRANCH_PROFILE_NONE=y ++# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set ++# CONFIG_PROFILE_ALL_BRANCHES is not set ++CONFIG_BLK_DEV_IO_TRACE=y ++CONFIG_KPROBE_EVENTS=y ++CONFIG_UPROBE_EVENTS=y ++CONFIG_BPF_EVENTS=y ++CONFIG_DYNAMIC_EVENTS=y ++CONFIG_PROBE_EVENTS=y ++# CONFIG_BPF_KPROBE_OVERRIDE is not set ++CONFIG_FTRACE_MCOUNT_RECORD=y ++# CONFIG_HIST_TRIGGERS is not set ++# CONFIG_TRACE_EVENT_INJECT is not set ++# CONFIG_TRACEPOINT_BENCHMARK is not set ++# CONFIG_RING_BUFFER_BENCHMARK is not set ++# CONFIG_TRACE_EVAL_MAP_FILE is not set ++# CONFIG_FTRACE_STARTUP_TEST is not set ++# CONFIG_RING_BUFFER_STARTUP_TEST is not set ++# CONFIG_PREEMPTIRQ_DELAY_TEST is not set ++# CONFIG_KPROBE_EVENT_GEN_TEST is not set ++# CONFIG_SAMPLES is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++CONFIG_STRICT_DEVMEM=y ++CONFIG_IO_STRICT_DEVMEM=y ++ ++# ++# arm64 Debugging ++# ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set ++# CONFIG_DEBUG_WX is not set ++# CONFIG_DEBUG_ALIGN_RODATA is not set ++# CONFIG_ARM64_RELOC_TEST is not set ++# CONFIG_CORESIGHT is not set ++# end of arm64 Debugging ++ ++# ++# Kernel Testing and Coverage ++# ++# CONFIG_KUNIT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++CONFIG_FUNCTION_ERROR_INJECTION=y ++# CONFIG_FAULT_INJECTION is not set ++CONFIG_ARCH_HAS_KCOV=y ++CONFIG_CC_HAS_SANCOV_TRACE_PC=y ++# CONFIG_KCOV is not set ++# CONFIG_RUNTIME_TESTING_MENU is not set ++# CONFIG_MEMTEST is not set ++# end of Kernel Testing and Coverage ++# end of Kernel hacking +diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig +index 7e693dcbdd19..986c569dade0 100644 +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -545,7 +545,7 @@ config I2C_DESIGNWARE_PLATFORM + tristate "Synopsys DesignWare Platform" + depends on (ACPI && COMMON_CLK) || !ACPI + select I2C_DESIGNWARE_CORE +- select MFD_SYSCON if MIPS_BAIKAL_T1 ++ select MFD_SYSCON if MIPS_BAIKAL_T1 || ARCH_BAIKAL + help + If you say yes to this option, support will be included for the + Synopsys DesignWare I2C adapter. +-- +2.31.1 + diff --git a/0602-Baikal-M-clock-driver.patch b/0602-Baikal-M-clock-driver.patch new file mode 100644 index 0000000..84c465a --- /dev/null +++ b/0602-Baikal-M-clock-driver.patch @@ -0,0 +1,502 @@ +From 2e8241aba5add6f768a0876bc11c989681e28817 Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Fri, 20 Mar 2020 13:55:42 +0400 +Subject: [PATCH 602/625] Baikal-M: clock driver + +(cherry picked from commit acf15020f93d3be658922bb46ee9b4eb84497494) +--- + drivers/clk/Makefile | 1 + + drivers/clk/baikal/Makefile | 1 + + drivers/clk/baikal/clk-baikal.c | 459 ++++++++++++++++++++++++++++++++ + 3 files changed, 461 insertions(+) + create mode 100644 drivers/clk/baikal/Makefile + create mode 100644 drivers/clk/baikal/clk-baikal.c + +diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile +index da8fcf147eb1..ab785aca5c8e 100644 +--- a/drivers/clk/Makefile ++++ b/drivers/clk/Makefile +@@ -77,6 +77,7 @@ obj-$(CONFIG_COMMON_CLK_AT91) += at91/ + obj-$(CONFIG_ARCH_ARTPEC) += axis/ + obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ + obj-$(CONFIG_CLK_BAIKAL_T1) += baikal-t1/ ++obj-$(CONFIG_ARCH_BAIKAL) += baikal/ + obj-y += bcm/ + obj-$(CONFIG_ARCH_BERLIN) += berlin/ + obj-$(CONFIG_ARCH_DAVINCI) += davinci/ +diff --git a/drivers/clk/baikal/Makefile b/drivers/clk/baikal/Makefile +new file mode 100644 +index 000000000000..56aa4de4081c +--- /dev/null ++++ b/drivers/clk/baikal/Makefile +@@ -0,0 +1 @@ ++obj-y += clk-baikal.o +\ No newline at end of file +diff --git a/drivers/clk/baikal/clk-baikal.c b/drivers/clk/baikal/clk-baikal.c +new file mode 100644 +index 000000000000..ddf1d328eeaf +--- /dev/null ++++ b/drivers/clk/baikal/clk-baikal.c +@@ -0,0 +1,459 @@ ++/* ++ * clk-baikal.c - Baikal Electronics clock driver. ++ * ++ * Copyright (C) 2015,2016 Baikal Electronics JSC ++ * ++ * Author: ++ * Ekaterina Skachko ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define CMU_PLL_SET_RATE 0 ++#define CMU_PLL_GET_RATE 1 ++#define CMU_PLL_ENABLE 2 ++#define CMU_PLL_DISABLE 3 ++#define CMU_PLL_ROUND_RATE 4 ++#define CMU_PLL_IS_ENABLED 5 ++#define CMU_CLK_CH_SET_RATE 6 ++#define CMU_CLK_CH_GET_RATE 7 ++#define CMU_CLK_CH_ENABLE 8 ++#define CMU_CLK_CH_DISABLE 9 ++#define CMU_CLK_CH_ROUND_RATE 10 ++#define CMU_CLK_CH_IS_ENABLED 11 ++ ++ ++struct baikal_clk_cmu { ++ struct clk_hw hw; ++ uint32_t cmu_id; ++ unsigned int parent; ++ const char *name; ++ spinlock_t *lock; ++ void __iomem *reg; ++ unsigned int latency; /* ns */ ++ unsigned int min, max, step; ++ unsigned int clk_ch_num; ++ uint32_t is_clk_ch; ++}; ++ ++#define to_baikal_cmu(_hw) container_of(_hw, struct baikal_clk_cmu, hw) ++ ++/* Pointer to the place on handling SMC CMU calls in monitor */ ++#define BAIKAL_SMC_LCRU_ID 0x82000000 ++ ++static int baikal_clk_enable(struct clk_hw *hw) ++{ ++ struct arm_smccc_res res; ++ struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); ++ uint32_t cmd; ++ ++ if (pclk->is_clk_ch){ ++ cmd = CMU_CLK_CH_ENABLE; ++ } ++ else { ++ cmd = CMU_PLL_ENABLE; ++ } ++ ++ pr_debug("[%s, %x:%d:%s] %s\n", ++ pclk->name, ++ pclk->parent, ++ pclk->cmu_id, ++ pclk->is_clk_ch?"ch":"pll", ++ "enable"); ++ ++ /* If clock valid */ ++ arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, 0, ++ pclk->parent, 0, 0, 0, &res); ++ ++ return res.a0; ++} ++ ++static void baikal_clk_disable(struct clk_hw *hw) ++{ ++ ++ struct arm_smccc_res res; ++ struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); ++ uint32_t cmd; ++ ++ if (pclk->is_clk_ch) ++ cmd = CMU_CLK_CH_DISABLE; ++ else ++ cmd = CMU_PLL_DISABLE; ++ ++ pr_debug("[%s, %x:%d:%s] %s\n", ++ pclk->name, ++ pclk->parent, ++ pclk->cmu_id, ++ pclk->is_clk_ch?"ch":"pll", ++ "disable"); ++ ++ /* If clock valid */ ++ arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, 0, ++ pclk->parent, 0, 0, 0, &res); ++} ++ ++static int baikal_clk_is_enabled(struct clk_hw *hw) ++{ ++ struct arm_smccc_res res; ++ struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); ++ uint32_t cmd; ++ ++ if (pclk->is_clk_ch) ++ cmd = CMU_CLK_CH_IS_ENABLED; ++ else ++ cmd = CMU_PLL_IS_ENABLED; ++ ++ /* If clock valid */ ++ arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, 0, ++ pclk->parent, 0, 0, 0, &res); ++ ++ pr_debug("[%s, %x:%d:%s] %s, %ld\n", ++ pclk->name, ++ pclk->parent, ++ pclk->cmu_id, ++ pclk->is_clk_ch?"ch":"pll", ++ "is enable", ++ res.a0); ++ ++ return res.a0; ++} ++ ++static unsigned long baikal_clk_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct arm_smccc_res res; ++ struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); ++ uint32_t cmd; ++ unsigned long parent; ++ ++ if (pclk->is_clk_ch) { ++ cmd = CMU_CLK_CH_GET_RATE; ++ parent = pclk->parent; ++ } else { ++ cmd = CMU_PLL_GET_RATE; ++ parent= parent_rate; ++ } ++ ++ /* If clock valid */ ++ arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, 0, ++ parent, 0, 0, 0, &res); ++ ++ pr_debug("[%s, %x:%d:%s] %s, %ld\n", ++ pclk->name, ++ parent, ++ pclk->cmu_id, ++ pclk->is_clk_ch?"ch":"pll", ++ "get rate", ++ res.a0); ++ ++ /* Return actual freq */ ++ return res.a0; ++ ++} ++ ++static int baikal_clk_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct arm_smccc_res res; ++ struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); ++ uint32_t cmd; ++ ++ if (pclk->is_clk_ch) ++ cmd = CMU_CLK_CH_SET_RATE; ++ else ++ cmd = CMU_PLL_SET_RATE; ++ ++ pr_debug("[%s, %x:%d:%s] %s, %ld\n", ++ pclk->name, ++ pclk->parent, ++ pclk->cmu_id, ++ pclk->is_clk_ch?"ch":"pll", ++ "set rate", ++ rate); ++ ++ arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, rate, ++ pclk->parent, 0, 0, 0, &res); ++ ++ return res.a0; ++} ++ ++static long baikal_clk_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *prate) ++{ ++ struct arm_smccc_res res; ++ struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); ++ unsigned long parent; ++ uint32_t cmd; ++ ++ if (pclk->is_clk_ch) { ++ cmd = CMU_CLK_CH_ROUND_RATE; ++ parent = pclk->parent; ++ } else { ++ cmd = CMU_PLL_ROUND_RATE; ++ parent = *prate; ++ } ++ ++ ++ /* If clock valid */ ++ arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, rate, ++ parent, 0, 0, 0, &res); ++ ++ pr_debug("[%s, %x:%d:%s] %s, %ld\n", ++ pclk->name, ++ pclk->parent, ++ pclk->cmu_id, ++ pclk->is_clk_ch?"ch":"pll", ++ "round rate", ++ res.a0); ++ ++ /* Return actual freq */ ++ return res.a0; ++} ++ ++const struct clk_ops be_clk_pll_ops = { ++ .enable = baikal_clk_enable, ++ .disable = baikal_clk_disable, ++ .is_enabled = baikal_clk_is_enabled, ++ .recalc_rate = baikal_clk_recalc_rate, ++ .set_rate = baikal_clk_set_rate, ++ .round_rate = baikal_clk_round_rate, ++}; ++ ++ ++ ++static int baikal_clk_probe(struct platform_device *pdev) ++{ ++ struct clk_init_data init; ++ struct clk_init_data *init_ch; ++ struct baikal_clk_cmu *cmu; ++ struct baikal_clk_cmu **cmu_ch; ++ struct device_node *node = pdev->dev.of_node; ++ ++ struct clk *clk; ++ struct clk_onecell_data *clk_ch; ++ ++ int number, i = 0; ++ u32 rc, index; ++ struct property *prop; ++ const __be32 *p; ++ const char *clk_ch_name; ++ const char *parent_name; ++ ++ cmu = kmalloc(sizeof(struct baikal_clk_cmu *), GFP_KERNEL); ++ if (!cmu) { ++ /* Error */ ++ pr_err("%s: could not allocate CMU clk\n", __func__); ++ kfree(cmu); ++ return -ENOMEM; ++ } ++ ++ of_property_read_string(node, "clock-output-names", &cmu->name); ++ parent_name = of_clk_get_parent_name(node, 0); ++ init.parent_names = &parent_name; ++ init.num_parents = 1; ++ of_property_read_u32(node, "clock-frequency", &cmu->parent); ++ of_property_read_u32(node, "cmu-id", &cmu->cmu_id); ++ ++ /* Setup clock init structure */ ++ init.name = cmu->name; ++ init.ops = &be_clk_pll_ops; ++ init.flags = CLK_IGNORE_UNUSED; ++ ++ cmu->hw.init = &init; ++ cmu->is_clk_ch = 0; ++ ++ /* Register the clock */ ++ pr_debug("Add %s clock\n", cmu->name); ++ clk = clk_register(NULL, &cmu->hw); ++ ++ if (IS_ERR(clk)) { ++ /* Error */ ++ pr_err("%s: could not register clk %s\n", __func__, cmu->name); ++ return -ENOMEM; ++ } ++ ++ /* Register the clock for lookup */ ++ rc = clk_register_clkdev(clk, cmu->name, NULL); ++ if (rc != 0) { ++ /* Error */ ++ pr_err("%s: could not register lookup clk %s\n", ++ __func__, cmu->name); ++ } ++ ++ /* FIXME We probably SHOULDN'T enable it here */ ++ clk_prepare_enable(clk); ++ ++ number = of_property_count_u32_elems(node, "clock-indices"); ++ ++ if (number > 0) { ++ clk_ch = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); ++ if (!clk_ch) { ++ /* Error */ ++ pr_err("%s: could not allocate CMU clk channel\n", __func__); ++ kfree(clk_ch); ++ return -ENOMEM; ++ } ++ /* Get the last index to find out max number of children*/ ++ of_property_for_each_u32(node, "clock-indices", prop, p, index) { ++ ; ++ } ++ clk_ch->clks = kcalloc(index + 1, sizeof(struct clk *), GFP_KERNEL); ++ clk_ch->clk_num = index + 1; ++ cmu_ch = kcalloc((index + 1 ), sizeof(struct baikal_clk_cmu *), GFP_KERNEL); ++ if (!cmu_ch) { ++ kfree(cmu_ch); ++ kfree(clk_ch); ++ return -ENOMEM; ++ } ++ init_ch = kcalloc((number + 1 ), sizeof(struct clk_init_data), GFP_KERNEL); ++ if (!init_ch){ ++ /* Error */ ++ pr_err("%s: could not allocate CMU init structure \n", __func__); ++ kfree(init_ch); ++ kfree(cmu_ch); ++ kfree(clk_ch); ++ return -ENOMEM; ++ } ++ ++ of_property_for_each_u32(node, "clock-indices", prop, p, index) { ++ of_property_read_string_index(node, "clock-names", ++ i, &clk_ch_name); ++ pr_err("%s index %x name <%s> i %x \n", __func__,index, clk_ch_name, i); ++ cmu_ch[index] = kmalloc(sizeof(struct baikal_clk_cmu), GFP_KERNEL); ++ ++ cmu_ch[index]->name = clk_ch_name; ++ cmu_ch[index]->cmu_id = index; ++ cmu_ch[index]->parent = cmu->cmu_id; ++ cmu_ch[index]->is_clk_ch = 1; ++ init_ch[i].parent_names = &cmu->name; ++ init_ch[i].num_parents = 1; ++ ++ init_ch[i].name = clk_ch_name; ++ init_ch[i].ops = &be_clk_pll_ops; ++ init_ch[i].flags = CLK_IGNORE_UNUSED; ++ ++ cmu_ch[index]->hw.init = &init_ch[i]; ++ clk_ch->clks[index] = clk_register(NULL, &cmu_ch[index]->hw); ++ ++ if (IS_ERR(clk_ch->clks[index])) { ++ /* Error */ ++ pr_err("%s: could not register clk %s\n", __func__, clk_ch_name); ++ } ++ /* Register the clock for lookup */ ++ rc = clk_register_clkdev(clk_ch->clks[index], clk_ch_name, NULL); ++ if (rc != 0) { ++ /* Error */ ++ pr_err("%s: could not register lookup clk %s\n", ++ __func__, clk_ch_name); ++ } ++ /* FIXME We probably SHOULDN'T enable it here */ ++ clk_prepare_enable(clk_ch->clks[index]); ++ i++; ++ } ++ return of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, clk_ch); ++ } else ++ ++ return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get, clk); ++} ++ ++static int baikal_clk_remove(struct platform_device *pdev) ++{ ++ of_clk_del_provider(pdev->dev.of_node); ++ ++ return 0; ++} ++ ++static const struct of_device_id baikal_clk_of_match[] = { ++ {.compatible = "baikal,cmu"}, ++ { /* sentinel value */ } ++}; ++ ++static struct platform_driver clk_avlsp_cmu0_driver = { ++ .probe = baikal_clk_probe, ++ .remove = baikal_clk_remove, ++ .driver = { ++ .name = "baikal-avlsp-cmu0", ++ .of_match_table = baikal_clk_of_match, ++ }, ++}; ++ ++static struct platform_driver clk_avlsp_cmu1_driver = { ++ .probe = baikal_clk_probe, ++ .remove = baikal_clk_remove, ++ .driver = { ++ .name = "baikal-avlsp-cmu1", ++ .of_match_table = baikal_clk_of_match, ++ }, ++}; ++ ++static struct platform_driver clk_xgbe_cmu0_driver = { ++ .probe = baikal_clk_probe, ++ .remove = baikal_clk_remove, ++ .driver = { ++ .name = "baikal-xgbe-cmu0", ++ .of_match_table = baikal_clk_of_match, ++ }, ++}; ++ ++static struct platform_driver clk_xgbe_cmu1_driver = { ++ .probe = baikal_clk_probe, ++ .remove = baikal_clk_remove, ++ .driver = { ++ .name = "baikal-xgbe-cmu1", ++ .of_match_table = baikal_clk_of_match, ++ }, ++}; ++ ++static struct platform_driver clk_ca57_cmu_driver = { ++ .probe = baikal_clk_probe, ++ .remove = baikal_clk_remove, ++ .driver = { ++ .name = "baikal-ca57_cmu", ++ .of_match_table = baikal_clk_of_match, ++ }, ++}; ++ ++static struct platform_driver clk_mali_cmu_driver = { ++ .probe = baikal_clk_probe, ++ .remove = baikal_clk_remove, ++ .driver = { ++ .name = "baikal-mali-cmu", ++ .of_match_table = baikal_clk_of_match, ++ }, ++}; ++ ++module_platform_driver(clk_avlsp_cmu0_driver); ++module_platform_driver(clk_avlsp_cmu1_driver); ++module_platform_driver(clk_xgbe_cmu0_driver); ++module_platform_driver(clk_xgbe_cmu1_driver); ++module_platform_driver(clk_mali_cmu_driver); ++module_platform_driver(clk_ca57_cmu_driver); ++ ++MODULE_DESCRIPTION("Clkout driver for the Baikal-M"); ++MODULE_AUTHOR("Ekaterina Skachko "); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:baikal-cmu"); +-- +2.31.1 + diff --git a/0603-efi-rtc-avoid-calling-efi.get_time-on-Baikal-M-board.patch b/0603-efi-rtc-avoid-calling-efi.get_time-on-Baikal-M-board.patch new file mode 100644 index 0000000..9b8c578 --- /dev/null +++ b/0603-efi-rtc-avoid-calling-efi.get_time-on-Baikal-M-board.patch @@ -0,0 +1,44 @@ +From 7b165ef3f844bd6a7f6edb195ba03e33291f0f8d Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Thu, 8 Oct 2020 18:31:28 +0400 +Subject: [PATCH 603/625] efi-rtc: avoid calling efi.get_time on Baikal-M + boards + +UEFI does NOT provide get_time at the runtime, hence calling it results +in an Oops. + +(cherry picked from commit 57a5898a6f7e7c80999cb844ed2f0394b38afcbe) +--- + drivers/rtc/rtc-efi.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/rtc/rtc-efi.c b/drivers/rtc/rtc-efi.c +index edb64debd173..895bb07a7006 100644 +--- a/drivers/rtc/rtc-efi.c ++++ b/drivers/rtc/rtc-efi.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + + #define EFI_ISDST (EFI_TIME_ADJUST_DAYLIGHT|EFI_TIME_IN_DAYLIGHT) + +@@ -257,6 +258,14 @@ static int __init efi_rtc_probe(struct platform_device *dev) + efi_time_t eft; + efi_time_cap_t cap; + ++#ifdef CONFIG_OF ++ /* efi.get_time is not always safe to call since some UEFI ++ * implementations do not privde get_time at runtime. */ ++ if (of_device_is_compatible(of_root, "baikal,baikal-m")) { ++ dev_err(&dev->dev, "Baikal-M UEFI has no get_time\n"); ++ return -ENODEV; ++ } ++#endif + /* First check if the RTC is usable */ + if (efi.get_time(&eft, &cap) != EFI_SUCCESS) + return -ENODEV; +-- +2.31.1 + diff --git a/0604-efi-arm-runtime-print-EFI-mapping.patch b/0604-efi-arm-runtime-print-EFI-mapping.patch new file mode 100644 index 0000000..1ab0d5b --- /dev/null +++ b/0604-efi-arm-runtime-print-EFI-mapping.patch @@ -0,0 +1,27 @@ +From 33a36bf1bf71c1bffdb0631a09856a24ba3d8165 Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Fri, 20 Mar 2020 17:14:36 +0400 +Subject: [PATCH 604/625] efi/arm-runtime: print EFI mapping + +(cherry picked from commit 652f76ffabc0e987169934d924d9e34b99b4cca9) +--- + drivers/firmware/efi/arm-runtime.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/firmware/efi/arm-runtime.c b/drivers/firmware/efi/arm-runtime.c +index 3359ae2adf24..5028cd1605f3 100644 +--- a/drivers/firmware/efi/arm-runtime.c ++++ b/drivers/firmware/efi/arm-runtime.c +@@ -71,6 +71,9 @@ static bool __init efi_virtmap_init(void) + pr_warn(" EFI remap %pa: failed to create mapping (%d)\n", + &phys, ret); + return false; ++ } else { ++ pr_info(" EFI remap %pa => %llx\n", ++ &phys, (unsigned long long)md->virt_addr); + } + } + +-- +2.31.1 + diff --git a/0605-ethernet-stmmac-made-dwmac1000_-DMA-functions-availa.patch b/0605-ethernet-stmmac-made-dwmac1000_-DMA-functions-availa.patch new file mode 100644 index 0000000..4ab80e0 --- /dev/null +++ b/0605-ethernet-stmmac-made-dwmac1000_-DMA-functions-availa.patch @@ -0,0 +1,253 @@ +From ddbb6264ac1a4216a1b965b4ddc0d7cb31fe3d99 Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Wed, 3 Jun 2020 20:22:29 +0400 +Subject: [PATCH 605/625] ethernet: stmmac: made dwmac1000_* DMA functions + available for reuse + +Some variants of dwmac hardware (in particular the one in the BE-M1000 +SoC) need custom DMA reset, and can reuse other dwmac1000 DMA functions. + +(cherry picked from commit f8e6ec3642eb28e7b74c0a7875310d7354895c8a) +--- + .../ethernet/stmicro/stmmac/dwmac1000_core.c | 1 + + .../ethernet/stmicro/stmmac/dwmac1000_dma.c | 45 +++++++++++-------- + .../ethernet/stmicro/stmmac/dwmac1000_dma.h | 26 +++++++++++ + .../net/ethernet/stmicro/stmmac/dwmac_lib.c | 8 ++++ + 4 files changed, 62 insertions(+), 18 deletions(-) + create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.h + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c +index fc8759f146c7..bf4f79ef3b22 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c +@@ -563,3 +563,4 @@ int dwmac1000_setup(struct stmmac_priv *priv) + + return 0; + } ++EXPORT_SYMBOL_GPL(dwmac1000_setup); +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c +index 2bac49b49f73..d27d5292550a 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c +@@ -16,7 +16,7 @@ + #include "dwmac1000.h" + #include "dwmac_dma.h" + +-static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) ++void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) + { + u32 value = readl(ioaddr + DMA_AXI_BUS_MODE); + int i; +@@ -69,9 +69,10 @@ static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) + + writel(value, ioaddr + DMA_AXI_BUS_MODE); + } ++EXPORT_SYMBOL_GPL(dwmac1000_dma_axi); + +-static void dwmac1000_dma_init(void __iomem *ioaddr, +- struct stmmac_dma_cfg *dma_cfg, int atds) ++void dwmac1000_dma_init(void __iomem *ioaddr, ++ struct stmmac_dma_cfg *dma_cfg, int atds) + { + u32 value = readl(ioaddr + DMA_BUS_MODE); + int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; +@@ -109,22 +110,25 @@ static void dwmac1000_dma_init(void __iomem *ioaddr, + /* Mask interrupts by writing to CSR7 */ + writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); + } ++EXPORT_SYMBOL_GPL(dwmac1000_dma_init); + +-static void dwmac1000_dma_init_rx(void __iomem *ioaddr, +- struct stmmac_dma_cfg *dma_cfg, +- dma_addr_t dma_rx_phy, u32 chan) ++void dwmac1000_dma_init_rx(void __iomem *ioaddr, ++ struct stmmac_dma_cfg *dma_cfg, ++ dma_addr_t dma_rx_phy, u32 chan) + { + /* RX descriptor base address list must be written into DMA CSR3 */ + writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR); + } ++EXPORT_SYMBOL_GPL(dwmac1000_dma_init_rx); + +-static void dwmac1000_dma_init_tx(void __iomem *ioaddr, +- struct stmmac_dma_cfg *dma_cfg, +- dma_addr_t dma_tx_phy, u32 chan) ++void dwmac1000_dma_init_tx(void __iomem *ioaddr, ++ struct stmmac_dma_cfg *dma_cfg, ++ dma_addr_t dma_tx_phy, u32 chan) + { + /* TX descriptor base address list must be written into DMA CSR4 */ + writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR); + } ++EXPORT_SYMBOL_GPL(dwmac1000_dma_init_tx); + + static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz) + { +@@ -147,8 +151,8 @@ static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz) + return csr6; + } + +-static void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode, +- u32 channel, int fifosz, u8 qmode) ++void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode, ++ u32 channel, int fifosz, u8 qmode) + { + u32 csr6 = readl(ioaddr + DMA_CONTROL); + +@@ -174,9 +178,10 @@ static void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode, + + writel(csr6, ioaddr + DMA_CONTROL); + } ++EXPORT_SYMBOL_GPL(dwmac1000_dma_operation_mode_rx); + +-static void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode, +- u32 channel, int fifosz, u8 qmode) ++void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode, ++ u32 channel, int fifosz, u8 qmode) + { + u32 csr6 = readl(ioaddr + DMA_CONTROL); + +@@ -207,8 +212,9 @@ static void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode, + + writel(csr6, ioaddr + DMA_CONTROL); + } ++EXPORT_SYMBOL_GPL(dwmac1000_dma_operation_mode_tx); + +-static void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) ++void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) + { + int i; + +@@ -217,9 +223,10 @@ static void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) + reg_space[DMA_BUS_MODE / 4 + i] = + readl(ioaddr + DMA_BUS_MODE + i * 4); + } ++EXPORT_SYMBOL_GPL(dwmac1000_dump_dma_regs); + +-static void dwmac1000_get_hw_feature(void __iomem *ioaddr, +- struct dma_features *dma_cap) ++void dwmac1000_get_hw_feature(void __iomem *ioaddr, ++ struct dma_features *dma_cap) + { + u32 hw_cap = readl(ioaddr + DMA_HW_FEATURE); + +@@ -253,12 +260,14 @@ static void dwmac1000_get_hw_feature(void __iomem *ioaddr, + /* Alternate (enhanced) DESC mode */ + dma_cap->enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; + } ++EXPORT_SYMBOL_GPL(dwmac1000_get_hw_feature); + +-static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt, +- u32 number_chan) ++void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt, ++ u32 number_chan) + { + writel(riwt, ioaddr + DMA_RX_WATCHDOG); + } ++EXPORT_SYMBOL_GPL(dwmac1000_rx_watchdog); + + const struct stmmac_dma_ops dwmac1000_dma_ops = { + .reset = dwmac_dma_reset, +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.h +new file mode 100644 +index 000000000000..b1e39a109f31 +--- /dev/null ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.h +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __DWMAC1000_DMA_H__ ++#define __DWMAC1000_DMA_H__ ++#include "dwmac1000.h" ++ ++void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi); ++void dwmac1000_dma_init(void __iomem *ioaddr, ++ struct stmmac_dma_cfg *dma_cfg, int atds); ++void dwmac1000_dma_init_rx(void __iomem *ioaddr, ++ struct stmmac_dma_cfg *dma_cfg, ++ dma_addr_t dma_rx_phy, u32 chan); ++void dwmac1000_dma_init_tx(void __iomem *ioaddr, ++ struct stmmac_dma_cfg *dma_cfg, ++ dma_addr_t dma_tx_phy, u32 chan); ++void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode, ++ u32 channel, int fifosz, u8 qmode); ++void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode, ++ u32 channel, int fifosz, u8 qmode); ++void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space); ++ ++void dwmac1000_get_hw_feature(void __iomem *ioaddr, ++ struct dma_features *dma_cap); ++ ++void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan); ++#endif /* __DWMAC1000_DMA_H__ */ +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c +index 57a53a600aa5..e391285a2158 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c +@@ -31,6 +31,7 @@ void dwmac_enable_dma_transmission(void __iomem *ioaddr) + { + writel(1, ioaddr + DMA_XMT_POLL_DEMAND); + } ++EXPORT_SYMBOL_GPL(dwmac_enable_dma_transmission); + + void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) + { +@@ -43,6 +44,7 @@ void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) + + writel(value, ioaddr + DMA_INTR_ENA); + } ++EXPORT_SYMBOL_GPL(dwmac_enable_dma_irq); + + void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) + { +@@ -55,6 +57,7 @@ void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) + + writel(value, ioaddr + DMA_INTR_ENA); + } ++EXPORT_SYMBOL_GPL(dwmac_disable_dma_irq); + + void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) + { +@@ -62,6 +65,7 @@ void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) + value |= DMA_CONTROL_ST; + writel(value, ioaddr + DMA_CONTROL); + } ++EXPORT_SYMBOL_GPL(dwmac_dma_start_tx); + + void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) + { +@@ -69,6 +73,7 @@ void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) + value &= ~DMA_CONTROL_ST; + writel(value, ioaddr + DMA_CONTROL); + } ++EXPORT_SYMBOL_GPL(dwmac_dma_stop_tx); + + void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) + { +@@ -76,6 +81,7 @@ void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) + value |= DMA_CONTROL_SR; + writel(value, ioaddr + DMA_CONTROL); + } ++EXPORT_SYMBOL_GPL(dwmac_dma_start_rx); + + void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) + { +@@ -83,6 +89,7 @@ void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) + value &= ~DMA_CONTROL_SR; + writel(value, ioaddr + DMA_CONTROL); + } ++EXPORT_SYMBOL_GPL(dwmac_dma_stop_rx); + + #ifdef DWMAC_DMA_DEBUG + static void show_tx_process_state(unsigned int status) +@@ -224,6 +231,7 @@ int dwmac_dma_interrupt(void __iomem *ioaddr, + + return ret; + } ++EXPORT_SYMBOL_GPL(dwmac_dma_interrupt); + + void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr) + { +-- +2.31.1 + diff --git a/0606-stmmac-Baikal-M-dwmac-driver.patch b/0606-stmmac-Baikal-M-dwmac-driver.patch new file mode 100644 index 0000000..36b67ce --- /dev/null +++ b/0606-stmmac-Baikal-M-dwmac-driver.patch @@ -0,0 +1,278 @@ +From 8d0e122d3d4979e32c6ad0d340d8c9b31a8b4d95 Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Fri, 20 Mar 2020 14:00:56 +0400 +Subject: [PATCH 606/625] stmmac: Baikal-M dwmac driver + +(cherry picked from commit 5fd65e2b57a4873946822e99fb74b07caa73c341) +--- + drivers/net/ethernet/stmicro/stmmac/Kconfig | 10 + + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + + .../ethernet/stmicro/stmmac/dwmac-baikal.c | 223 ++++++++++++++++++ + 3 files changed, 234 insertions(+) + create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-baikal.c + +diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig +index 53f14c5a9e02..26a3f62a36cc 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig ++++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig +@@ -66,6 +66,16 @@ config DWMAC_ANARION + + This selects the Anarion SoC glue layer support for the stmmac driver. + ++config DWMAC_BAIKAL ++ tristate "Baikal Electronics DWMAC support" ++ default y if MIPS_BAIKAL || ARCH_BAIKAL ++ depends on OF ++ help ++ Support for Baikal Electronics DWMAC Ethernet. ++ ++ This selects the Baikal-T/M SoC glue layer support for the stmmac ++ device driver. ++ + config DWMAC_IPQ806X + tristate "QCA IPQ806x DWMAC support" + default ARCH_QCOM +diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile +index 24e6145d4eae..64970f60f536 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/Makefile ++++ b/drivers/net/ethernet/stmicro/stmmac/Makefile +@@ -13,6 +13,7 @@ stmmac-$(CONFIG_STMMAC_SELFTESTS) += stmmac_selftests.o + # Ordering matters. Generic driver must be last. + obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o + obj-$(CONFIG_DWMAC_ANARION) += dwmac-anarion.o ++obj-$(CONFIG_DWMAC_BAIKAL) += dwmac-baikal.o + obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o + obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o + obj-$(CONFIG_DWMAC_MEDIATEK) += dwmac-mediatek.o +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-baikal.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-baikal.c +new file mode 100644 +index 000000000000..646051cd500d +--- /dev/null ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-baikal.c +@@ -0,0 +1,223 @@ ++/* ++ * Baikal Electronics SoCs DWMAC glue layer ++ * ++ * Copyright (C) 2015,2016 Baikal Electronics JSC ++ * Author: ++ * Dmitry Dunaev ++ * All bugs by Alexey Sheplyakov ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "stmmac.h" ++#include "stmmac_platform.h" ++#include "common.h" ++#include "dwmac_dma.h" ++#include "dwmac1000_dma.h" ++ ++#define MAC_GPIO 0x000000e0 /* GPIO register */ ++#define MAC_GPIO_GPO0 (1 << 8) /* 0-output port */ ++ ++struct baikal_dwmac { ++ struct device *dev; ++ struct clk *tx2_clk; ++}; ++ ++static int baikal_dwmac_dma_reset(void __iomem *ioaddr) ++{ ++ int err; ++ u32 value = readl(ioaddr + DMA_BUS_MODE); ++ ++ /* DMA SW reset */ ++ value |= DMA_BUS_MODE_SFT_RESET; ++ writel(value, ioaddr + DMA_BUS_MODE); ++ ++ udelay(10); ++ /* Clear PHY reset */ ++ value = readl(ioaddr + MAC_GPIO); ++ value |= MAC_GPIO_GPO0; ++ writel(value, ioaddr + MAC_GPIO); ++ pr_info("PHY re-inited for Baikal DWMAC\n"); ++ ++ err = readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, ++ !(value & DMA_BUS_MODE_SFT_RESET), ++ 10000, 1000000); ++ if (err) ++ return -EBUSY; ++ ++ return 0; ++} ++ ++static const struct stmmac_dma_ops baikal_dwmac_dma_ops = { ++ .reset = baikal_dwmac_dma_reset, ++ .init = dwmac1000_dma_init, ++ .init_rx_chan = dwmac1000_dma_init_rx, ++ .init_tx_chan = dwmac1000_dma_init_tx, ++ .axi = dwmac1000_dma_axi, ++ .dump_regs = dwmac1000_dump_dma_regs, ++ .dma_rx_mode = dwmac1000_dma_operation_mode_rx, ++ .dma_tx_mode = dwmac1000_dma_operation_mode_tx, ++ .enable_dma_transmission = dwmac_enable_dma_transmission, ++ .enable_dma_irq = dwmac_enable_dma_irq, ++ .disable_dma_irq = dwmac_disable_dma_irq, ++ .start_tx = dwmac_dma_start_tx, ++ .stop_tx = dwmac_dma_stop_tx, ++ .start_rx = dwmac_dma_start_rx, ++ .stop_rx = dwmac_dma_stop_rx, ++ .dma_interrupt = dwmac_dma_interrupt, ++ .get_hw_feature = dwmac1000_get_hw_feature, ++ .rx_watchdog = dwmac1000_rx_watchdog, ++}; ++ ++static struct mac_device_info* baikal_dwmac_setup(void *ppriv) ++{ ++ struct mac_device_info *mac, *old_mac; ++ struct stmmac_priv *priv = ppriv; ++ int ret; ++ ++ mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); ++ if (!mac) ++ return NULL; ++ ++ mac->dma = &baikal_dwmac_dma_ops; ++ old_mac = priv->hw; ++ priv->hw = mac; ++ ret = dwmac1000_setup(priv); ++ priv->hw = old_mac; ++ if (ret) { ++ dev_err(priv->device, "dwmac1000_setup: error %d", ret); ++ return NULL; ++ } ++ return mac; ++} ++ ++static void baikal_dwmac_fix_mac_speed(void *priv, unsigned int speed) ++{ ++ struct baikal_dwmac *dwmac = priv; ++ unsigned long tx2_clk_freq = 0; ++ dev_info(dwmac->dev, "fix_mac_speed new speed %u\n", speed); ++ switch (speed) { ++ case SPEED_1000: ++ tx2_clk_freq = 250000000; ++ break; ++ case SPEED_100: ++ tx2_clk_freq = 50000000; ++ break; ++ case SPEED_10: ++ tx2_clk_freq = 5000000; ++ break; ++ } ++ if (dwmac->tx2_clk && tx2_clk_freq != 0) { ++ dev_info(dwmac->dev, "setting TX2 clock frequency to %lu\n", tx2_clk_freq); ++ clk_set_rate(dwmac->tx2_clk, tx2_clk_freq); ++ ++ } ++ ++} ++ ++ ++static int dwmac_baikal_probe(struct platform_device *pdev) ++{ ++ struct plat_stmmacenet_data *plat_dat; ++ struct stmmac_resources stmmac_res; ++ struct baikal_dwmac *dwmac; ++ int ret; ++ ++ ret = stmmac_get_platform_resources(pdev, &stmmac_res); ++ if (ret) ++ return ret; ++ ++ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_warn(&pdev->dev, "No suitable DMA available\n"); ++ return ret; ++ } ++ ++ if (pdev->dev.of_node) { ++ plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); ++ if (IS_ERR(plat_dat)) { ++ dev_err(&pdev->dev, "dt configuration failed\n"); ++ return PTR_ERR(plat_dat); ++ } ++ } else { ++ plat_dat = dev_get_platdata(&pdev->dev); ++ if (!plat_dat) { ++ dev_err(&pdev->dev, "no platform data provided\n"); ++ return -EINVAL; ++ } ++ ++ /* Set default value for multicast hash bins */ ++ plat_dat->multicast_filter_bins = HASH_TABLE_SIZE; ++ ++ /* Set default value for unicast filter entries */ ++ plat_dat->unicast_filter_entries = 1; ++ } ++ ++ dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); ++ if (!dwmac) { ++ ret = -ENOMEM; ++ goto err_remove_config_dt; ++ } ++ ++ dwmac->dev = &pdev->dev; ++ dwmac->tx2_clk = devm_clk_get(dwmac->dev, "tx2_clk"); ++ if (IS_ERR(dwmac->tx2_clk)) { ++ dev_warn(&pdev->dev, "coldn't get TX2 clock\n"); ++ dwmac->tx2_clk = NULL; ++ } ++ plat_dat->fix_mac_speed = baikal_dwmac_fix_mac_speed; ++ plat_dat->bsp_priv = dwmac; ++ ++ plat_dat->has_gmac = 1; ++ plat_dat->enh_desc = 1; ++ plat_dat->tx_coe = 1; ++ plat_dat->rx_coe = 1; ++ // TODO: set CSR correct clock in dts! ++ plat_dat->clk_csr = 3; ++ plat_dat->setup = baikal_dwmac_setup; ++ ++ dev_info(&pdev->dev, "Baikal Electronics DWMAC glue driver\n"); ++ ++ ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); ++ if (ret) ++ goto err_remove_config_dt; ++ ++ return 0; ++ ++err_remove_config_dt: ++ stmmac_remove_config_dt(pdev, plat_dat); ++ ++ return ret; ++} ++ ++static const struct of_device_id dwmac_baikal_match[] = { ++ { .compatible = "be,dwmac-3.710"}, ++ { .compatible = "be,dwmac"}, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, dwmac_baikal_match); ++ ++static struct platform_driver dwmac_baikal_driver = { ++ .probe = dwmac_baikal_probe, ++ .remove = stmmac_pltfr_remove, ++ .driver = { ++ .name = "baikal-dwmac", ++ .pm = &stmmac_pltfr_pm_ops, ++ .of_match_table = of_match_ptr(dwmac_baikal_match), ++ }, ++}; ++module_platform_driver(dwmac_baikal_driver); ++ ++MODULE_DESCRIPTION("Baikal dwmac glue driver"); ++MODULE_LICENSE("GPL v2"); +-- +2.31.1 + diff --git a/0607-Fixed-secondary-CPUs-boot-on-BE-M1000-SoC.patch b/0607-Fixed-secondary-CPUs-boot-on-BE-M1000-SoC.patch new file mode 100644 index 0000000..cbc5131 --- /dev/null +++ b/0607-Fixed-secondary-CPUs-boot-on-BE-M1000-SoC.patch @@ -0,0 +1,137 @@ +From 460b2ff3c8509372228afae9e869aa375b85c319 Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Tue, 10 Nov 2020 19:05:39 +0400 +Subject: [PATCH 607/625] Fixed secondary CPUs boot on BE-M1000 SoC + +The secure world on BE-M1000 SoC denies execution attempts outside of +the ranges [0x80000000, 0x8FFFFFFF] [0xA0000000, 0xBFFFFFFF]. Thus +PSCI calls to boot secondary CPUs fail unless the kernel image resides +in one of these (physical) address ranges. However BE-M1000's UEFI +PE/COFF loader puts the kernel into the forbidden range. Since the alignment +is good enough EFI stub does not try to relocate the kernel. As a result +secondary CPUs fail to boot. + +Relocation to a random address is not going to work either. Therefore +automatically disable kaslr on "known bad" systems (for now only BE-M1000 +ones) and forcibly relocate the kernel to a low(er) address. +--- + drivers/firmware/efi/libstub/arm64-stub.c | 61 ++++++++++++++++++++++- + 1 file changed, 60 insertions(+), 1 deletion(-) + +diff --git a/drivers/firmware/efi/libstub/arm64-stub.c b/drivers/firmware/efi/libstub/arm64-stub.c +index 22ece1ad68a8..897708508909 100644 +--- a/drivers/firmware/efi/libstub/arm64-stub.c ++++ b/drivers/firmware/efi/libstub/arm64-stub.c +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + #include + + #include "efistub.h" +@@ -34,6 +35,31 @@ efi_status_t check_platform_features(void) + return EFI_SUCCESS; + } + ++static const char* machines_need_low_alloc[] = { ++ "baikal,baikal-m", ++}; ++ ++static bool need_low_alloc(void) { ++ size_t i; ++ const void *fdt; ++ const char *match; ++ ++ fdt = get_efi_config_table(DEVICE_TREE_GUID); ++ if (!fdt) { ++ efi_info("failed to retrive FDT from EFI\n"); ++ return false; ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(machines_need_low_alloc); i++) { ++ match = machines_need_low_alloc[i]; ++ if (fdt_node_check_compatible(fdt, 0, match) == 0) { ++ efi_info("machine %s: forcing kernel relocation to low address\n", match); ++ return true; ++ } ++ } ++ return false; ++} ++ + /* + * Although relocatable kernels can fix up the misalignment with respect to + * MIN_KIMG_ALIGN, the resulting virtual text addresses are subtly out of +@@ -46,6 +72,19 @@ static u64 min_kimg_align(void) + return efi_nokaslr ? MIN_KIMG_ALIGN : EFI_KIMG_ALIGN; + } + ++static inline efi_status_t efi_low_alloc(unsigned long size, unsigned long align, ++ unsigned long *addr) ++{ ++ /* ++ * Don't allocate at 0x0. It will confuse code that ++ * checks pointers against NULL. Skip the first 8 ++ * bytes so we start at a nice even number. ++ */ ++ return efi_low_alloc_above(size, align, addr, 0x8); ++} ++ ++ ++ + efi_status_t handle_kernel_image(unsigned long *image_addr, + unsigned long *image_size, + unsigned long *reserve_addr, +@@ -55,6 +94,13 @@ efi_status_t handle_kernel_image(unsigned long *image_addr, + efi_status_t status; + unsigned long kernel_size, kernel_memsize = 0; + u32 phys_seed = 0; ++ bool force_low_reloc = need_low_alloc(); ++ if (force_low_reloc) { ++ if (!efi_nokaslr) { ++ efi_info("booting on a broken firmware, KASLR will be disabled\n"); ++ efi_nokaslr = true; ++ } ++ } + + if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) { + if (!efi_nokaslr) { +@@ -69,7 +115,8 @@ efi_status_t handle_kernel_image(unsigned long *image_addr, + efi_nokaslr = true; + } + } else { +- efi_info("KASLR disabled on kernel command line\n"); ++ if (!force_low_reloc) ++ efi_info("KASLR disabled on kernel command line\n"); + } + } + +@@ -91,6 +138,15 @@ efi_status_t handle_kernel_image(unsigned long *image_addr, + status = EFI_OUT_OF_RESOURCES; + } + ++ if (force_low_reloc) { ++ status = efi_low_alloc(*reserve_size, ++ min_kimg_align(), ++ reserve_addr); ++ if (status != EFI_SUCCESS) { ++ efi_err("Failed to relocate kernel, expect secondary CPUs boot failure\n"); ++ } ++ } ++ + if (status != EFI_SUCCESS) { + if (IS_ALIGNED((u64)_text, min_kimg_align())) { + /* +@@ -113,6 +169,9 @@ efi_status_t handle_kernel_image(unsigned long *image_addr, + } + + *image_addr = *reserve_addr; ++ if (efi_nokaslr) { ++ efi_info("relocating kernel to 0x%lx\n", *image_addr); ++ } + memcpy((void *)*image_addr, _text, kernel_size); + + return EFI_SUCCESS; +-- +2.31.1 + diff --git a/0608-Baikal-M-USB-driver.patch b/0608-Baikal-M-USB-driver.patch new file mode 100644 index 0000000..dceb69f --- /dev/null +++ b/0608-Baikal-M-USB-driver.patch @@ -0,0 +1,175 @@ +From 91e33969c0864de65db59308b298d321a5280daa Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Fri, 20 Mar 2020 14:02:43 +0400 +Subject: [PATCH 608/625] Baikal-M: USB driver + +(cherry picked from commit 136cab54114b2b0b61cf503065d6d547f3d3d5a2) +--- + drivers/usb/dwc3/Kconfig | 9 +++ + drivers/usb/dwc3/Makefile | 1 + + drivers/usb/dwc3/dwc3-baikal.c | 126 +++++++++++++++++++++++++++++++++ + 3 files changed, 136 insertions(+) + create mode 100644 drivers/usb/dwc3/dwc3-baikal.c + +diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig +index 7a2304565a73..121f8e708d51 100644 +--- a/drivers/usb/dwc3/Kconfig ++++ b/drivers/usb/dwc3/Kconfig +@@ -139,4 +139,13 @@ config USB_DWC3_QCOM + for peripheral mode support. + Say 'Y' or 'M' if you have one such device. + ++config USB_DWC3_BAIKAL ++ tristate "Baikal Electronics Platforms" ++ depends on OF ++ default USB_DWC3 ++ help ++ Baikal Electronics SoCs with one DesignWare Core USB3 IP ++ inside. ++ Say 'Y' or 'M' if you have one such device. ++ + endif +diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile +index ae86da0dc5bd..0dcaf92a43ec 100644 +--- a/drivers/usb/dwc3/Makefile ++++ b/drivers/usb/dwc3/Makefile +@@ -51,3 +51,4 @@ obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o + obj-$(CONFIG_USB_DWC3_OF_SIMPLE) += dwc3-of-simple.o + obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o + obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o ++obj-$(CONFIG_USB_DWC3_BAIKAL) += dwc3-baikal.o +diff --git a/drivers/usb/dwc3/dwc3-baikal.c b/drivers/usb/dwc3/dwc3-baikal.c +new file mode 100644 +index 000000000000..2426dc49bd79 +--- /dev/null ++++ b/drivers/usb/dwc3/dwc3-baikal.c +@@ -0,0 +1,126 @@ ++/** ++ * dwc3-baikal.c - Baikal Electronics SoCs Specific Glue layer ++ * ++ * Copyright (C) 2015 Baikal Electronics JSC - http://www.baikalelectronics.ru ++ * ++ * Author: Dmitry Dunaev ++ * ++ * This program is free software: you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 of ++ * the License as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct dwc3_baikal { ++ struct device *dev; ++ struct clk *clk; ++}; ++ ++static int be_dwc3_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *node = pdev->dev.of_node; ++ struct dwc3_baikal *dwc; ++ int ret; ++ ++ dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); ++ if (!dwc) ++ return -ENOMEM; ++ ++ ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64)); ++ if (ret) { ++ dev_err(dev, "DMA mask error %d\n", ret); ++ return ret; ++ } ++ ++ platform_set_drvdata(pdev, dwc); ++ dwc->dev = dev; ++ ++ dwc->clk = devm_clk_get(dwc->dev, "usb"); ++ if (IS_ERR(dwc->clk)) { ++ dev_err(dev, "no interface clk specified\n"); ++ return -EINVAL; ++ } ++ ++ ret = clk_prepare_enable(dwc->clk); ++ if (ret < 0) { ++ dev_err(dwc->dev, "unable to enable usb clock\n"); ++ return ret; ++ } ++ ++ if (node) { ++ ret = of_platform_populate(node, NULL, NULL, dev); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to create dwc3 core\n"); ++ goto __error; ++ } ++ } else { ++ dev_err(dev, "no device node, failed to add dwc3 core\n"); ++ ret = -ENODEV; ++ goto __error; ++ } ++ ++ return 0; ++ ++__error: ++ clk_disable_unprepare(dwc->clk); ++ ++ return ret; ++} ++ ++static int be_dwc3_remove_core(struct device *dev, void *c) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ ++ platform_device_unregister(pdev); ++ ++ return 0; ++} ++ ++static int be_dwc3_remove(struct platform_device *pdev) ++{ ++ struct dwc3_baikal *dwc = platform_get_drvdata(pdev); ++ ++ device_for_each_child(&pdev->dev, NULL, be_dwc3_remove_core); ++ clk_disable_unprepare(dwc->clk); ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++static const struct of_device_id be_dwc3_of_match[] = { ++ { .compatible = "be,baikal-dwc3", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, be_dwc3_of_match); ++ ++static struct platform_driver be_dwc3_driver = { ++ .probe = be_dwc3_probe, ++ .remove = be_dwc3_remove, ++ .driver = { ++ .name = "baikal-dwc3", ++ .of_match_table = be_dwc3_of_match, ++ }, ++}; ++ ++module_platform_driver(be_dwc3_driver); ++ ++MODULE_ALIAS("platform:baikal-dwc3"); ++MODULE_AUTHOR("Dmitry Dunaev "); ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("DesignWare USB3 Baikal SoCs Glue Layer"); +-- +2.31.1 + diff --git a/0609-Baikal-M-video-unit-driver.patch b/0609-Baikal-M-video-unit-driver.patch new file mode 100644 index 0000000..8856535 --- /dev/null +++ b/0609-Baikal-M-video-unit-driver.patch @@ -0,0 +1,1722 @@ +From 6bebe9c130b3d2d4e55ac421552b30f945013b76 Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Thu, 30 Apr 2020 15:46:43 +0400 +Subject: [PATCH 609/625] Baikal-M: video unit driver + +Based on code from SDK-M-4.3 with the following improvements: + +* Fixed autoloading when compiled as a module +* Avoid concurrent calls to BAIKAL_SMC_VDU_UPDATE_HDMI +* Added missing drm_crtc_vblank_{on,off} +* Moved enable/disable_vblank to crtc_funcs, so atomic_flip users + (Wayland compistors) work as expected +* Removed empty atomic_check +* Use `drm_fb_cma_get_gem_addr` instead of reimplementing it +--- + drivers/gpu/drm/Kconfig | 1 + + drivers/gpu/drm/Makefile | 1 + + drivers/gpu/drm/baikal/Kconfig | 15 + + drivers/gpu/drm/baikal/Makefile | 12 + + drivers/gpu/drm/baikal/baikal-hdmi.c | 170 ++++++++++ + drivers/gpu/drm/baikal/baikal_vdu_connector.c | 98 ++++++ + drivers/gpu/drm/baikal/baikal_vdu_crtc.c | 310 ++++++++++++++++++ + drivers/gpu/drm/baikal/baikal_vdu_debugfs.c | 87 +++++ + drivers/gpu/drm/baikal/baikal_vdu_drm.h | 95 ++++++ + drivers/gpu/drm/baikal/baikal_vdu_drv.c | 310 ++++++++++++++++++ + drivers/gpu/drm/baikal/baikal_vdu_encoder.c | 51 +++ + drivers/gpu/drm/baikal/baikal_vdu_gem.c | 37 +++ + drivers/gpu/drm/baikal/baikal_vdu_plane.c | 233 +++++++++++++ + drivers/gpu/drm/baikal/baikal_vdu_regs.h | 146 +++++++++ + drivers/gpu/drm/bridge/Kconfig | 7 + + 15 files changed, 1573 insertions(+) + create mode 100644 drivers/gpu/drm/baikal/Kconfig + create mode 100644 drivers/gpu/drm/baikal/Makefile + create mode 100644 drivers/gpu/drm/baikal/baikal-hdmi.c + create mode 100644 drivers/gpu/drm/baikal/baikal_vdu_connector.c + create mode 100644 drivers/gpu/drm/baikal/baikal_vdu_crtc.c + create mode 100644 drivers/gpu/drm/baikal/baikal_vdu_debugfs.c + create mode 100644 drivers/gpu/drm/baikal/baikal_vdu_drm.h + create mode 100644 drivers/gpu/drm/baikal/baikal_vdu_drv.c + create mode 100644 drivers/gpu/drm/baikal/baikal_vdu_encoder.c + create mode 100644 drivers/gpu/drm/baikal/baikal_vdu_gem.c + create mode 100644 drivers/gpu/drm/baikal/baikal_vdu_plane.c + create mode 100644 drivers/gpu/drm/baikal/baikal_vdu_regs.h + +diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig +index ca868271f4c4..06a855255108 100644 +--- a/drivers/gpu/drm/Kconfig ++++ b/drivers/gpu/drm/Kconfig +@@ -235,6 +235,7 @@ config DRM_SCHED + source "drivers/gpu/drm/i2c/Kconfig" + + source "drivers/gpu/drm/arm/Kconfig" ++source "drivers/gpu/drm/baikal/Kconfig" + + config DRM_RADEON + tristate "ATI Radeon" +diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile +index 81569009f884..063e40f93834 100644 +--- a/drivers/gpu/drm/Makefile ++++ b/drivers/gpu/drm/Makefile +@@ -124,3 +124,4 @@ obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/ + obj-$(CONFIG_DRM_MCDE) += mcde/ + obj-$(CONFIG_DRM_TIDSS) += tidss/ + obj-y += xlnx/ ++obj-$(CONFIG_DRM_BAIKAL_VDU) += baikal/ +diff --git a/drivers/gpu/drm/baikal/Kconfig b/drivers/gpu/drm/baikal/Kconfig +new file mode 100644 +index 000000000000..7f3661ae5578 +--- /dev/null ++++ b/drivers/gpu/drm/baikal/Kconfig +@@ -0,0 +1,15 @@ ++config DRM_BAIKAL_VDU ++ tristate "DRM Support for Baikal-M VDU" ++ depends on DRM ++ depends on ARM || ARM64 || COMPILE_TEST ++ depends on COMMON_CLK ++ default y if ARCH_BAIKAL ++ select DRM_KMS_HELPER ++ select DRM_KMS_CMA_HELPER ++ select DRM_GEM_CMA_HELPER ++ select DRM_PANEL ++ select DRM_BAIKAL_HDMI ++ select VT_HW_CONSOLE_BINDING if FRAMEBUFFER_CONSOLE ++ help ++ Choose this option for DRM support for the Baikal-M Video Display Unit (VDU). ++ If M is selected the module will be called baikal_vdu_drm. +diff --git a/drivers/gpu/drm/baikal/Makefile b/drivers/gpu/drm/baikal/Makefile +new file mode 100644 +index 000000000000..4c3e9e67befb +--- /dev/null ++++ b/drivers/gpu/drm/baikal/Makefile +@@ -0,0 +1,12 @@ ++# SPDX-License-Identifier: GPL-2.0 ++baikal_vdu_drm-y += baikal_vdu_connector.o \ ++ baikal_vdu_crtc.o \ ++ baikal_vdu_drv.o \ ++ baikal_vdu_encoder.o \ ++ baikal_vdu_gem.o \ ++ baikal_vdu_plane.o ++ ++baikal_vdu_drm-$(CONFIG_DEBUG_FS) += baikal_vdu_debugfs.o ++ ++obj-$(CONFIG_DRM_BAIKAL_VDU) += baikal_vdu_drm.o ++obj-$(CONFIG_DRM_BAIKAL_HDMI) += baikal-hdmi.o +diff --git a/drivers/gpu/drm/baikal/baikal-hdmi.c b/drivers/gpu/drm/baikal/baikal-hdmi.c +new file mode 100644 +index 000000000000..541d5d126bfc +--- /dev/null ++++ b/drivers/gpu/drm/baikal/baikal-hdmi.c +@@ -0,0 +1,170 @@ ++/* ++ * Baikal Electronics BE-M1000 DesignWare HDMI 2.0 Tx PHY support driver ++ * ++ * Copyright (C) 2019 Baikal Electronics JSC ++ * ++ * Author: Pavel Parkhomenko ++ * ++ * Parts of this file were based on sources as follows: ++ * ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * ++ * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define BAIKAL_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */ ++#define BAIKAL_HDMI_PHY_PLLCURRCTRL 0x10 /* PLL current */ ++#define BAIKAL_HDMI_PHY_PLLGMPCTRL 0x15 /* PLL Gmp (conductance) */ ++#define BAIKAL_HDMI_PHY_TXTERM 0x19 /* Rterm */ ++#define BAIKAL_HDMI_PHY_VLEVCTRL 0x0e /* Voltage levels */ ++#define BAIKAL_HDMI_PHY_CKSYMTXCTRL 0x09 /* Tx symbols control and slope boost */ ++ ++int fixed_clock = 0; ++int max_clock = 0; ++ ++struct baikal_hdmi_phy_params { ++ unsigned long mpixelclock; ++ u16 opmode_div; ++ u16 curr; ++ u16 gmp; ++ u16 txterm; ++ u16 vlevctrl; ++ u16 cksymtxctrl; ++}; ++ ++static const struct baikal_hdmi_phy_params baikal_hdmi_phy_params[] = { ++ /* PCLK opmode current gmp txter vlevctrl cksymtxctrl */ ++ { 44900000, 0x00b3, 0x0000, 0x0000, 0x0004, 0x0232, 0x8009 }, ++ { 90000000, 0x0072, 0x0008, 0x0001, 0x0004, 0x0232, 0x8009 }, ++ { 148250000, 0x0051, 0x001b, 0x0002, 0x0004, 0x0232, 0x8009 }, ++ { 182750000, 0x0051, 0x001b, 0x0002, 0x0004, 0x0230, 0x8009 }, ++ { 218250000, 0x0040, 0x0036, 0x0003, 0x0004, 0x0230, 0x8009 }, ++ { 288000000, 0x0040, 0x0036, 0x0003, 0x0004, 0x0273, 0x8009 }, ++ { 340000000, 0x0040, 0x0036, 0x0003, 0x0004, 0x0273, 0x8029 }, ++ { 594000000, 0x1a40, 0x003f, 0x0003, 0x0004, 0x014a, 0x8039 }, ++ { ~0UL }, ++}; ++ ++static int baikal_hdmi_phy_configure(struct dw_hdmi *hdmi, ++ void *data, ++ unsigned long mpixelclock) ++{ ++ const struct baikal_hdmi_phy_params *params = baikal_hdmi_phy_params; ++ ++ for (; params && params->mpixelclock != ~0UL; ++params) { ++ if (mpixelclock <= params->mpixelclock) ++ break; ++ } ++ ++ if (params->mpixelclock == ~0UL) ++ return -EINVAL; ++ ++ dw_hdmi_phy_i2c_write(hdmi, params->opmode_div, ++ BAIKAL_HDMI_PHY_OPMODE_PLLCFG); ++ dw_hdmi_phy_i2c_write(hdmi, params->curr, ++ BAIKAL_HDMI_PHY_PLLCURRCTRL); ++ dw_hdmi_phy_i2c_write(hdmi, params->gmp, ++ BAIKAL_HDMI_PHY_PLLGMPCTRL); ++ dw_hdmi_phy_i2c_write(hdmi, params->txterm, ++ BAIKAL_HDMI_PHY_TXTERM); ++ dw_hdmi_phy_i2c_write(hdmi, params->vlevctrl, ++ BAIKAL_HDMI_PHY_VLEVCTRL); ++ dw_hdmi_phy_i2c_write(hdmi, params->cksymtxctrl, ++ BAIKAL_HDMI_PHY_CKSYMTXCTRL); ++ ++ return 0; ++} ++ ++static enum drm_mode_status baikal_hdmi_mode_valid(struct dw_hdmi *hdmi, ++ void *data, ++ const struct drm_display_info *info, ++ const struct drm_display_mode *mode) ++{ ++ if (mode->clock < 13500) ++ return MODE_CLOCK_LOW; ++ if (mode->clock >= 340000) ++ return MODE_CLOCK_HIGH; ++ if (fixed_clock && mode->clock != fixed_clock) ++ return MODE_BAD; ++ if (max_clock && mode->clock > max_clock) ++ return MODE_BAD; ++ ++ return MODE_OK; ++} ++ ++static const struct dw_hdmi_plat_data baikal_dw_hdmi_plat_data = { ++ .configure_phy = baikal_hdmi_phy_configure, ++ .mode_valid = baikal_hdmi_mode_valid, ++}; ++ ++static int baikal_dw_hdmi_bind(struct device *dev, struct device *master, void *data) ++{ ++ struct dw_hdmi *hdmi; ++ struct platform_device *pdev = to_platform_device(dev); ++ hdmi = dw_hdmi_probe(pdev, &baikal_dw_hdmi_plat_data); ++ if (IS_ERR(hdmi)) { ++ return PTR_ERR(hdmi); ++ } else ++ return 0; ++} ++ ++static void baikal_dw_hdmi_unbind(struct device *dev, struct device *master, void *data) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ struct dw_hdmi *hdmi = platform_get_drvdata(pdev); ++ dw_hdmi_unbind(hdmi); ++} ++ ++static int baikal_dw_hdmi_probe(struct platform_device *pdev) ++{ ++ struct dw_hdmi *hdmi; ++ hdmi = dw_hdmi_probe(pdev, &baikal_dw_hdmi_plat_data); ++ if (IS_ERR(hdmi)) { ++ return PTR_ERR(hdmi); ++ } else { ++ return 0; ++ } ++} ++ ++static int baikal_dw_hdmi_remove(struct platform_device *pdev) ++{ ++ struct dw_hdmi *hdmi = platform_get_drvdata(pdev); ++ dw_hdmi_remove(hdmi); ++ return 0; ++} ++ ++static const struct of_device_id baikal_dw_hdmi_of_table[] = { ++ { .compatible = "baikal,hdmi" }, ++ { /* Sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, baikal_dw_hdmi_of_table); ++ ++static struct platform_driver baikal_dw_hdmi_platform_driver = { ++ .probe = baikal_dw_hdmi_probe, ++ .remove = baikal_dw_hdmi_remove, ++ .driver = { ++ .name = "baikal-dw-hdmi", ++ .of_match_table = baikal_dw_hdmi_of_table, ++ }, ++}; ++ ++module_param(fixed_clock, int, 0644); ++module_param(max_clock, int, 0644); ++ ++module_platform_driver(baikal_dw_hdmi_platform_driver); ++ ++MODULE_AUTHOR("Pavel Parkhomenko "); ++MODULE_DESCRIPTION("Baikal BE-M1000 SoC DesignWare HDMI 2.0 Tx + Gen2 PHY Driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_connector.c b/drivers/gpu/drm/baikal/baikal_vdu_connector.c +new file mode 100644 +index 000000000000..ca48e230f174 +--- /dev/null ++++ b/drivers/gpu/drm/baikal/baikal_vdu_connector.c +@@ -0,0 +1,98 @@ ++/* ++ * Copyright (C) 2019-2020 Baikal Electronics JSC ++ * ++ * Author: Pavel Parkhomenko ++ * ++ * Parts of this file were based on sources as follows: ++ * ++ * Copyright (c) 2006-2008 Intel Corporation ++ * Copyright (c) 2007 Dave Airlie ++ * Copyright (C) 2011 Texas Instruments ++ * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. ++ * ++ * This program is free software and is provided to you under the terms of the ++ * GNU General Public License version 2 as published by the Free Software ++ * Foundation, and any use by you of this program is subject to the terms of ++ * such GNU licence. ++ * ++ */ ++ ++/** ++ * baikal_vdu_connector.c ++ * Implementation of the connector functions for Baikal Electronics BE-M1000 SoC's VDU ++ */ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "baikal_vdu_drm.h" ++#include "baikal_vdu_regs.h" ++ ++static void baikal_vdu_drm_connector_destroy(struct drm_connector *connector) ++{ ++ drm_connector_unregister(connector); ++ drm_connector_cleanup(connector); ++} ++ ++static enum drm_connector_status baikal_vdu_drm_connector_detect( ++ struct drm_connector *connector, bool force) ++{ ++ struct baikal_vdu_drm_connector *vdu_connector = ++ to_baikal_vdu_drm_connector(connector); ++ ++ return (vdu_connector->panel ? ++ connector_status_connected : ++ connector_status_disconnected); ++} ++ ++static int baikal_vdu_drm_connector_helper_get_modes( ++ struct drm_connector *connector) ++{ ++ struct baikal_vdu_drm_connector *vdu_connector = ++ to_baikal_vdu_drm_connector(connector); ++ ++ if (!vdu_connector) { ++ pr_err("%s: vdu_connector == NULL\n", __func__); ++ return 0; ++ } ++ if (!vdu_connector->panel) ++ return 0; ++ ++ return drm_panel_get_modes(vdu_connector->panel, connector); ++} ++ ++const struct drm_connector_funcs connector_funcs = { ++ .fill_modes = drm_helper_probe_single_connector_modes, ++ .destroy = baikal_vdu_drm_connector_destroy, ++ .detect = baikal_vdu_drm_connector_detect, ++ //.dpms = drm_atomic_helper_connector_dpms, // TODO enable it? ++ .reset = drm_atomic_helper_connector_reset, ++ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, ++}; ++ ++const struct drm_connector_helper_funcs connector_helper_funcs = { ++ .get_modes = baikal_vdu_drm_connector_helper_get_modes, ++}; ++ ++static const struct drm_encoder_funcs encoder_funcs = { ++ .destroy = drm_encoder_cleanup, ++}; ++ ++int baikal_vdu_connector_create(struct drm_device *dev) ++{ ++ struct baikal_vdu_private *priv = dev->dev_private; ++ struct baikal_vdu_drm_connector *vdu_connector = &priv->connector; ++ struct drm_connector *connector = &vdu_connector->connector; ++ ++ drm_connector_init(dev, connector, &connector_funcs, ++ DRM_MODE_CONNECTOR_LVDS); ++ drm_connector_helper_add(connector, &connector_helper_funcs); ++ return 0; ++} +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_crtc.c b/drivers/gpu/drm/baikal/baikal_vdu_crtc.c +new file mode 100644 +index 000000000000..6ef61791e299 +--- /dev/null ++++ b/drivers/gpu/drm/baikal/baikal_vdu_crtc.c +@@ -0,0 +1,310 @@ ++/* ++ * Copyright (C) 2019-2020 Baikal Electronics JSC ++ * ++ * Author: Pavel Parkhomenko ++ * ++ * Parts of this file were based on sources as follows: ++ * ++ * Copyright (c) 2006-2008 Intel Corporation ++ * Copyright (c) 2007 Dave Airlie ++ * Copyright (C) 2011 Texas Instruments ++ * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. ++ * ++ * This program is free software and is provided to you under the terms of the ++ * GNU General Public License version 2 as published by the Free Software ++ * Foundation, and any use by you of this program is subject to the terms of ++ * such GNU licence. ++ * ++ */ ++ ++/** ++ * baikal_vdu_crtc.c ++ * Implementation of the CRTC functions for Baikal Electronics BE-M1000 VDU driver ++ */ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "baikal_vdu_drm.h" ++#include "baikal_vdu_regs.h" ++ ++struct baikal_vdu_crtc_mode_fixup { ++ int vdisplay; ++ int vfp_add; ++}; ++ ++static const struct baikal_vdu_crtc_mode_fixup mode_fixups[] = { ++ { 480, 38 }, ++ { 600, 8 }, ++ { 720, 43 }, ++ { 768, 43 }, ++ { 800, 71 }, ++ { 864, 71 }, ++ { 900, 71 }, ++ { 960, 71 }, ++ { 1024, 25 }, ++ { 1050, 25 }, ++ { 1080, 8 }, ++ { 1200, 32 }, ++ { 1440, 27 }, ++ { ~0U }, ++}; ++ ++irqreturn_t baikal_vdu_irq(int irq, void *data) ++{ ++ struct drm_device *drm = data; ++ struct baikal_vdu_private *priv = drm->dev_private; ++ irqreturn_t status = IRQ_NONE; ++ u32 raw_stat; ++ u32 irq_stat; ++ ++ irq_stat = readl(priv->regs + IVR); ++ raw_stat = readl(priv->regs + ISR); ++ ++ if (irq_stat & INTR_VCT) { ++ priv->counters[10]++; ++ drm_crtc_handle_vblank(&priv->crtc); ++ status = IRQ_HANDLED; ++ } ++ ++ if (irq_stat & INTR_FER) { ++ priv->counters[11]++; ++ priv->counters[12] = readl(priv->regs + DBAR); ++ priv->counters[13] = readl(priv->regs + DCAR); ++ priv->counters[14] = readl(priv->regs + MRR); ++ status = IRQ_HANDLED; ++ } ++ ++ priv->counters[3] |= raw_stat; ++ ++ /* Clear all interrupts */ ++ writel(irq_stat, priv->regs + ISR); ++ ++ return status; ++} ++ ++bool baikal_vdu_crtc_mode_fixup(struct drm_crtc *crtc, ++ const struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode) ++{ ++ struct baikal_vdu_private *priv = crtc->dev->dev_private; ++ ++ memcpy(adjusted_mode, mode, sizeof(*mode)); ++ ++ if (!priv->mode_fixup) ++ return true; ++ ++ if (priv->mode_fixup == -1) { ++ const struct baikal_vdu_crtc_mode_fixup *fixups = mode_fixups; ++ for (; fixups && fixups->vdisplay != ~0U; ++fixups) { ++ if (mode->vdisplay <= fixups->vdisplay) ++ break; ++ } ++ if (fixups->vdisplay == ~0U) ++ return true; ++ else ++ priv->mode_fixup = fixups->vfp_add; ++ } ++ ++ adjusted_mode->vtotal += priv->mode_fixup; ++ adjusted_mode->vsync_start += priv->mode_fixup; ++ adjusted_mode->vsync_end += priv->mode_fixup; ++ adjusted_mode->clock = mode->clock * adjusted_mode->vtotal / mode->vtotal; ++ ++ return true; ++} ++ ++static void baikal_vdu_crtc_helper_mode_set_nofb(struct drm_crtc *crtc) ++{ ++ struct drm_device *dev = crtc->dev; ++ struct baikal_vdu_private *priv = dev->dev_private; ++ const struct drm_display_mode *orig_mode = &crtc->state->mode; ++ const struct drm_display_mode *mode = &crtc->state->adjusted_mode; ++ unsigned int ppl, hsw, hfp, hbp; ++ unsigned int lpp, vsw, vfp, vbp; ++ unsigned int reg; ++ ++ drm_mode_debug_printmodeline(orig_mode); ++ drm_mode_debug_printmodeline(mode); ++ ++ ppl = mode->hdisplay / 16; ++ hsw = mode->hsync_end - mode->hsync_start - 1; ++ hfp = mode->hsync_start - mode->hdisplay; ++ hbp = mode->htotal - mode->hsync_end; ++ ++ lpp = mode->vdisplay; ++ vsw = mode->vsync_end - mode->vsync_start; ++ vfp = mode->vsync_start - mode->vdisplay; ++ vbp = mode->vtotal - mode->vsync_end; ++ ++ writel((HTR_HFP(hfp) & HTR_HFP_MASK) | ++ (HTR_PPL(ppl) & HTR_PPL_MASK) | ++ (HTR_HBP(hbp) & HTR_HBP_MASK) | ++ (HTR_HSW(hsw) & HTR_HSW_MASK), ++ priv->regs + HTR); ++ ++ if (mode->hdisplay > 4080 || ppl * 16 != mode->hdisplay) ++ writel((HPPLOR_HPPLO(mode->hdisplay) & HPPLOR_HPPLO_MASK) | HPPLOR_HPOE, ++ priv->regs + HPPLOR); ++ ++ writel((VTR1_VSW(vsw) & VTR1_VSW_MASK) | ++ (VTR1_VFP(vfp) & VTR1_VFP_MASK) | ++ (VTR1_VBP(vbp) & VTR1_VBP_MASK), ++ priv->regs + VTR1); ++ ++ writel(lpp & VTR2_LPP_MASK, priv->regs + VTR2); ++ ++ writel((HVTER_VSWE(vsw >> VTR1_VSW_LSB_WIDTH) & HVTER_VSWE_MASK) | ++ (HVTER_HSWE(hsw >> HTR_HSW_LSB_WIDTH) & HVTER_HSWE_MASK) | ++ (HVTER_VBPE(vbp >> VTR1_VBP_LSB_WIDTH) & HVTER_VBPE_MASK) | ++ (HVTER_VFPE(vfp >> VTR1_VFP_LSB_WIDTH) & HVTER_VFPE_MASK) | ++ (HVTER_HBPE(hbp >> HTR_HBP_LSB_WIDTH) & HVTER_HBPE_MASK) | ++ (HVTER_HFPE(hfp >> HTR_HFP_LSB_WIDTH) & HVTER_HFPE_MASK), ++ priv->regs + HVTER); ++ ++ /* Set polarities */ ++ reg = readl(priv->regs + CR1); ++ if (mode->flags & DRM_MODE_FLAG_NHSYNC) ++ reg |= CR1_VSP; ++ else ++ reg &= ~CR1_VSP; ++ if (mode->flags & DRM_MODE_FLAG_NVSYNC) ++ reg |= CR1_HSP; ++ else ++ reg &= ~CR1_HSP; ++ reg |= CR1_DEP; // set DE to active high; ++ writel(reg, priv->regs + CR1); ++ ++ crtc->hwmode = crtc->state->adjusted_mode; ++} ++ ++static void baikal_vdu_crtc_helper_enable(struct drm_crtc *crtc, ++ struct drm_crtc_state *old_state) ++{ ++ struct baikal_vdu_private *priv = crtc->dev->dev_private; ++ u32 cntl; ++ ++ DRM_DEV_DEBUG_DRIVER(crtc->dev->dev, "enabling pixel clock\n"); ++ clk_prepare_enable(priv->clk); ++ ++ drm_panel_prepare(priv->connector.panel); ++ ++ writel(ISCR_VSC_VFP, priv->regs + ISCR); ++ ++ /* release clock reset; enable clocking */ ++ cntl = readl(priv->regs + PCTR); ++ cntl |= PCTR_PCR + PCTR_PCI; ++ writel(cntl, priv->regs + PCTR); ++ ++ /* Set 16-word input FIFO watermark and 24-bit LCD interface mode */ ++ /* Enable and Power Up */ ++ cntl = readl(priv->regs + CR1); ++ cntl |= CR1_LCE + CR1_FDW_16_WORDS + CR1_OPS_LCD24; ++ writel(cntl, priv->regs + CR1); ++ ++ drm_panel_enable(priv->connector.panel); ++ drm_crtc_vblank_on(crtc); ++} ++ ++void baikal_vdu_crtc_helper_disable(struct drm_crtc *crtc) ++{ ++ struct baikal_vdu_private *priv = crtc->dev->dev_private; ++ ++ drm_crtc_vblank_off(crtc); ++ drm_panel_disable(priv->connector.panel); ++ ++ /* Disable and Power Down */ ++ //writel(0, priv->regs + CR1); ++ ++ drm_panel_unprepare(priv->connector.panel); ++ ++ /* Disable clock */ ++ DRM_DEV_DEBUG_DRIVER(crtc->dev->dev, "disabling pixel clock\n"); ++ clk_disable_unprepare(priv->clk); ++} ++ ++static void baikal_vdu_crtc_helper_atomic_flush(struct drm_crtc *crtc, ++ struct drm_crtc_state *old_state) ++{ ++ struct drm_pending_vblank_event *event = crtc->state->event; ++ ++ if (event) { ++ crtc->state->event = NULL; ++ ++ spin_lock_irq(&crtc->dev->event_lock); ++ if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0) ++ drm_crtc_arm_vblank_event(crtc, event); ++ else ++ drm_crtc_send_vblank_event(crtc, event); ++ spin_unlock_irq(&crtc->dev->event_lock); ++ } ++} ++ ++static int baikal_vdu_enable_vblank(struct drm_crtc *crtc) ++{ ++ struct baikal_vdu_private *priv = crtc->dev->dev_private; ++ ++ //clk_prepare_enable(priv->clk); ++ ++ /* clear interrupt status */ ++ writel(0x3ffff, priv->regs + ISR); ++ ++ writel(INTR_VCT + INTR_FER, priv->regs + IMR); ++ ++ return 0; ++} ++ ++static void baikal_vdu_disable_vblank(struct drm_crtc *crtc) ++{ ++ struct baikal_vdu_private *priv = crtc->dev->dev_private; ++ ++ /* clear interrupt status */ ++ writel(0x3ffff, priv->regs + ISR); ++ ++ writel(INTR_FER, priv->regs + IMR); ++} ++ ++const struct drm_crtc_funcs crtc_funcs = { ++ .set_config = drm_atomic_helper_set_config, ++ .page_flip = drm_atomic_helper_page_flip, ++ .reset = drm_atomic_helper_crtc_reset, ++ .destroy = drm_crtc_cleanup, ++ .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, ++ .enable_vblank = baikal_vdu_enable_vblank, ++ .disable_vblank = baikal_vdu_disable_vblank, ++}; ++ ++const struct drm_crtc_helper_funcs crtc_helper_funcs = { ++ .mode_fixup = baikal_vdu_crtc_mode_fixup, ++ .mode_set_nofb = baikal_vdu_crtc_helper_mode_set_nofb, ++ .atomic_flush = baikal_vdu_crtc_helper_atomic_flush, ++ .disable = baikal_vdu_crtc_helper_disable, ++ .atomic_enable = baikal_vdu_crtc_helper_enable, ++}; ++ ++int baikal_vdu_crtc_create(struct drm_device *dev) ++{ ++ struct baikal_vdu_private *priv = dev->dev_private; ++ struct drm_crtc *crtc = &priv->crtc; ++ ++ drm_crtc_init_with_planes(dev, crtc, ++ &priv->primary, NULL, ++ &crtc_funcs, "primary"); ++ drm_crtc_helper_add(crtc, &crtc_helper_funcs); ++ ++ /* XXX: The runtime clock disabling still results in ++ * occasional system hangs, and needs debugging. ++ */ ++ ++ DRM_DEV_DEBUG_DRIVER(crtc->dev->dev, "enabling pixel clock\n"); ++ clk_prepare_enable(priv->clk); ++ ++ return 0; ++} +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_debugfs.c b/drivers/gpu/drm/baikal/baikal_vdu_debugfs.c +new file mode 100644 +index 000000000000..77be6aa588dc +--- /dev/null ++++ b/drivers/gpu/drm/baikal/baikal_vdu_debugfs.c +@@ -0,0 +1,87 @@ ++/* ++ * Copyright (C) 2019-2020 Baikal Electronics JSC ++ * ++ * Author: Pavel Parkhomenko ++ * ++ * Parts of this file were based on sources as follows: ++ * ++ * Copyright © 2017 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "baikal_vdu_drm.h" ++#include "baikal_vdu_regs.h" ++ ++#define REGDEF(reg) { reg, #reg } ++static const struct { ++ u32 reg; ++ const char *name; ++} baikal_vdu_reg_defs[] = { ++ REGDEF(CR1), ++ REGDEF(HTR), ++ REGDEF(VTR1), ++ REGDEF(VTR2), ++ REGDEF(PCTR), ++ REGDEF(ISR), ++ REGDEF(IMR), ++ REGDEF(IVR), ++ REGDEF(ISCR), ++ REGDEF(DBAR), ++ REGDEF(DCAR), ++ REGDEF(DEAR), ++ REGDEF(HVTER), ++ REGDEF(HPPLOR), ++ REGDEF(GPIOR), ++ REGDEF(OWER), ++ REGDEF(OWXSER0), ++ REGDEF(OWYSER0), ++ REGDEF(OWDBAR0), ++ REGDEF(OWDCAR0), ++ REGDEF(OWDEAR0), ++ REGDEF(OWXSER1), ++ REGDEF(OWYSER1), ++ REGDEF(OWDBAR1), ++ REGDEF(OWDCAR1), ++ REGDEF(OWDEAR1), ++ REGDEF(MRR), ++}; ++ ++int baikal_vdu_debugfs_regs(struct seq_file *m, void *unused) ++{ ++ struct drm_info_node *node = (struct drm_info_node *)m->private; ++ struct drm_device *dev = node->minor->dev; ++ struct baikal_vdu_private *priv = dev->dev_private; ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(baikal_vdu_reg_defs); i++) { ++ seq_printf(m, "%s (0x%04x): 0x%08x\n", ++ baikal_vdu_reg_defs[i].name, baikal_vdu_reg_defs[i].reg, ++ readl(priv->regs + baikal_vdu_reg_defs[i].reg)); ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(priv->counters); i++) { ++ seq_printf(m, "COUNTER[%d]: 0x%08x\n", i, priv->counters[i]); ++ } ++ ++ return 0; ++} ++ ++static const struct drm_info_list baikal_vdu_debugfs_list[] = { ++ {"regs", baikal_vdu_debugfs_regs, 0}, ++}; ++ ++void baikal_vdu_debugfs_init(struct drm_minor *minor) ++{ ++ drm_debugfs_create_files(baikal_vdu_debugfs_list, ++ ARRAY_SIZE(baikal_vdu_debugfs_list), ++ minor->debugfs_root, minor); ++} +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_drm.h b/drivers/gpu/drm/baikal/baikal_vdu_drm.h +new file mode 100644 +index 000000000000..d049335dab1d +--- /dev/null ++++ b/drivers/gpu/drm/baikal/baikal_vdu_drm.h +@@ -0,0 +1,95 @@ ++/* ++ * Copyright (C) 2019-2020 Baikal Electronics JSC ++ * ++ * Author: Pavel Parkhomenko ++ * ++ * Parts of this file were based on sources as follows: ++ * ++ * Copyright (c) 2006-2008 Intel Corporation ++ * Copyright (c) 2007 Dave Airlie ++ * Copyright (C) 2011 Texas Instruments ++ * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. ++ * ++ * This program is free software and is provided to you under the terms of the ++ * GNU General Public License version 2 as published by the Free Software ++ * Foundation, and any use by you of this program is subject to the terms of ++ * such GNU licence. ++ * ++ */ ++ ++#ifndef __BAIKAL_VDU_DRM_H__ ++#define __BAIKAL_VDU_DRM_H__ ++ ++#include ++#include ++#include ++ ++struct clk; ++struct drm_device; ++struct drm_fbdev_cma; ++struct drm_panel; ++ ++/*struct baikal_vdu_framebuffer { ++ u32 base; ++ u32 size; ++ u32 index; ++ u32 reg_base; ++ u32 reg_size; ++ u32 reg_width; ++ u32 reg_height; ++};*/ ++ ++struct baikal_vdu_drm_connector { ++ struct drm_connector connector; ++ struct drm_panel *panel; ++}; ++ ++struct baikal_vdu_private { ++ struct drm_device *drm; ++ ++ struct baikal_vdu_drm_connector connector; ++ struct drm_crtc crtc; ++ struct drm_encoder encoder; ++ struct drm_bridge *bridge; ++ struct drm_plane primary; ++ ++ void *regs; ++ struct clk *clk; ++ spinlock_t lock; ++ u32 counters[20]; ++ int mode_fixup; ++ ++ u32 fb_addr; ++ u32 fb_end; ++ ++ struct delayed_work update_work; ++}; ++ ++#define to_baikal_vdu_drm_connector(x) \ ++ container_of(x, struct baikal_vdu_drm_connector, connector) ++ ++extern const struct drm_encoder_funcs baikal_vdu_encoder_funcs; ++ ++/* CRTC Functions */ ++int baikal_vdu_crtc_create(struct drm_device *dev); ++irqreturn_t baikal_vdu_irq(int irq, void *data); ++ ++int baikal_vdu_primary_plane_init(struct drm_device *dev); ++ ++/* Connector Functions */ ++int baikal_vdu_connector_create(struct drm_device *dev); ++ ++/* Encoder Functions */ ++int baikal_vdu_encoder_init(struct drm_device *dev); ++ ++/* GEM Functions */ ++int baikal_vdu_dumb_create(struct drm_file *file_priv, ++ struct drm_device *dev, ++ struct drm_mode_create_dumb *args); ++ ++void baikal_vdu_debugfs_init(struct drm_minor *minor); ++ ++/* Worker functions */ ++void baikal_vdu_update_work(struct work_struct *work); ++ ++#endif /* __BAIKAL_VDU_DRM_H__ */ +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_drv.c b/drivers/gpu/drm/baikal/baikal_vdu_drv.c +new file mode 100644 +index 000000000000..0caa97dcb2e9 +--- /dev/null ++++ b/drivers/gpu/drm/baikal/baikal_vdu_drv.c +@@ -0,0 +1,310 @@ ++/* ++ * Copyright (C) 2019-2020 Baikal Electronics JSC ++ * ++ * Author: Pavel Parkhomenko ++ * All bugs by Alexey Sheplyakov ++ * ++ * This driver is based on ARM PL111 DRM driver ++ * ++ * Parts of this file were based on sources as follows: ++ * ++ * Copyright (c) 2006-2008 Intel Corporation ++ * Copyright (c) 2007 Dave Airlie ++ * Copyright (C) 2011 Texas Instruments ++ * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. ++ * ++ * This program is free software and is provided to you under the terms of the ++ * GNU General Public License version 2 as published by the Free Software ++ * Foundation, and any use by you of this program is subject to the terms of ++ * such GNU licence. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "baikal_vdu_drm.h" ++#include "baikal_vdu_regs.h" ++ ++#define DRIVER_NAME "baikal-vdu" ++#define DRIVER_DESC "DRM module for Baikal VDU" ++#define DRIVER_DATE "20200131" ++ ++#define BAIKAL_SMC_SCP_LOG_DISABLE 0x82000200 ++ ++int mode_fixup = 0; ++ ++static struct drm_mode_config_funcs mode_config_funcs = { ++ .fb_create = drm_gem_fb_create, ++ .atomic_check = drm_atomic_helper_check, ++ .atomic_commit = drm_atomic_helper_commit, ++}; ++ ++static int vdu_modeset_init(struct drm_device *dev) ++{ ++ struct drm_mode_config *mode_config; ++ struct baikal_vdu_private *priv = dev->dev_private; ++ struct arm_smccc_res res; ++ int ret = 0; ++ ++ if (priv == NULL) ++ return -EINVAL; ++ ++ drm_mode_config_init(dev); ++ mode_config = &dev->mode_config; ++ mode_config->funcs = &mode_config_funcs; ++ mode_config->min_width = 1; ++ mode_config->max_width = 4096; ++ mode_config->min_height = 1; ++ mode_config->max_height = 4096; ++ ++ ret = baikal_vdu_primary_plane_init(dev); ++ if (ret != 0) { ++ dev_err(dev->dev, "Failed to init primary plane\n"); ++ goto out_config; ++ } ++ ++ ret = baikal_vdu_crtc_create(dev); ++ if (ret) { ++ dev_err(dev->dev, "Failed to create crtc\n"); ++ goto out_config; ++ } ++ ++ ret = drm_of_find_panel_or_bridge(dev->dev->of_node, -1, -1, ++ &priv->connector.panel, ++ &priv->bridge); ++ if (ret == -EPROBE_DEFER) { ++ dev_info(dev->dev, "Bridge probe deferred\n"); ++ goto out_config; ++ } ++ ++ ret = baikal_vdu_encoder_init(dev); ++ if (ret) { ++ dev_err(dev->dev, "Failed to create DRM encoder\n"); ++ goto out_config; ++ } ++ ++ if (priv->bridge) { ++ priv->bridge->encoder = &priv->encoder; ++ ret = drm_bridge_attach(&priv->encoder, priv->bridge, NULL, 0); ++ if (ret) { ++ dev_err(dev->dev, "Failed to attach DRM bridge %d\n", ret); ++ goto out_config; ++ } ++ } else if (priv->connector.panel) { ++ ret = baikal_vdu_connector_create(dev); ++ if (ret) { ++ dev_err(dev->dev, "Failed to create DRM connector\n"); ++ goto out_config; ++ } ++ ret = drm_connector_attach_encoder(&priv->connector.connector, ++ &priv->encoder); ++ if (ret != 0) { ++ dev_err(dev->dev, "Failed to attach encoder\n"); ++ goto out_config; ++ } ++ } else ++ ret = -EINVAL; ++ ++ if (ret) { ++ dev_err(dev->dev, "No bridge or panel attached!\n"); ++ goto out_config; ++ } ++ ++ priv->clk = clk_get(dev->dev, "pclk"); ++ if (IS_ERR(priv->clk)) { ++ dev_err(dev->dev, "fatal: unable to get pclk, err %ld\n", PTR_ERR(priv->clk)); ++ ret = PTR_ERR(priv->clk); ++ goto out_config; ++ } ++ ++ priv->mode_fixup = mode_fixup; ++ ++ drm_fb_helper_remove_conflicting_framebuffers(NULL, "baikal-vdudrmfb", false); ++ ++ ret = drm_vblank_init(dev, 1); ++ if (ret != 0) { ++ dev_err(dev->dev, "Failed to init vblank\n"); ++ goto out_clk; ++ } ++ ++ arm_smccc_smc(BAIKAL_SMC_SCP_LOG_DISABLE, 0, 0, 0, 0, 0, 0, 0, &res); ++ INIT_DEFERRABLE_WORK(&priv->update_work, ++ baikal_vdu_update_work); ++ ++ drm_mode_config_reset(dev); ++ ++ drm_kms_helper_poll_init(dev); ++ ++ ret = drm_dev_register(dev, 0); ++ if (ret) ++ goto out_clk; ++ ++ drm_fbdev_generic_setup(dev, 32); ++ goto finish; ++ ++out_clk: ++ clk_put(priv->clk); ++out_config: ++ drm_mode_config_cleanup(dev); ++finish: ++ return ret; ++} ++ ++static const struct file_operations drm_fops = { ++ .owner = THIS_MODULE, ++ .open = drm_open, ++ .release = drm_release, ++ .unlocked_ioctl = drm_ioctl, ++ .mmap = drm_gem_cma_mmap, ++ .poll = drm_poll, ++ .read = drm_read, ++}; ++ ++static struct drm_driver vdu_drm_driver = { ++ .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | ++ DRIVER_MODESET | DRIVER_ATOMIC, ++ .irq_handler = baikal_vdu_irq, ++ .ioctls = NULL, ++ .fops = &drm_fops, ++ .name = DRIVER_NAME, ++ .desc = DRIVER_DESC, ++ .date = DRIVER_DATE, ++ .major = 1, ++ .minor = 0, ++ .patchlevel = 0, ++ .dumb_create = baikal_vdu_dumb_create, ++ .gem_create_object = drm_gem_cma_create_object_default_funcs, ++ .prime_handle_to_fd = drm_gem_prime_handle_to_fd, ++ .prime_fd_to_handle = drm_gem_prime_fd_to_handle, ++ .gem_prime_import = drm_gem_prime_import, ++ .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, ++ .gem_prime_export = drm_gem_prime_export, ++ .gem_prime_mmap = drm_gem_cma_prime_mmap, ++#if defined(CONFIG_DEBUG_FS) ++ .debugfs_init = baikal_vdu_debugfs_init, ++#endif ++}; ++ ++static int baikal_vdu_drm_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct baikal_vdu_private *priv; ++ struct drm_device *drm; ++ struct resource *mem; ++ int irq; ++ int ret; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ drm = drm_dev_alloc(&vdu_drm_driver, dev); ++ if (IS_ERR(drm)) ++ return PTR_ERR(drm); ++ platform_set_drvdata(pdev, drm); ++ priv->drm = drm; ++ drm->dev_private = priv; ++ ++ if (!(mem = platform_get_resource(pdev, IORESOURCE_MEM, 0))) { ++ dev_err(dev, "%s no MMIO resource specified\n", __func__); ++ return -EINVAL; ++ } ++ ++ priv->regs = devm_ioremap_resource(dev, mem); ++ if (IS_ERR(priv->regs)) { ++ dev_err(dev, "%s MMIO allocation failed\n", __func__); ++ return PTR_ERR(priv->regs); ++ } ++ ++ /* turn off interrupts before requesting the irq */ ++ writel(0, priv->regs + IMR); ++ ++ if (!(irq = platform_get_irq(pdev, 0))) { ++ dev_err(dev, "%s no IRQ resource specified\n", __func__); ++ return -EINVAL; ++ } ++ ++ spin_lock_init(&priv->lock); ++ ++ ret = drm_irq_install(drm, irq); ++ if (ret != 0) { ++ dev_err(dev, "%s IRQ %d allocation failed\n", __func__, irq); ++ return ret; ++ } ++ ++ ret = vdu_modeset_init(drm); ++ if (ret != 0) { ++ dev_err(dev, "Failed to init modeset\n"); ++ goto dev_unref; ++ } ++ ++ return 0; ++ ++dev_unref: ++ drm_irq_uninstall(drm); ++ drm->dev_private = NULL; ++ drm_dev_put(drm); ++ return ret; ++} ++ ++static int baikal_vdu_drm_remove(struct platform_device *pdev) ++{ ++ struct drm_device *drm = platform_get_drvdata(pdev); ++ ++ drm_dev_unregister(drm); ++ drm_mode_config_cleanup(drm); ++ drm_irq_uninstall(drm); ++ drm->dev_private = NULL; ++ drm_dev_put(drm); ++ ++ return 0; ++} ++ ++static const struct of_device_id baikal_vdu_of_match[] = { ++ { .compatible = "baikal,vdu" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, baikal_vdu_of_match); ++ ++static struct platform_driver baikal_vdu_platform_driver = { ++ .probe = baikal_vdu_drm_probe, ++ .remove = baikal_vdu_drm_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .of_match_table = baikal_vdu_of_match, ++ }, ++}; ++ ++module_param(mode_fixup, int, 0644); ++ ++module_platform_driver(baikal_vdu_platform_driver); ++ ++MODULE_AUTHOR("Pavel Parkhomenko "); ++MODULE_DESCRIPTION("Baikal Electronics BE-M1000 Video Display Unit (VDU) DRM Driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:" DRIVER_NAME); ++MODULE_SOFTDEP("pre: baikal_hdmi"); +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_encoder.c b/drivers/gpu/drm/baikal/baikal_vdu_encoder.c +new file mode 100644 +index 000000000000..9081d196dac3 +--- /dev/null ++++ b/drivers/gpu/drm/baikal/baikal_vdu_encoder.c +@@ -0,0 +1,51 @@ ++/* ++ * Copyright (C) 2019-2020 Baikal Electronics JSC ++ * ++ * Author: Pavel Parkhomenko ++ * ++ * Parts of this file were based on sources as follows: ++ * ++ * Copyright (c) 2006-2008 Intel Corporation ++ * Copyright (c) 2007 Dave Airlie ++ * Copyright (C) 2011 Texas Instruments ++ * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. ++ * ++ * This program is free software and is provided to you under the terms of the ++ * GNU General Public License version 2 as published by the Free Software ++ * Foundation, and any use by you of this program is subject to the terms of ++ * such GNU licence. ++ * ++ */ ++ ++/** ++ * baikal_vdu_encoder.c ++ * Implementation of the encoder functions for Baikal Electronics BE-M1000 VDU driver ++ */ ++#include ++#include ++#include ++ ++#include ++ ++#include "baikal_vdu_drm.h" ++ ++const struct drm_encoder_funcs baikal_vdu_encoder_funcs = { ++ .destroy = drm_encoder_cleanup, ++}; ++ ++int baikal_vdu_encoder_init(struct drm_device *dev) ++{ ++ struct baikal_vdu_private *priv = dev->dev_private; ++ struct drm_encoder *encoder = &priv->encoder; ++ int ret; ++ ++ ret = drm_encoder_init(dev, encoder, &baikal_vdu_encoder_funcs, ++ DRM_MODE_ENCODER_NONE, NULL); ++ if (ret) ++ return ret; ++ ++ encoder->crtc = &priv->crtc; ++ encoder->possible_crtcs = BIT(drm_crtc_index(encoder->crtc)); ++ ++ return 0; ++} +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_gem.c b/drivers/gpu/drm/baikal/baikal_vdu_gem.c +new file mode 100644 +index 000000000000..b07566caf12c +--- /dev/null ++++ b/drivers/gpu/drm/baikal/baikal_vdu_gem.c +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (C) 2019-2020 Baikal Electronics JSC ++ * ++ * Author: Pavel Parkhomenko ++ * ++ * Parts of this file were based on sources as follows: ++ * ++ * Copyright (c) 2006-2008 Intel Corporation ++ * Copyright (c) 2007 Dave Airlie ++ * Copyright (C) 2011 Texas Instruments ++ * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. ++ * ++ * This program is free software and is provided to you under the terms of the ++ * GNU General Public License version 2 as published by the Free Software ++ * Foundation, and any use by you of this program is subject to the terms of ++ * such GNU licence. ++ * ++ */ ++ ++/** ++ * baikal_vdu_gem.c ++ * Implementation of the GEM functions for Baikal Electronics BE-M1000 VDU driver ++ */ ++#include ++#include ++#include ++#include ++#include ++#include "baikal_vdu_drm.h" ++ ++int baikal_vdu_dumb_create(struct drm_file *file_priv, ++ struct drm_device *dev, struct drm_mode_create_dumb *args) ++{ ++ args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8); ++ ++ return drm_gem_cma_dumb_create_internal(file_priv, dev, args); ++} +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_plane.c b/drivers/gpu/drm/baikal/baikal_vdu_plane.c +new file mode 100644 +index 000000000000..9817af3c6de8 +--- /dev/null ++++ b/drivers/gpu/drm/baikal/baikal_vdu_plane.c +@@ -0,0 +1,233 @@ ++/* ++ * Copyright (C) 2019-2020 Baikal Electronics JSC ++ * ++ * Author: Pavel Parkhomenko ++ * ++ * Parts of this file were based on sources as follows: ++ * ++ * Copyright (c) 2006-2008 Intel Corporation ++ * Copyright (c) 2007 Dave Airlie ++ * Copyright (C) 2011 Texas Instruments ++ * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. ++ * ++ * This program is free software and is provided to you under the terms of the ++ * GNU General Public License version 2 as published by the Free Software ++ * Foundation, and any use by you of this program is subject to the terms of ++ * such GNU licence. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "baikal_vdu_drm.h" ++#include "baikal_vdu_regs.h" ++ ++#define BAIKAL_SMC_VDU_UPDATE_HDMI 0x82000100 ++ ++void baikal_vdu_update_work(struct work_struct *work) ++{ ++ struct arm_smccc_res res; ++ unsigned long flags; ++ struct baikal_vdu_private *priv = container_of(work, struct baikal_vdu_private, ++ update_work.work); ++ int count = 0; ++ u64 t1, t2; ++ t1 = read_sysreg(CNTVCT_EL0); ++ spin_lock_irqsave(&priv->lock, flags); ++ arm_smccc_smc(BAIKAL_SMC_VDU_UPDATE_HDMI, priv->fb_addr, priv->fb_end, 0, 0, 0, 0, 0, &res); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ if (res.a0 == -EBUSY) ++ priv->counters[15]++; ++ else ++ priv->counters[16]++; ++ while (res.a0 == -EBUSY && count < 10) { ++ count++; ++ usleep_range(10000, 20000); ++ res.a0 = 0; ++ spin_lock_irqsave(&priv->lock, flags); ++ arm_smccc_smc(BAIKAL_SMC_VDU_UPDATE_HDMI, priv->fb_addr, priv->fb_end, 0, 0, 0, 0, 0, &res); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ if (res.a0 == -EBUSY) ++ priv->counters[15]++; ++ else ++ priv->counters[16]++; ++ } ++ t2 = read_sysreg(CNTVCT_EL0); ++ priv->counters[17] = t2 - t1; ++ priv->counters[18] = count; ++ priv->counters[19]++; ++} ++ ++static int baikal_vdu_primary_plane_atomic_check(struct drm_plane *plane, ++ struct drm_plane_state *state) ++{ ++ struct drm_device *dev = plane->dev; ++ struct baikal_vdu_private *priv = dev->dev_private; ++ struct drm_crtc_state *crtc_state; ++ struct drm_display_mode *mode; ++ int rate, ret; ++ ++ if (!state->crtc) ++ return 0; ++ ++ crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); ++ mode = &crtc_state->adjusted_mode; ++ rate = mode->clock * 1000; ++ if (rate == clk_get_rate(priv->clk)) ++ return 0; ++ ++ if (__clk_is_enabled(priv->clk)) ++ clk_disable_unprepare(priv->clk); ++ ret = clk_set_rate(priv->clk, rate); ++ DRM_DEV_DEBUG_DRIVER(dev->dev, "Requested pixel clock is %d Hz\n", rate); ++ ++ if (ret < 0) { ++ DRM_ERROR("Cannot set desired pixel clock (%d Hz)\n", ++ rate); ++ return -EINVAL; ++ } ++ clk_prepare_enable(priv->clk); ++ if (!__clk_is_enabled(priv->clk)) { ++ DRM_ERROR("PLL could not lock at desired frequency (%d Hz)\n", ++ rate); ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++static void baikal_vdu_primary_plane_atomic_update(struct drm_plane *plane, ++ struct drm_plane_state *old_state) ++{ ++ struct drm_device *dev = plane->dev; ++ struct baikal_vdu_private *priv = dev->dev_private; ++ struct drm_plane_state *state = plane->state; ++ struct drm_framebuffer *fb = state->fb; ++ struct arm_smccc_res res; ++ u32 cntl, addr, end; ++ unsigned long flags; ++ ++ if (!fb) ++ return; ++ ++ addr = drm_fb_cma_get_gem_addr(fb, state, 0); ++ end = ((addr + fb->height * fb->pitches[0] - 1) & MRR_DEAR_MRR_MASK) | MRR_OUTSTND_RQ(4); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ arm_smccc_smc(BAIKAL_SMC_VDU_UPDATE_HDMI, addr, end, 0, 0, 0, 0, 0, &res); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ if (res.a0 == -EBUSY) { ++ priv->counters[15]++; ++ priv->fb_addr = addr; ++ priv->fb_end = end; ++ smp_wmb(); ++ schedule_delayed_work(&priv->update_work, usecs_to_jiffies(250)); ++ } else ++ priv->counters[16]++; ++ ++ cntl = readl(priv->regs + CR1); ++ cntl &= ~CR1_BPP_MASK; ++ ++ /* Note that the the hardware's format reader takes 'r' from ++ * the low bit, while DRM formats list channels from high bit ++ * to low bit as you read left to right. ++ */ ++ switch (fb->format->format) { ++ case DRM_FORMAT_BGR888: ++ cntl |= CR1_BPP24 | CR1_FBP | CR1_BGR; ++ break; ++ case DRM_FORMAT_RGB888: ++ cntl |= CR1_BPP24 | CR1_FBP; ++ break; ++ case DRM_FORMAT_ABGR8888: ++ case DRM_FORMAT_XBGR8888: ++ cntl |= CR1_BPP24 | CR1_BGR; ++ break; ++ case DRM_FORMAT_ARGB8888: ++ case DRM_FORMAT_XRGB8888: ++ cntl |= CR1_BPP24; ++ break; ++ case DRM_FORMAT_BGR565: ++ cntl |= CR1_BPP16_565 | CR1_BGR; ++ break; ++ case DRM_FORMAT_RGB565: ++ cntl |= CR1_BPP16_565; ++ break; ++ case DRM_FORMAT_ABGR1555: ++ case DRM_FORMAT_XBGR1555: ++ cntl |= CR1_BPP16_555 | CR1_BGR; ++ break; ++ case DRM_FORMAT_ARGB1555: ++ case DRM_FORMAT_XRGB1555: ++ cntl |= CR1_BPP16_555; ++ break; ++ default: ++ WARN_ONCE(true, "Unknown FB format 0x%08x, set XRGB8888 instead\n", ++ fb->format->format); ++ cntl |= CR1_BPP24; ++ break; ++ } ++ ++ writel(cntl, priv->regs + CR1); ++} ++ ++static const struct drm_plane_helper_funcs baikal_vdu_primary_plane_helper_funcs = { ++ .atomic_check = baikal_vdu_primary_plane_atomic_check, ++ .atomic_update = baikal_vdu_primary_plane_atomic_update, ++}; ++ ++static const struct drm_plane_funcs baikal_vdu_primary_plane_funcs = { ++ .update_plane = drm_atomic_helper_update_plane, ++ .disable_plane = drm_atomic_helper_disable_plane, ++ .reset = drm_atomic_helper_plane_reset, ++ .destroy = drm_plane_cleanup, ++ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, ++}; ++ ++int baikal_vdu_primary_plane_init(struct drm_device *drm) ++{ ++ struct baikal_vdu_private *priv = drm->dev_private; ++ struct drm_plane *plane = &priv->primary; ++ static const u32 formats[] = { ++ DRM_FORMAT_BGR888, ++ DRM_FORMAT_RGB888, ++ DRM_FORMAT_ABGR8888, ++ DRM_FORMAT_XBGR8888, ++ DRM_FORMAT_ARGB8888, ++ DRM_FORMAT_XRGB8888, ++ DRM_FORMAT_BGR565, ++ DRM_FORMAT_RGB565, ++ DRM_FORMAT_ABGR1555, ++ DRM_FORMAT_XBGR1555, ++ DRM_FORMAT_ARGB1555, ++ DRM_FORMAT_XRGB1555, ++ }; ++ int ret; ++ ++ ret = drm_universal_plane_init(drm, plane, 0, ++ &baikal_vdu_primary_plane_funcs, ++ formats, ++ ARRAY_SIZE(formats), ++ NULL, ++ DRM_PLANE_TYPE_PRIMARY, ++ NULL); ++ if (ret) ++ return ret; ++ ++ drm_plane_helper_add(plane, &baikal_vdu_primary_plane_helper_funcs); ++ ++ return 0; ++} ++ ++ +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_regs.h b/drivers/gpu/drm/baikal/baikal_vdu_regs.h +new file mode 100644 +index 000000000000..a0d8e69eb5e6 +--- /dev/null ++++ b/drivers/gpu/drm/baikal/baikal_vdu_regs.h +@@ -0,0 +1,146 @@ ++/* ++ * Copyright (C) 2019-2020 Baikal Electronics JSC ++ * ++ * Author: Pavel Parkhomenko ++ * ++ * Parts of this file were based on sources as follows: ++ * ++ * David A Rusling ++ * Copyright (C) 2001 ARM Limited ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++ ++#ifndef __BAIKAL_VDU_REGS_H__ ++#define __BAIKAL_VDU_REGS_H__ ++ ++#define CR1 0x000 ++#define HTR 0x008 ++#define VTR1 0x00C ++#define VTR2 0x010 ++#define PCTR 0x014 ++#define ISR 0x018 ++#define IMR 0x01C ++#define IVR 0x020 ++#define ISCR 0x024 ++#define DBAR 0x028 ++#define DCAR 0x02C ++#define DEAR 0x030 ++#define HVTER 0x044 ++#define HPPLOR 0x048 ++#define GPIOR 0x1F8 ++#define OWER 0x600 ++#define OWXSER0 0x604 ++#define OWYSER0 0x608 ++#define OWDBAR0 0x60C ++#define OWDCAR0 0x610 ++#define OWDEAR0 0x614 ++#define OWXSER1 0x618 ++#define OWYSER1 0x61C ++#define OWDBAR1 0x620 ++#define OWDCAR1 0x624 ++#define OWDEAR1 0x628 ++#define MRR 0xFFC ++ ++#define INTR_BAU BIT(7) ++#define INTR_VCT BIT(6) ++#define INTR_MBE BIT(5) ++#define INTR_FER BIT(4) ++ ++#define CR1_FBP BIT(19) ++#define CR1_FDW_4_WORDS (0 << 16) ++#define CR1_FDW_8_WORDS (1 << 16) ++#define CR1_FDW_16_WORDS (2 << 16) ++#define CR1_OPS_LCD18 (0 << 13) ++#define CR1_OPS_LCD24 (1 << 13) ++#define CR1_OPS_565 (0 << 12) ++#define CR1_OPS_555 (1 << 12) ++#define CR1_VSP BIT(11) ++#define CR1_HSP BIT(10) ++#define CR1_DEP BIT(8) ++#define CR1_BGR BIT(5) ++#define CR1_BPP_MASK GENMASK(4, 2) ++#define CR1_BPP1 (0 << 2) ++#define CR1_BPP2 (1 << 2) ++#define CR1_BPP4 (2 << 2) ++#define CR1_BPP8 (3 << 2) ++#define CR1_BPP16 (4 << 2) ++#define CR1_BPP18 (5 << 2) ++#define CR1_BPP24 (6 << 2) ++#define CR1_LCE BIT(0) ++ ++#define CR1_BPP16_555 ((CR1_BPP16) | (CR1_OPS_555)) ++#define CR1_BPP16_565 ((CR1_BPP16) | (CR1_OPS_565)) ++ ++#define VTR1_VBP_MASK GENMASK(23, 16) ++#define VTR1_VBP(x) ((x) << 16) ++#define VTR1_VBP_LSB_WIDTH 8 ++#define VTR1_VFP_MASK GENMASK(15, 8) ++#define VTR1_VFP(x) ((x) << 8) ++#define VTR1_VFP_LSB_WIDTH 8 ++#define VTR1_VSW_MASK GENMASK(7, 0) ++#define VTR1_VSW(x) ((x) << 0) ++#define VTR1_VSW_LSB_WIDTH 8 ++ ++#define VTR2_LPP_MASK GENMASK(11, 0) ++ ++#define HTR_HSW_MASK GENMASK(31, 24) ++#define HTR_HSW(x) ((x) << 24) ++#define HTR_HSW_LSB_WIDTH 8 ++#define HTR_HBP_MASK GENMASK(23, 16) ++#define HTR_HBP(x) ((x) << 16) ++#define HTR_HBP_LSB_WIDTH 8 ++#define HTR_PPL_MASK GENMASK(15, 8) ++#define HTR_PPL(x) ((x) << 8) ++#define HTR_HFP_MASK GENMASK(7, 0) ++#define HTR_HFP(x) ((x) << 0) ++#define HTR_HFP_LSB_WIDTH 8 ++ ++#define PCTR_PCI2 BIT(11) ++#define PCTR_PCR BIT(10) ++#define PCTR_PCI BIT(9) ++#define PCTR_PCB BIT(8) ++#define PCTR_PCD_MASK GENMASK(7, 0) ++#define PCTR_MAX_PCD 128 ++ ++#define ISCR_VSC_OFF 0x0 ++#define ISCR_VSC_VSW 0x4 ++#define ISCR_VSC_VBP 0x5 ++#define ISCR_VSC_VACTIVE 0x6 ++#define ISCR_VSC_VFP 0x7 ++ ++#define HVTER_VSWE_MASK GENMASK(25, 24) ++#define HVTER_VSWE(x) ((x) << 24) ++#define HVTER_HSWE_MASK GENMASK(17, 16) ++#define HVTER_HSWE(x) ((x) << 16) ++#define HVTER_VBPE_MASK GENMASK(13, 12) ++#define HVTER_VBPE(x) ((x) << 12) ++#define HVTER_VFPE_MASK GENMASK(9, 8) ++#define HVTER_VFPE(x) ((x) << 8) ++#define HVTER_HBPE_MASK GENMASK(5, 4) ++#define HVTER_HBPE(x) ((x) << 4) ++#define HVTER_HFPE_MASK GENMASK(1, 0) ++#define HVTER_HFPE(x) ((x) << 0) ++ ++#define HPPLOR_HPOE BIT(31) ++#define HPPLOR_HPPLO_MASK GENMASK(11, 0) ++#define HPPLOR_HPPLO(x) ((x) << 0) ++ ++#define GPIOR_UHD_MASK GENMASK(23, 16) ++#define GPIOR_UHD_FMT_LDI (0 << 20) ++#define GPIOR_UHD_FMT_VESA (1 << 20) ++#define GPIOR_UHD_FMT_JEIDA (2 << 20) ++#define GPIOR_UHD_SNGL_PORT (0 << 18) ++#define GPIOR_UHD_DUAL_PORT (1 << 18) ++#define GPIOR_UHD_QUAD_PORT (2 << 18) ++#define GPIOR_UHD_ENB BIT(17) ++#define GPIOR_UHD_PIX_INTLV (0 << 16) ++#define GPIOR_UHD_PIX_SQNTL (1 << 16) ++ ++#define MRR_DEAR_MRR_MASK GENMASK(31, 3) ++#define MRR_OUTSTND_RQ_MASK GENMASK(2, 0) ++#define MRR_OUTSTND_RQ(x) ((x >> 1) << 0) ++ ++#endif /* __BAIKAL_VDU_REGS_H__ */ +diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig +index e145cbb35bac..c9050ac41215 100644 +--- a/drivers/gpu/drm/bridge/Kconfig ++++ b/drivers/gpu/drm/bridge/Kconfig +@@ -71,6 +71,13 @@ config DRM_LVDS_CODEC + Support for transparent LVDS encoders and decoders that don't + require any configuration. + ++config DRM_BAIKAL_HDMI ++ tristate "Baikal-M HDMI transmitter" ++ default y if ARCH_BAIKAL ++ select DRM_DW_HDMI ++ help ++ Choose this if you want to use HDMI on Baikal-M. ++ + config DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW + tristate "MegaChips stdp4028-ge-b850v3-fw and stdp2690-ge-b850v3-fw" + depends on OF +-- +2.31.1 + diff --git a/0610-Added-Baikal-T1-M-BMC-driver.patch b/0610-Added-Baikal-T1-M-BMC-driver.patch new file mode 100644 index 0000000..b2db012 --- /dev/null +++ b/0610-Added-Baikal-T1-M-BMC-driver.patch @@ -0,0 +1,810 @@ +From 11c1cbda8ed87683a6a058e1991e1bb5f8379d04 Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Tue, 9 Jun 2020 10:37:23 +0400 +Subject: [PATCH 610/625] Added Baikal-T1/M BMC driver + +The BMC device is responsible for CPU kick-starting, controlling +power button, and a full board poweroff. + +(cherry picked from commit 53d167c426d92ca9df319924a107e8cd62cd96b1) +--- + drivers/misc/Kconfig | 18 + + drivers/misc/Makefile | 1 + + drivers/misc/tp_bmc.c | 747 ++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 766 insertions(+) + create mode 100644 drivers/misc/tp_bmc.c + +diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig +index fafa8b0d8099..00368637ede0 100644 +--- a/drivers/misc/Kconfig ++++ b/drivers/misc/Kconfig +@@ -466,6 +466,24 @@ config HISI_HIKEY_USB + switching between the dual-role USB-C port and the USB-A host ports + using only one USB controller. + ++config TP_BMC ++ tristate "T-platforms Baikal-T(1)/M BMC" ++ depends on I2C && SYSFS ++ depends on OF ++ select PINCTRL ++ select GENERIC_PINCONF ++ select SERIO ++ default y if ARCH_BAIKAL ++ help ++ Say Y here if you want to build a driver for T-platforms BMC devices ++ embedded into the boards with Baikal-T(1)/M processors. The device main ++ purpose is the CPU kick-starting as well as some additional side-way ++ functionality like power on/off buttons state tracing and full device ++ powering off. ++ ++ If you choose to build module, its name will be tp-bmc. If unsure, ++ say N here. ++ + source "drivers/misc/c2port/Kconfig" + source "drivers/misc/eeprom/Kconfig" + source "drivers/misc/cb710/Kconfig" +diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile +index d23231e73330..f60e5079a6fb 100644 +--- a/drivers/misc/Makefile ++++ b/drivers/misc/Makefile +@@ -57,3 +57,4 @@ obj-$(CONFIG_HABANA_AI) += habanalabs/ + obj-$(CONFIG_UACCE) += uacce/ + obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o + obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o ++obj-$(CONFIG_TP_BMC) += tp_bmc.o +diff --git a/drivers/misc/tp_bmc.c b/drivers/misc/tp_bmc.c +new file mode 100644 +index 000000000000..0b320d3ffae4 +--- /dev/null ++++ b/drivers/misc/tp_bmc.c +@@ -0,0 +1,747 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++enum I2C_REGS { ++ R_ID1 = 0, ++ R_ID2, ++ R_ID3, ++ R_ID4, ++ R_SOFTOFF_RQ, ++ R_PWROFF_RQ, ++ R_PWRBTN_STATE, ++ R_VERSION1, ++ R_VERSION2, ++ R_BOOTREASON, ++ R_BOOTREASON_ARG, ++ R_SCRATCH1, ++ R_SCRATCH2, ++ R_SCRATCH3, ++ R_SCRATCH4, ++ R_CAP, ++ R_GPIODIR0, ++ R_GPIODIR1, ++ R_GPIODIR2, ++ R_COUNT ++}; ++ ++#define BMC_ID1_VAL 0x49 ++#define BMC_ID2_VAL 0x54 ++#define BMC_ID3_VAL 0x58 ++#define BMC_ID4_VAL0 0x32 ++#define BMC_ID4_VAL1 0x2 ++ ++#define BMC_VERSION1 0 ++#define BMC_VERSION2 2 ++#define BMC_VERSION2_3 3 ++ ++#define BMC_CAP_PWRBTN 0x1 ++#define BMC_CAP_TOUCHPAD 0x2 ++#define BMC_CAP_RTC 0x4 ++#define BMC_CAP_FRU 0x8 ++#define BMC_CAP_GPIODIR 0x10 ++ ++#define BMC_SERIO_BUFSIZE 7 ++ ++#define POLL_JIFFIES 100 ++ ++struct bmc_poll_data { ++ struct i2c_client *c; ++}; ++ ++static struct i2c_client *bmc_i2c; ++static struct i2c_client *rtc_i2c; ++static struct i2c_driver mitx2_bmc_i2c_driver; ++static struct input_dev *button_dev; ++static struct bmc_poll_data poll_data; ++static struct task_struct *polling_task; ++#ifdef CONFIG_SERIO ++static struct i2c_client *serio_i2c; ++static struct task_struct *touchpad_task; ++#endif ++static u8 bmc_proto_version[3]; ++static u8 bmc_bootreason[2]; ++static u8 bmc_scratch[4]; ++static int bmc_cap; ++static const char input_name[] = "BMC input dev"; ++static u8 prev_ret; ++ ++/* BMC RTC */ ++static int ++bmc_rtc_read_time(struct device *dev, struct rtc_time *tm) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ uint8_t rtc_buf[8]; ++ struct i2c_msg msg; ++ int t; ++ int rc; ++ ++ msg.addr = client->addr; ++ msg.flags = I2C_M_RD; ++ msg.len = 8; ++ msg.buf = rtc_buf; ++ rc = i2c_transfer(client->adapter, &msg, 1); ++ if (rc != 1) { ++ dev_err(dev, "rtc_read_time: i2c_transfer error %d\n", rc); ++ return rc; ++ } ++ ++ tm->tm_sec = bcd2bin(rtc_buf[0] & 0x7f); ++ tm->tm_min = bcd2bin(rtc_buf[1] & 0x7f); ++ tm->tm_hour = bcd2bin(rtc_buf[2] & 0x3f); ++ if (rtc_buf[3] & (1 << 6)) /* PM */ ++ tm->tm_hour += 12; ++ tm->tm_mday = bcd2bin(rtc_buf[4] & 0x3f); ++ tm->tm_mon = bcd2bin(rtc_buf[5] & 0x1f); ++ t = rtc_buf[5] >> 5; ++ tm->tm_wday = (t == 7) ? 0 : t; ++ tm->tm_year = bcd2bin(rtc_buf[6]) + 100; /* year since 1900 */ ++ tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); ++ tm->tm_isdst = 0; ++ ++ return rtc_valid_tm(tm); ++} ++ ++static int ++bmc_rtc_set_time(struct device *dev, struct rtc_time *tm) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ uint8_t rtc_buf[8]; ++ struct i2c_msg msg; ++ int rc; ++ uint8_t seconds, minutes, hours, wday, mday, month, years; ++ ++ seconds = bin2bcd(tm->tm_sec); ++ minutes = bin2bcd(tm->tm_min); ++ hours = bin2bcd(tm->tm_hour); ++ wday = tm->tm_wday ? tm->tm_wday : 0x7; ++ mday = bin2bcd(tm->tm_mday); ++ month = bin2bcd(tm->tm_mon); ++ years = bin2bcd(tm->tm_year % 100); ++ ++ /* Need sanity check??? */ ++ rtc_buf[0] = seconds; ++ rtc_buf[1] = minutes; ++ rtc_buf[2] = hours; ++ rtc_buf[3] = 0; ++ rtc_buf[4] = mday; ++ rtc_buf[5] = month | (wday << 5); ++ rtc_buf[6] = years; ++ rtc_buf[7] = 0; ++ ++ msg.addr = client->addr; ++ msg.flags = 0; ++ msg.len = 8; ++ msg.buf = rtc_buf; ++ dev_dbg(dev, "rtc_set_time: %08x-%08x\n", *(uint32_t *)&rtc_buf[0], ++ *(uint32_t *)&rtc_buf[4]); ++ rc = i2c_transfer(client->adapter, &msg, 1); ++ if (rc != 1) ++ dev_err(dev, "i2c write: %d\n", rc); ++ ++ return (rc == 1) ? 0 : -EIO; ++} ++ ++static const struct rtc_class_ops ++bmc_rtc_ops = { ++ .read_time = bmc_rtc_read_time, ++ .set_time = bmc_rtc_set_time, ++}; ++ ++#ifdef CONFIG_SERIO ++/* BMC serio (PS/2 touchpad) interface */ ++ ++static int bmc_serio_write(struct serio *id, unsigned char val) ++{ ++ struct i2c_client *client = id->port_data; ++ uint8_t buf[4]; ++ struct i2c_msg msg; ++ int rc; ++ ++ buf[0] = val; ++ msg.addr = client->addr; ++ msg.flags = 0; ++ msg.len = 1; ++ msg.buf = buf; ++ dev_dbg(&client->dev, "bmc_serio_write: %02x\n", val); ++ rc = i2c_transfer(client->adapter, &msg, 1); ++ if (rc != 1) ++ dev_err(&client->dev, "i2c write: %d\n", rc); ++ ++ return (rc == 1) ? 0 : -EIO; ++} ++ ++/* returns: -1 on error, +1 if more data available, 0 otherwise */ ++static int bmc_serio_read(struct i2c_client *client) ++{ ++ struct serio *serio = dev_get_drvdata(&client->dev); ++ int i, rc, cnt; ++ uint8_t buf[BMC_SERIO_BUFSIZE]; ++ struct i2c_msg msg; ++ ++ msg.addr = client->addr; ++ msg.flags = I2C_M_RD; ++ msg.len = BMC_SERIO_BUFSIZE; ++ msg.buf = buf; ++ rc = i2c_transfer(client->adapter, &msg, 1); ++ if (rc != 1) { ++ dev_err(&client->dev, "bmc_serio_read: i2c_transfer error %d\n", rc); ++ return -1; ++ } ++ ++ cnt = buf[0]; ++ rc = 0; ++ if (cnt > BMC_SERIO_BUFSIZE - 1) { ++ cnt = BMC_SERIO_BUFSIZE - 1; ++ rc = 1; ++ } ++ ++ for (i = 0; i < cnt; i++) { ++ serio_interrupt(serio, buf[i + 1], 0); ++ } ++ ++ return 0; ++} ++ ++int ++touchpad_poll_fn(void *data) { ++ int ret; ++ ++ while (1) { ++ if (kthread_should_stop()) ++ break; ++ while ((ret = bmc_serio_read(serio_i2c)) > 0) ++ ; ++ if (ret < 0) { ++ msleep_interruptible(10000); ++ } ++ msleep_interruptible(10); ++ } ++ return 0; ++} ++#endif /* CONFIG_SERIO */ ++ ++#ifdef CONFIG_PINCTRL ++static uint8_t bmc_pincf_state [3]; ++#define BMC_NPINS (sizeof(bmc_pincf_state) * 8) ++ ++static struct pinctrl_pin_desc bmc_pin_desc[BMC_NPINS] = { ++ PINCTRL_PIN(0, "P0"), ++ PINCTRL_PIN(1, "P1"), ++ PINCTRL_PIN(2, "P2"), ++ PINCTRL_PIN(3, "P3"), ++ PINCTRL_PIN(4, "P4"), ++ PINCTRL_PIN(5, "P5"), ++ PINCTRL_PIN(6, "P6"), ++ PINCTRL_PIN(7, "P7"), ++ PINCTRL_PIN(8, "P8"), ++ PINCTRL_PIN(9, "P9"), ++ PINCTRL_PIN(10, "P10"), ++ PINCTRL_PIN(11, "P11"), ++ PINCTRL_PIN(12, "P12"), ++ PINCTRL_PIN(13, "P13"), ++ PINCTRL_PIN(14, "P14"), ++ PINCTRL_PIN(15, "P15"), ++ PINCTRL_PIN(16, "P16"), ++ PINCTRL_PIN(17, "P17"), ++ PINCTRL_PIN(18, "P18"), ++ PINCTRL_PIN(19, "P19"), ++ PINCTRL_PIN(20, "P20"), ++ PINCTRL_PIN(21, "P21"), ++ PINCTRL_PIN(22, "P22"), ++ PINCTRL_PIN(23, "P23"), ++}; ++ ++#define PCTRL_DEV "bmc_pinctrl" ++ ++static int bmc_pin_config_get(struct pinctrl_dev *pctldev, ++ unsigned pin, ++ unsigned long *config) ++{ ++ int idx, bit; ++ ++ if (pin > BMC_NPINS) ++ return -EINVAL; ++ ++ idx = pin >> 3; ++ bit = pin & 7; ++ ++ *config = !!(bmc_pincf_state[idx] & (1 << bit)); ++ return 0; ++} ++ ++static int bmc_pin_config_set(struct pinctrl_dev *pctldev, ++ unsigned pin, ++ unsigned long *config, ++ unsigned nc) ++{ ++ int idx, bit; ++ enum pin_config_param param; ++ int arg; ++ ++ if (pin > BMC_NPINS) ++ return -EINVAL; ++ ++ idx = pin >> 3; ++ bit = pin & 7; ++ ++ param = pinconf_to_config_param (*config); ++ arg = pinconf_to_config_argument (*config); ++ if (param != PIN_CONFIG_OUTPUT) ++ return -EINVAL; ++ ++ if (arg) ++ bmc_pincf_state[idx] |= (1 << bit); ++ else ++ bmc_pincf_state[idx] &= ~(1 << bit); ++dev_dbg(&bmc_i2c->dev, "bmc_pin_config_set: pin %u, dir %lu\n", pin, *config); ++ ++ return i2c_smbus_write_byte_data(bmc_i2c, R_GPIODIR0 + idx, bmc_pincf_state[idx]); ++} ++ ++void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, ++ struct seq_file *s, unsigned long config); ++ ++void pinctrl_utils_free_map(struct pinctrl_dev *pctldev, ++ struct pinctrl_map *map, unsigned num_maps); ++ ++static const struct pinconf_ops bmc_confops = { ++ .pin_config_get = bmc_pin_config_get, ++ .pin_config_set = bmc_pin_config_set, ++ .pin_config_config_dbg_show = pinconf_generic_dump_config, ++}; ++ ++static int bmc_groups_count(struct pinctrl_dev *pctldev) ++{ ++ return 0; ++} ++ ++static const char *bmc_group_name(struct pinctrl_dev *pctldev, ++ unsigned selector) ++{ ++ return NULL; ++} ++ ++static const struct pinctrl_ops bmc_ctrl_ops = { ++ .get_groups_count = bmc_groups_count, ++ .get_group_name = bmc_group_name, ++ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, ++ .dt_free_map = pinctrl_utils_free_map, ++}; ++ ++static struct pinctrl_desc bmc_pincrtl_desc = { ++ .name = PCTRL_DEV, ++ .pins = bmc_pin_desc, ++ .pctlops = &bmc_ctrl_ops, ++ .npins = BMC_NPINS, ++ .confops = &bmc_confops, ++}; ++ ++static struct pinctrl_dev *bmc_pinctrl_dev; ++ ++static int bmc_pinctrl_register(struct device *dev) ++{ ++ struct pinctrl_dev *pctrl_dev; ++ struct platform_device *pbdev; ++ ++ pbdev = platform_device_alloc(PCTRL_DEV, -1); ++ pbdev->dev.parent = dev; ++ pbdev->dev.of_node = of_find_node_by_name(dev->of_node, "bmc_pinctrl"); ++ platform_device_add(pbdev); ++ pctrl_dev = devm_pinctrl_register(&pbdev->dev, &bmc_pincrtl_desc, NULL); ++ if (IS_ERR(pctrl_dev)) { ++ dev_err(&pbdev->dev, "Can't register pinctrl (%ld)\n", PTR_ERR(pctrl_dev)); ++ return PTR_ERR(pctrl_dev); ++ } else { ++ dev_info(&pbdev->dev, "BMC pinctrl registered\n"); ++ bmc_pinctrl_dev = pctrl_dev; ++ } ++ /* reset all pins to default state */ ++ i2c_smbus_write_byte_data(to_i2c_client(dev), R_GPIODIR0, 0); ++ i2c_smbus_write_byte_data(to_i2c_client(dev), R_GPIODIR1, 0); ++ i2c_smbus_write_byte_data(to_i2c_client(dev), R_GPIODIR2, 0); ++ return 0; ++} ++ ++static void bmc_pinctrl_unregister(void) ++{ ++ if (bmc_pinctrl_dev) ++ devm_pinctrl_unregister(&bmc_i2c->dev, bmc_pinctrl_dev); ++} ++ ++#endif ++ ++void ++bmc_pwroff_rq(void) { ++ int ret = 0; ++ ++ dev_info(&bmc_i2c->dev, "Write reg R_PWROFF_RQ\n"); ++ ret = i2c_smbus_write_byte_data(bmc_i2c, R_PWROFF_RQ, 0x01); ++ dev_info(&bmc_i2c->dev, "ret: %i\n", ret); ++} ++ ++int ++pwroff_rq_poll_fn(void *data) { ++ int ret; ++ ++ while (1) { ++ if (kthread_should_stop()) ++ break; ++ dev_dbg(&poll_data.c->dev, "Polling\n"); ++ ret = i2c_smbus_read_byte_data(poll_data.c, R_SOFTOFF_RQ); ++ dev_dbg(&poll_data.c->dev, "Polling returned: %i\n", ret); ++ if (prev_ret != ret) { ++ dev_info(&poll_data.c->dev, "key change [%i]\n", ret); ++ if (ret < 0) { ++ dev_err(&poll_data.c->dev, ++ "Could not read register %x\n", ++ R_SOFTOFF_RQ); ++ return -EIO; ++ } else if (ret != 0) { ++ dev_info(&poll_data.c->dev, ++ "PWROFF \"irq\" detected [%i]\n", ret); ++ input_event(button_dev, EV_KEY, KEY_POWER, 1); ++ } else { ++ input_event(button_dev, EV_KEY, KEY_POWER, 0); ++ } ++ input_sync(button_dev); ++ } ++ prev_ret = ret; ++ ++ msleep_interruptible(100); ++ } ++ do_exit(1); ++ return 0; ++} ++ ++static int ++mitx2_bmc_validate(struct i2c_client *client) { ++ int ret = 0; ++ int i = 0; ++ static const u8 regs[] = {R_ID1, R_ID2, R_ID3}; ++ static const u8 vals[] = {BMC_ID1_VAL, BMC_ID2_VAL, BMC_ID3_VAL}; ++ ++ bmc_proto_version[0] = 0; ++ bmc_proto_version[1] = 0; ++ bmc_proto_version[2] = 0; ++ ++ for (i = 0; i < ARRAY_SIZE(regs); i++) { ++ ret = i2c_smbus_read_byte_data(client, regs[i]); ++ if (ret < 0) { ++ dev_err(&client->dev, "Could not read register %x\n", ++ regs[i]); ++ return -EIO; ++ } ++ if (ret != vals[i]) { ++ dev_err(&client->dev, ++ "Bad value [0x%02x] in register 0x%02x, should be [0x%02x]\n", ++ ret, regs[i], vals[i]); ++ ++ return -ENODEV; ++ } ++ } ++ ret = i2c_smbus_read_byte_data(client, R_ID4); ++ if (ret < 0) { ++ dev_err(&client->dev, "Could not read register %x\n", R_ID4); ++ return -EIO; ++ } ++ if (ret == BMC_ID4_VAL0) { ++ bmc_proto_version[0] = 0; ++ } else if (ret == BMC_ID4_VAL1) { ++ bmc_proto_version[0] = 2; ++ ret = i2c_smbus_read_byte_data(client, R_VERSION1); ++ if (ret < 0) { ++ dev_err(&client->dev, "Could not read register %x\n", ++ R_VERSION1); ++ return -EIO; ++ } ++ bmc_proto_version[1] = ret; ++ ret = i2c_smbus_read_byte_data(client, R_VERSION2); ++ if (ret < 0) { ++ dev_err(&client->dev, "Could not read register %x\n", ++ R_VERSION2); ++ return -EIO; ++ } ++ bmc_proto_version[2] = ret; ++ ret = i2c_smbus_read_byte_data(client, R_BOOTREASON); ++ if (ret < 0) { ++ dev_err(&client->dev, "Could not read register %x\n", ++ R_BOOTREASON); ++ return -EIO; ++ } ++ bmc_bootreason[0] = ret; ++ dev_info(&client->dev, "BMC bootreason[0]->%i\n", ret); ++ ret = i2c_smbus_read_byte_data(client, R_BOOTREASON_ARG); ++ if (ret < 0) { ++ dev_err(&client->dev, "Could not read register %x\n", ++ R_BOOTREASON_ARG); ++ return -EIO; ++ } ++ bmc_bootreason[1] = ret; ++ dev_info(&client->dev, "BMC bootreason[1]->%i\n", ret); ++ for (i = R_SCRATCH1; i <= R_SCRATCH4; i++) { ++ ret = i2c_smbus_read_byte_data(client, i); ++ if (ret < 0) { ++ dev_err(&client->dev, ++ "Could not read register %x\n", i); ++ return -EIO; ++ } ++ bmc_scratch[i - R_SCRATCH1] = ret; ++ } ++ if (bmc_proto_version[2] >= BMC_VERSION2_3) { ++ ret = i2c_smbus_read_byte_data(client, R_CAP); ++ if (ret >= 0) ++ bmc_cap = ret; ++ dev_info(&client->dev, ++ "BMC extended capabilities %x\n", bmc_cap); ++ } else { ++ bmc_cap = BMC_CAP_PWRBTN; ++ } ++ } else { ++ dev_err(&client->dev, "Bad value [0x%02x] in register 0x%02x\n", ++ ret, R_ID4); ++ return -ENODEV; ++ } ++ dev_info(&client->dev, "BMC seems to be valid\n"); ++ return 0; ++} ++ ++static int ++bmc_create_client_devices(struct device *bmc_dev) ++{ ++ int ret = 0; ++ struct rtc_device *rtc_dev; ++ struct i2c_client *client = to_i2c_client(bmc_dev); ++ int client_addr = client->addr + 1; ++ ++ if (bmc_cap & BMC_CAP_TOUCHPAD) { ++#ifdef CONFIG_SERIO ++ struct serio *serio; ++ serio_i2c = i2c_new_ancillary_device(client, ++ "bmc_serio", client_addr); ++ if (IS_ERR(serio_i2c)) { ++ dev_err(&client->dev, "Can't get serio secondary\n"); ++ serio_i2c = NULL; ++ ret = -ENOMEM; ++ goto fail; ++ } ++ serio = devm_kzalloc(&serio_i2c->dev, sizeof(struct serio), GFP_KERNEL); ++ if (!serio) { ++ dev_err(&serio_i2c->dev, "Can't allocate serio\n"); ++ ret = -ENOMEM; ++ i2c_unregister_device(serio_i2c); ++ serio_i2c = NULL; ++ goto skip_tp; ++ } ++ serio->write = bmc_serio_write; ++ serio->port_data = serio_i2c; ++ serio->id.type = SERIO_PS_PSTHRU; ++ serio_register_port(serio); ++ dev_set_drvdata(&serio_i2c->dev, serio); ++ touchpad_task = kthread_run(touchpad_poll_fn, NULL, "BMC serio poll task"); ++ ++skip_tp: ++#endif ++ client_addr++; ++ } ++ ++ if (bmc_cap & BMC_CAP_RTC) { ++ rtc_i2c = i2c_new_ancillary_device(client, ++ "bmc_rtc", client_addr); ++ if (IS_ERR(rtc_i2c)) { ++ dev_err(&client->dev, "Can't get RTC secondary\n"); ++ rtc_i2c = NULL; ++ ret = -ENOMEM; ++ goto fail; ++ } ++ ++ rtc_dev = devm_rtc_device_register(&rtc_i2c->dev, "bmc_rtc", ++ &bmc_rtc_ops, THIS_MODULE); ++ if (IS_ERR(rtc_dev)) { ++ ret = PTR_ERR(rtc_dev); ++ dev_err(&client->dev, "Failed to register RTC device: %d\n", ++ ret); ++ i2c_unregister_device(rtc_i2c); ++ rtc_i2c = NULL; ++ } ++fail: ++ client_addr++; ++ } ++ ++#ifdef CONFIG_PINCTRL ++ if (bmc_cap & BMC_CAP_GPIODIR || 1 /*vvv*/) ++ bmc_pinctrl_register(bmc_dev); ++#endif ++ ++ return ret; ++} ++ ++static int ++mitx2_bmc_i2c_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ int err = 0; ++ int i = 0; ++ ++ dev_info(&client->dev, "mitx2 bmc probe\n"); ++ ++ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) ++ return -ENODEV; ++ ++ for (i = 0; i < 10; i++) { ++ err = mitx2_bmc_validate(client); ++ if (!err) ++ break; ++ msleep_interruptible(20); ++ } ++ if (err) ++ return err; ++ ++ if (bmc_cap & BMC_CAP_PWRBTN) { ++ button_dev = input_allocate_device(); ++ if (!button_dev) { ++ dev_err(&client->dev, "Not enough memory\n"); ++ return -ENOMEM; ++ } ++ ++ button_dev->id.bustype = BUS_I2C; ++ button_dev->dev.parent = &client->dev; ++ button_dev->name = input_name; ++ button_dev->phys = "bmc-input0"; ++ button_dev->evbit[0] = BIT_MASK(EV_KEY); ++ button_dev->keybit[BIT_WORD(KEY_POWER)] = BIT_MASK(KEY_POWER); ++ ++ err = input_register_device(button_dev); ++ if (err) { ++ dev_err(&client->dev, "Failed to register device\n"); ++ input_free_device(button_dev); ++ return err; ++ } ++ ++ dev_info(&client->dev, "Starting polling thread\n"); ++ poll_data.c = client; ++ polling_task = kthread_run(pwroff_rq_poll_fn, NULL, "BMC poll task"); ++ } ++ ++ if (bmc_cap || 1 /*vvv*/) ++ err = bmc_create_client_devices(&client->dev); ++ ++ bmc_i2c = client; ++ /* register as poweroff handler */ ++ pm_power_off = bmc_pwroff_rq; ++ ++ return 0; ++} ++ ++static int ++mitx2_bmc_i2c_remove(struct i2c_client *client) ++{ ++#ifdef CONFIG_SERIO ++ struct serio *serio; ++#endif ++ ++ if (button_dev) { ++ kthread_stop(polling_task); ++ input_unregister_device(button_dev); ++ } ++#ifdef CONFIG_SERIO ++ if (serio_i2c) { ++ kthread_stop(touchpad_task); ++ serio = dev_get_drvdata(&serio_i2c->dev); ++ serio_unregister_port(serio); ++ i2c_unregister_device(serio_i2c); ++ } ++#endif ++ if (rtc_i2c) ++ i2c_unregister_device(rtc_i2c); ++#ifdef CONFIG_PINCTRL ++ bmc_pinctrl_unregister(); ++#endif ++ ++ return 0; ++} ++ ++#ifdef CONFIG_OF ++static const struct of_device_id mitx2_bmc_of_match[] = { ++ { .compatible = "tp,mitx2-bmc" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, mitx2_bmc_of_match); ++#endif ++ ++static const struct i2c_device_id mitx2_bmc_i2c_id[] = { ++ { "mitx2_bmc", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, mitx2_bmc_i2c_id); ++ ++static ssize_t ++version_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%i.%i.%i\n", bmc_proto_version[0], ++ bmc_proto_version[1], bmc_proto_version[2]); ++} ++ ++static struct kobj_attribute version_attribute = ++ __ATTR(version, 0664, version_show, NULL); ++ ++static ssize_t ++bootreason_show(struct kobject *kobj, ++ struct kobj_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%i\n", (bmc_bootreason[0] | ++ (bmc_bootreason[1] << 8))); ++} ++ ++static struct kobj_attribute bootreason_attribute = ++ __ATTR(bootreason, 0664, bootreason_show, NULL); ++ ++static ssize_t ++scratch_show(struct kobject *kobj, ++ struct kobj_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%i\n", (bmc_scratch[0] | (bmc_scratch[1] << 8) | ++ (bmc_scratch[2] << 16) | (bmc_scratch[3] << 24))); ++} ++ ++static struct kobj_attribute scratch_attribute = ++ __ATTR(scratch, 0664, scratch_show, NULL); ++ ++static struct attribute *bmc_attrs[] = { ++ &version_attribute.attr, ++ &bootreason_attribute.attr, ++ &scratch_attribute.attr, ++ NULL, ++}; ++ ++ATTRIBUTE_GROUPS(bmc); ++ ++static struct i2c_driver mitx2_bmc_i2c_driver = { ++ .driver = { ++ .name = "mitx2-bmc", ++ .of_match_table = of_match_ptr(mitx2_bmc_of_match), ++ .groups = bmc_groups, ++ }, ++ .probe = mitx2_bmc_i2c_probe, ++ .remove = mitx2_bmc_i2c_remove, ++ .id_table = mitx2_bmc_i2c_id, ++}; ++module_i2c_driver(mitx2_bmc_i2c_driver); ++ ++MODULE_AUTHOR("Konstantin Kirik"); ++MODULE_DESCRIPTION("mITX2 BMC driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("serial:bmc"); +-- +2.31.1 + diff --git a/0611-dw-hdmi-ahb-audio-support-BE-M1000-SoC.patch b/0611-dw-hdmi-ahb-audio-support-BE-M1000-SoC.patch new file mode 100644 index 0000000..04fa112 --- /dev/null +++ b/0611-dw-hdmi-ahb-audio-support-BE-M1000-SoC.patch @@ -0,0 +1,251 @@ +From 750bd359f6fff79a3131f89c3bd9ad8a83a6356a Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Wed, 3 Feb 2021 16:58:16 +0400 +Subject: [PATCH 611/625] dw-hdmi-ahb-audio: support BE-M1000 SoC + +--- + .../drm/bridge/synopsys/dw-hdmi-ahb-audio.c | 106 ++++++++++++------ + .../gpu/drm/bridge/synopsys/dw-hdmi-audio.h | 1 + + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 + + 3 files changed, 78 insertions(+), 35 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c +index d0db1acf11d7..3bb652e42718 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c +@@ -132,12 +132,45 @@ struct snd_dw_hdmi { + u8 cs[192][8]; + }; + +-static void dw_hdmi_writel(u32 val, void __iomem *ptr) ++static inline void dw_hdmi_writeb_relaxed(u8 value, const struct dw_hdmi_audio_data *data, int offset) + { +- writeb_relaxed(val, ptr); +- writeb_relaxed(val >> 8, ptr + 1); +- writeb_relaxed(val >> 16, ptr + 2); +- writeb_relaxed(val >> 24, ptr + 3); ++ void __iomem *base = data->base; ++ if (data->reg_offset != 0) ++ offset <<= data->reg_offset; ++ writeb_relaxed(value, base + offset); ++} ++ ++static inline void dw_hdmi_writeb(u8 value, const struct dw_hdmi_audio_data *data, int offset) ++{ ++ void __iomem *base = data->base; ++ if (data->reg_offset != 0) ++ offset <<= data->reg_offset; ++ writeb(value, base + offset); ++} ++ ++static inline u8 dw_hdmi_readb(const struct dw_hdmi_audio_data *data, int offset) ++{ ++ void __iomem *base = data->base; ++ if (data->reg_offset != 0) ++ offset <<= data->reg_offset; ++ return readb(base + offset); ++ ++} ++ ++static inline u8 dw_hdmi_readb_relaxed(const struct dw_hdmi_audio_data *data, int offset) ++{ ++ void __iomem *base = data->base; ++ if (data->reg_offset != 0) ++ offset <<= data->reg_offset; ++ return readb_relaxed(base + offset); ++} ++ ++static void dw_hdmi_writel(u32 val, const struct dw_hdmi_audio_data *data, int offset) ++{ ++ dw_hdmi_writeb_relaxed(val, data, offset); ++ dw_hdmi_writeb_relaxed(val >> 8, data, offset + 1); ++ dw_hdmi_writeb_relaxed(val >> 16, data, offset + 2); ++ dw_hdmi_writeb_relaxed(val >> 24, data, offset + 3); + } + + /* +@@ -232,7 +265,6 @@ static void dw_hdmi_create_cs(struct snd_dw_hdmi *dw, + + static void dw_hdmi_start_dma(struct snd_dw_hdmi *dw) + { +- void __iomem *base = dw->data.base; + unsigned offset = dw->buf_offset; + unsigned period = dw->buf_period; + u32 start, stop; +@@ -240,18 +272,18 @@ static void dw_hdmi_start_dma(struct snd_dw_hdmi *dw) + dw->reformat(dw, offset, period); + + /* Clear all irqs before enabling irqs and starting DMA */ +- writeb_relaxed(HDMI_IH_AHBDMAAUD_STAT0_ALL, +- base + HDMI_IH_AHBDMAAUD_STAT0); ++ dw_hdmi_writeb_relaxed(HDMI_IH_AHBDMAAUD_STAT0_ALL, ++ &dw->data, HDMI_IH_AHBDMAAUD_STAT0); + + start = dw->buf_addr + offset; + stop = start + period - 1; + + /* Setup the hardware start/stop addresses */ +- dw_hdmi_writel(start, base + HDMI_AHB_DMA_STRADDR0); +- dw_hdmi_writel(stop, base + HDMI_AHB_DMA_STPADDR0); ++ dw_hdmi_writel(start, &dw->data, HDMI_AHB_DMA_STRADDR0); ++ dw_hdmi_writel(stop, &dw->data, HDMI_AHB_DMA_STPADDR0); + +- writeb_relaxed((u8)~HDMI_AHB_DMA_MASK_DONE, base + HDMI_AHB_DMA_MASK); +- writeb(HDMI_AHB_DMA_START_START, base + HDMI_AHB_DMA_START); ++ dw_hdmi_writeb_relaxed((u8)~HDMI_AHB_DMA_MASK_DONE, &dw->data, HDMI_AHB_DMA_MASK); ++ dw_hdmi_writeb(HDMI_AHB_DMA_START_START, &dw->data, HDMI_AHB_DMA_START); + + offset += period; + if (offset >= dw->buf_size) +@@ -262,8 +294,8 @@ static void dw_hdmi_start_dma(struct snd_dw_hdmi *dw) + static void dw_hdmi_stop_dma(struct snd_dw_hdmi *dw) + { + /* Disable interrupts before disabling DMA */ +- writeb_relaxed(~0, dw->data.base + HDMI_AHB_DMA_MASK); +- writeb_relaxed(HDMI_AHB_DMA_STOP_STOP, dw->data.base + HDMI_AHB_DMA_STOP); ++ dw_hdmi_writeb_relaxed(~0, &dw->data, HDMI_AHB_DMA_MASK); ++ dw_hdmi_writeb_relaxed(HDMI_AHB_DMA_STOP_STOP, &dw->data, HDMI_AHB_DMA_STOP); + } + + static irqreturn_t snd_dw_hdmi_irq(int irq, void *data) +@@ -272,11 +304,11 @@ static irqreturn_t snd_dw_hdmi_irq(int irq, void *data) + struct snd_pcm_substream *substream; + unsigned stat; + +- stat = readb_relaxed(dw->data.base + HDMI_IH_AHBDMAAUD_STAT0); ++ stat = dw_hdmi_readb_relaxed(&dw->data, HDMI_IH_AHBDMAAUD_STAT0); + if (!stat) + return IRQ_NONE; + +- writeb_relaxed(stat, dw->data.base + HDMI_IH_AHBDMAAUD_STAT0); ++ dw_hdmi_writeb_relaxed(stat, &dw->data, HDMI_IH_AHBDMAAUD_STAT0); + + substream = dw->substream; + if (stat & HDMI_IH_AHBDMAAUD_STAT0_DONE && substream) { +@@ -319,7 +351,6 @@ static int dw_hdmi_open(struct snd_pcm_substream *substream) + { + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_dw_hdmi *dw = substream->private_data; +- void __iomem *base = dw->data.base; + int ret; + + runtime->hw = dw_hdmi_hw; +@@ -345,16 +376,16 @@ static int dw_hdmi_open(struct snd_pcm_substream *substream) + return ret; + + /* Clear FIFO */ +- writeb_relaxed(HDMI_AHB_DMA_CONF0_SW_FIFO_RST, +- base + HDMI_AHB_DMA_CONF0); ++ dw_hdmi_writeb_relaxed(HDMI_AHB_DMA_CONF0_SW_FIFO_RST, ++ &dw->data, HDMI_AHB_DMA_CONF0); + + /* Configure interrupt polarities */ +- writeb_relaxed(~0, base + HDMI_AHB_DMA_POL); +- writeb_relaxed(~0, base + HDMI_AHB_DMA_BUFFPOL); ++ dw_hdmi_writeb_relaxed(~0, &dw->data, HDMI_AHB_DMA_POL); ++ dw_hdmi_writeb_relaxed(~0, &dw->data, HDMI_AHB_DMA_BUFFPOL); + + /* Keep interrupts masked, and clear any pending */ +- writeb_relaxed(~0, base + HDMI_AHB_DMA_MASK); +- writeb_relaxed(~0, base + HDMI_IH_AHBDMAAUD_STAT0); ++ dw_hdmi_writeb_relaxed(~0, &dw->data, HDMI_AHB_DMA_MASK); ++ dw_hdmi_writeb_relaxed(~0, &dw->data, HDMI_IH_AHBDMAAUD_STAT0); + + ret = request_irq(dw->data.irq, snd_dw_hdmi_irq, IRQF_SHARED, + "dw-hdmi-audio", dw); +@@ -362,9 +393,9 @@ static int dw_hdmi_open(struct snd_pcm_substream *substream) + return ret; + + /* Un-mute done interrupt */ +- writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL & +- ~HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE, +- base + HDMI_IH_MUTE_AHBDMAAUD_STAT0); ++ dw_hdmi_writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL & ++ ~HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE, ++ &dw->data, HDMI_IH_MUTE_AHBDMAAUD_STAT0); + + return 0; + } +@@ -374,8 +405,8 @@ static int dw_hdmi_close(struct snd_pcm_substream *substream) + struct snd_dw_hdmi *dw = substream->private_data; + + /* Mute all interrupts */ +- writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL, +- dw->data.base + HDMI_IH_MUTE_AHBDMAAUD_STAT0); ++ dw_hdmi_writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL, ++ &dw->data, HDMI_IH_MUTE_AHBDMAAUD_STAT0); + + free_irq(dw->data.irq, dw); + +@@ -416,6 +447,11 @@ static int dw_hdmi_prepare(struct snd_pcm_substream *substream) + HDMI_AHB_DMA_CONF0_INCR8; + threshold = 128; + break; ++ case 0x2a: /* this revision is used in Baikal-M SoC */ ++ conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE | ++ HDMI_AHB_DMA_CONF0_INCR16; ++ threshold = 128; ++ break; + default: + /* NOTREACHED */ + return -EINVAL; +@@ -430,9 +466,9 @@ static int dw_hdmi_prepare(struct snd_pcm_substream *substream) + conf1 = default_hdmi_channel_config[runtime->channels - 2].conf1; + ca = default_hdmi_channel_config[runtime->channels - 2].ca; + +- writeb_relaxed(threshold, dw->data.base + HDMI_AHB_DMA_THRSLD); +- writeb_relaxed(conf0, dw->data.base + HDMI_AHB_DMA_CONF0); +- writeb_relaxed(conf1, dw->data.base + HDMI_AHB_DMA_CONF1); ++ dw_hdmi_writeb_relaxed(threshold, &dw->data, HDMI_AHB_DMA_THRSLD); ++ dw_hdmi_writeb_relaxed(conf0, &dw->data, HDMI_AHB_DMA_CONF0); ++ dw_hdmi_writeb_relaxed(conf1, &dw->data, HDMI_AHB_DMA_CONF1); + + dw_hdmi_set_channel_count(dw->data.hdmi, runtime->channels); + dw_hdmi_set_channel_allocation(dw->data.hdmi, ca); +@@ -524,10 +560,10 @@ static int snd_dw_hdmi_probe(struct platform_device *pdev) + unsigned revision; + int ret; + +- writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL, +- data->base + HDMI_IH_MUTE_AHBDMAAUD_STAT0); +- revision = readb_relaxed(data->base + HDMI_REVISION_ID); +- if (revision != 0x0a && revision != 0x1a) { ++ dw_hdmi_writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL, ++ data, HDMI_IH_MUTE_AHBDMAAUD_STAT0); ++ revision = dw_hdmi_readb_relaxed(data, HDMI_REVISION_ID); ++ if (revision != 0x0a && revision != 0x1a && revision != 0x2a) { + dev_err(dev, "dw-hdmi-audio: unknown revision 0x%02x\n", + revision); + return -ENXIO; +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h +index cb07dc0da5a7..8fb5ebd5a169 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h +@@ -10,6 +10,7 @@ struct dw_hdmi_audio_data { + int irq; + struct dw_hdmi *hdmi; + u8 *eld; ++ unsigned reg_offset; + }; + + struct dw_hdmi_i2s_audio_data { +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 0c79a9ba48bb..d0580b7d7430 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -3396,6 +3396,12 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, + audio.irq = irq; + audio.hdmi = hdmi; + audio.eld = hdmi->connector.eld; ++ audio.reg_offset = 0; ++ if (of_device_is_compatible(np, "baikal,hdmi")) { ++ audio.reg_offset = 2; ++ dev_info(dev, "setting audio.reg_offset=%d for BE-M1000 SoC\n", ++ audio.reg_offset); ++ } + hdmi->enable_audio = dw_hdmi_ahb_audio_enable; + hdmi->disable_audio = dw_hdmi_ahb_audio_disable; + +-- +2.31.1 + diff --git a/0612-bt1-pvt.c-access-registers-via-pvt_-readl-writel-hel.patch b/0612-bt1-pvt.c-access-registers-via-pvt_-readl-writel-hel.patch new file mode 100644 index 0000000..8c7195a --- /dev/null +++ b/0612-bt1-pvt.c-access-registers-via-pvt_-readl-writel-hel.patch @@ -0,0 +1,252 @@ +From 5b71a758ddc825759d287b5077c0f36a25c30da6 Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Thu, 3 Dec 2020 19:02:15 +0400 +Subject: [PATCH 612/625] bt1-pvt.c: access registers via pvt_{readl,writel} + helper functions + +BE-M1000 SoC is equipped with PVT sensors too. However PVT registers are +not directly accessible to kernel. Instead the registers (and clocks) +are managed by the "secure world", so Linux has to call into firmware. + +This patch replaces readl/writel with pvt_readl/pvt_writel functions. +No functional changes is intended. Subsequent patch will define pvt_readl +and pvt_writel functions for BE-M1000 SoC. +--- + drivers/hwmon/bt1-pvt.c | 85 +++++++++++++++++++++++------------------ + 1 file changed, 48 insertions(+), 37 deletions(-) + +diff --git a/drivers/hwmon/bt1-pvt.c b/drivers/hwmon/bt1-pvt.c +index 3e1d56585b91..c6749585d604 100644 +--- a/drivers/hwmon/bt1-pvt.c ++++ b/drivers/hwmon/bt1-pvt.c +@@ -138,12 +138,23 @@ static long pvt_calc_poly(const struct pvt_poly *poly, long data) + return ret / poly->total_divider; + } + +-static inline u32 pvt_update(void __iomem *reg, u32 mask, u32 data) ++static inline u32 pvt_readl(struct pvt_hwmon const *pvt, int reg) { ++ return readl(pvt->regs + reg); ++} ++ ++static inline u32 pvt_readl_relaxed(struct pvt_hwmon const *pvt, int reg) { ++ return readl_relaxed(pvt->regs + reg); ++} ++ ++static inline void pvt_writel(u32 data, struct pvt_hwmon const *pvt, int reg) { ++ writel(data, pvt->regs + reg); ++} ++static inline u32 pvt_update(struct pvt_hwmon *pvt, int reg, u32 mask, u32 data) + { + u32 old; + +- old = readl_relaxed(reg); +- writel((old & ~mask) | (data & mask), reg); ++ old = pvt_readl_relaxed(pvt, reg); ++ pvt_writel((old & ~mask) | (data & mask), pvt, reg); + + return old & mask; + } +@@ -161,8 +172,8 @@ static inline void pvt_set_mode(struct pvt_hwmon *pvt, u32 mode) + + mode = FIELD_PREP(PVT_CTRL_MODE_MASK, mode); + +- old = pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); +- pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_MODE_MASK | PVT_CTRL_EN, ++ old = pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, 0); ++ pvt_update(pvt, PVT_CTRL, PVT_CTRL_MODE_MASK | PVT_CTRL_EN, + mode | old); + } + +@@ -179,8 +190,8 @@ static inline void pvt_set_trim(struct pvt_hwmon *pvt, u32 trim) + + trim = FIELD_PREP(PVT_CTRL_TRIM_MASK, trim); + +- old = pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); +- pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_TRIM_MASK | PVT_CTRL_EN, ++ old = pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, 0); ++ pvt_update(pvt, PVT_CTRL, PVT_CTRL_TRIM_MASK | PVT_CTRL_EN, + trim | old); + } + +@@ -188,9 +199,9 @@ static inline void pvt_set_tout(struct pvt_hwmon *pvt, u32 tout) + { + u32 old; + +- old = pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); +- writel(tout, pvt->regs + PVT_TTIMEOUT); +- pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, old); ++ old = pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, 0); ++ pvt_writel(tout, pvt, PVT_TTIMEOUT); ++ pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, old); + } + + /* +@@ -237,7 +248,7 @@ static irqreturn_t pvt_soft_isr(int irq, void *data) + * status before the next conversion happens. Threshold events will be + * handled a bit later. + */ +- thres_sts = readl(pvt->regs + PVT_RAW_INTR_STAT); ++ thres_sts = pvt_readl(pvt, PVT_RAW_INTR_STAT); + + /* + * Then lets recharge the PVT interface with the next sampling mode. +@@ -260,14 +271,14 @@ static irqreturn_t pvt_soft_isr(int irq, void *data) + */ + mutex_lock(&pvt->iface_mtx); + +- old = pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_DVALID, ++ old = pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_DVALID, + PVT_INTR_DVALID); + +- val = readl(pvt->regs + PVT_DATA); ++ val = pvt_readl(pvt, PVT_DATA); + + pvt_set_mode(pvt, pvt_info[pvt->sensor].mode); + +- pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_DVALID, old); ++ pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_DVALID, old); + + mutex_unlock(&pvt->iface_mtx); + +@@ -337,7 +348,7 @@ static int pvt_read_limit(struct pvt_hwmon *pvt, enum pvt_sensor_type type, + u32 data; + + /* No need in serialization, since it is just read from MMIO. */ +- data = readl(pvt->regs + pvt_info[type].thres_base); ++ data = pvt_readl(pvt, pvt_info[type].thres_base); + + if (is_low) + data = FIELD_GET(PVT_THRES_LO_MASK, data); +@@ -372,7 +383,7 @@ static int pvt_write_limit(struct pvt_hwmon *pvt, enum pvt_sensor_type type, + return ret; + + /* Make sure the upper and lower ranges don't intersect. */ +- limit = readl(pvt->regs + pvt_info[type].thres_base); ++ limit = pvt_readl(pvt, pvt_info[type].thres_base); + if (is_low) { + limit = FIELD_GET(PVT_THRES_HI_MASK, limit); + data = clamp_val(data, PVT_DATA_MIN, limit); +@@ -385,7 +396,7 @@ static int pvt_write_limit(struct pvt_hwmon *pvt, enum pvt_sensor_type type, + mask = PVT_THRES_HI_MASK; + } + +- pvt_update(pvt->regs + pvt_info[type].thres_base, mask, data); ++ pvt_update(pvt, pvt_info[type].thres_base, mask, data); + + mutex_unlock(&pvt->iface_mtx); + +@@ -439,14 +450,14 @@ static irqreturn_t pvt_hard_isr(int irq, void *data) + * Mask the DVALID interrupt so after exiting from the handler a + * repeated conversion wouldn't happen. + */ +- pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_DVALID, ++ pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_DVALID, + PVT_INTR_DVALID); + + /* + * Nothing special for alarm-less driver. Just read the data, update + * the cache and notify a waiter of this event. + */ +- val = readl(pvt->regs + PVT_DATA); ++ val = pvt_readl(pvt, PVT_DATA); + if (!(val & PVT_DATA_VALID)) { + dev_err(pvt->dev, "Got IRQ when data isn't valid\n"); + return IRQ_HANDLED; +@@ -498,8 +509,8 @@ static int pvt_read_data(struct pvt_hwmon *pvt, enum pvt_sensor_type type, + * Unmask the DVALID interrupt and enable the sensors conversions. + * Do the reverse procedure when conversion is done. + */ +- pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_DVALID, 0); +- pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, PVT_CTRL_EN); ++ pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_DVALID, 0); ++ pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, PVT_CTRL_EN); + + /* + * Wait with timeout since in case if the sensor is suddenly powered +@@ -510,8 +521,8 @@ static int pvt_read_data(struct pvt_hwmon *pvt, enum pvt_sensor_type type, + timeout = 2 * usecs_to_jiffies(ktime_to_us(pvt->timeout)); + ret = wait_for_completion_timeout(&cache->conversion, timeout); + +- pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); +- pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_DVALID, ++ pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, 0); ++ pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_DVALID, + PVT_INTR_DVALID); + + data = READ_ONCE(cache->data); +@@ -637,7 +648,7 @@ static int pvt_read_trim(struct pvt_hwmon *pvt, long *val) + { + u32 data; + +- data = readl(pvt->regs + PVT_CTRL); ++ data = pvt_readl(pvt, PVT_CTRL); + *val = FIELD_GET(PVT_CTRL_TRIM_MASK, data) * PVT_TRIM_STEP; + + return 0; +@@ -983,21 +994,21 @@ static int pvt_check_pwr(struct pvt_hwmon *pvt) + * conversion. In the later case alas we won't be able to detect the + * problem. + */ +- pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_ALL, PVT_INTR_ALL); +- pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, PVT_CTRL_EN); ++ pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_ALL, PVT_INTR_ALL); ++ pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, PVT_CTRL_EN); + pvt_set_tout(pvt, 0); +- readl(pvt->regs + PVT_DATA); ++ pvt_readl(pvt, PVT_DATA); + + tout = PVT_TOUT_MIN / NSEC_PER_USEC; + usleep_range(tout, 2 * tout); + +- data = readl(pvt->regs + PVT_DATA); ++ data = pvt_readl(pvt, PVT_DATA); + if (!(data & PVT_DATA_VALID)) { + ret = -ENODEV; + dev_err(pvt->dev, "Sensor is powered down\n"); + } + +- pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); ++ pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, 0); + + return ret; + } +@@ -1018,10 +1029,10 @@ static int pvt_init_iface(struct pvt_hwmon *pvt) + * accidentally have ISR executed before the driver data is fully + * initialized. Clear the IRQ status as well. + */ +- pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_ALL, PVT_INTR_ALL); +- pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); +- readl(pvt->regs + PVT_CLR_INTR); +- readl(pvt->regs + PVT_DATA); ++ pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_ALL, PVT_INTR_ALL); ++ pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, 0); ++ pvt_readl(pvt, PVT_CLR_INTR); ++ pvt_readl(pvt, PVT_DATA); + + /* Setup default sensor mode, timeout and temperature trim. */ + pvt_set_mode(pvt, pvt_info[pvt->sensor].mode); +@@ -1105,8 +1116,8 @@ static void pvt_disable_iface(void *data) + struct pvt_hwmon *pvt = data; + + mutex_lock(&pvt->iface_mtx); +- pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, 0); +- pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_DVALID, ++ pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, 0); ++ pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_DVALID, + PVT_INTR_DVALID); + mutex_unlock(&pvt->iface_mtx); + } +@@ -1128,8 +1139,8 @@ static int pvt_enable_iface(struct pvt_hwmon *pvt) + * which theoretically may cause races. + */ + mutex_lock(&pvt->iface_mtx); +- pvt_update(pvt->regs + PVT_INTR_MASK, PVT_INTR_DVALID, 0); +- pvt_update(pvt->regs + PVT_CTRL, PVT_CTRL_EN, PVT_CTRL_EN); ++ pvt_update(pvt, PVT_INTR_MASK, PVT_INTR_DVALID, 0); ++ pvt_update(pvt, PVT_CTRL, PVT_CTRL_EN, PVT_CTRL_EN); + mutex_unlock(&pvt->iface_mtx); + + return 0; +-- +2.31.1 + diff --git a/0613-bt1-pvt-define-pvt_readl-pvt_writel-for-BE-M1000-SoC.patch b/0613-bt1-pvt-define-pvt_readl-pvt_writel-for-BE-M1000-SoC.patch new file mode 100644 index 0000000..76a39b0 --- /dev/null +++ b/0613-bt1-pvt-define-pvt_readl-pvt_writel-for-BE-M1000-SoC.patch @@ -0,0 +1,87 @@ +From bb4383c2491f602cb87e619418cbff9c32a0f0ac Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Thu, 3 Dec 2020 19:13:51 +0400 +Subject: [PATCH 613/625] bt1-pvt: define pvt_readl/pvt_writel for BE-M1000 SoC + +--- + drivers/hwmon/bt1-pvt.c | 23 +++++++++++++++++++++++ + drivers/hwmon/bt1-pvt.h | 8 ++++++++ + 2 files changed, 31 insertions(+) + +diff --git a/drivers/hwmon/bt1-pvt.c b/drivers/hwmon/bt1-pvt.c +index c6749585d604..d1f66de6a2cd 100644 +--- a/drivers/hwmon/bt1-pvt.c ++++ b/drivers/hwmon/bt1-pvt.c +@@ -29,6 +29,9 @@ + #include + #include + #include ++#ifdef CONFIG_ARM64 ++#include ++#endif + + #include "bt1-pvt.h" + +@@ -138,6 +141,7 @@ static long pvt_calc_poly(const struct pvt_poly *poly, long data) + return ret / poly->total_divider; + } + ++#ifdef BT1_PVT_DIRECT_REG_ACCESS + static inline u32 pvt_readl(struct pvt_hwmon const *pvt, int reg) { + return readl(pvt->regs + reg); + } +@@ -149,6 +153,25 @@ static inline u32 pvt_readl_relaxed(struct pvt_hwmon const *pvt, int reg) { + static inline void pvt_writel(u32 data, struct pvt_hwmon const *pvt, int reg) { + writel(data, pvt->regs + reg); + } ++#else ++static inline u32 pvt_readl(struct pvt_hwmon const *pvt, int reg) { ++ struct arm_smccc_res res; ++ arm_smccc_smc(BAIKAL_SMC_PVT_ID, PVT_READ, pvt->pvt_id, reg, ++ 0, 0, 0, 0, &res); ++ return res.a0; ++} ++ ++static inline u32 pvt_readl_relaxed(struct pvt_hwmon const *pvt, int reg) { ++ return pvt_readl(pvt, reg); ++} ++ ++static inline void pvt_writel(u32 data, struct pvt_hwmon const *pvt, int reg) { ++ struct arm_smccc_res res; ++ arm_smccc_smc(BAIKAL_SMC_PVT_ID, PVT_WRITE, pvt->pvt_id, reg, ++ data, 0, 0, 0, &res); ++} ++#endif ++ + static inline u32 pvt_update(struct pvt_hwmon *pvt, int reg, u32 mask, u32 data) + { + u32 old; +diff --git a/drivers/hwmon/bt1-pvt.h b/drivers/hwmon/bt1-pvt.h +index 93b8dd5e7c94..0cea95b01c13 100644 +--- a/drivers/hwmon/bt1-pvt.h ++++ b/drivers/hwmon/bt1-pvt.h +@@ -101,6 +101,13 @@ + # define PVT_TOUT_DEF 0 + #endif + ++#define BAIKAL_SMC_PVT_ID 0x82000001 ++#define PVT_READ 0 ++#define PVT_WRITE 1 ++#ifndef CONFIG_ARM64 ++#define BT1_PVT_DIRECT_REG_ACCESS ++#endif ++ + /* + * enum pvt_sensor_type - Baikal-T1 PVT sensor types (correspond to each PVT + * sampling mode) +@@ -217,6 +224,7 @@ struct pvt_hwmon { + enum pvt_sensor_type sensor; + struct pvt_cache cache[PVT_SENSORS_NUM]; + ktime_t timeout; ++ int pvt_id; + }; + + /* +-- +2.31.1 + diff --git a/0614-bt1-pvt-adjust-probing-for-BE-M1000-SoC.patch b/0614-bt1-pvt-adjust-probing-for-BE-M1000-SoC.patch new file mode 100644 index 0000000..668e72f --- /dev/null +++ b/0614-bt1-pvt-adjust-probing-for-BE-M1000-SoC.patch @@ -0,0 +1,135 @@ +From 1048ea091c614a2514a0e851d6c614de572e1141 Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Thu, 3 Dec 2020 19:22:04 +0400 +Subject: [PATCH 614/625] bt1-pvt: adjust probing for BE-M1000 SoC + +The registers and clocks are managed by the secure world and can't be +accessed by Linux directly. Therefore skip enabling/disabling clocks +and ioremapping registers on BE-M1000. + +Also a sensor is identified by special `pvt_id' instead of registers base +address. pvt_id is initialized from the device tree. +--- + drivers/hwmon/Kconfig | 7 ++++--- + drivers/hwmon/bt1-pvt.c | 28 ++++++++++++++++++++++++---- + 2 files changed, 28 insertions(+), 7 deletions(-) + +diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig +index a850e4f0e0bd..efaf8ba21e7b 100644 +--- a/drivers/hwmon/Kconfig ++++ b/drivers/hwmon/Kconfig +@@ -415,10 +415,11 @@ config SENSORS_ATXP1 + will be called atxp1. + + config SENSORS_BT1_PVT +- tristate "Baikal-T1 Process, Voltage, Temperature sensor driver" +- depends on MIPS_BAIKAL_T1 || COMPILE_TEST ++ tristate "Baikal-T1/M Process, Voltage, Temperature sensor driver" ++ depends on MIPS_BAIKAL_T1 || ARCH_BAIKAL || COMPILE_TEST ++ default m if MIPS_BAIKAL_T1 || ARCH_BAIKAL + help +- If you say yes here you get support for Baikal-T1 PVT sensor ++ If you say yes here you get support for Baikal-M or Baikal-T1 PVT sensor + embedded into the SoC. + + This driver can also be built as a module. If so, the module will be +diff --git a/drivers/hwmon/bt1-pvt.c b/drivers/hwmon/bt1-pvt.c +index d1f66de6a2cd..38774ec33ee1 100644 +--- a/drivers/hwmon/bt1-pvt.c ++++ b/drivers/hwmon/bt1-pvt.c +@@ -950,6 +950,7 @@ static int pvt_request_regs(struct pvt_hwmon *pvt) + { + struct platform_device *pdev = to_platform_device(pvt->dev); + struct resource *res; ++ int err = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { +@@ -957,11 +958,19 @@ static int pvt_request_regs(struct pvt_hwmon *pvt) + return -EINVAL; + } + ++#ifdef BT1_PVT_DIRECT_REG_ACCESS + pvt->regs = devm_ioremap_resource(pvt->dev, res); + if (IS_ERR(pvt->regs)) { + dev_err(pvt->dev, "Couldn't map PVT registers\n"); + return PTR_ERR(pvt->regs); + } ++#else ++ err = of_property_read_u32(pvt->dev->of_node, "pvt_id", &(pvt->pvt_id)); ++ if (err) { ++ dev_err(pvt->dev, "couldn't find pvt_id\n"); ++ return err; ++ } ++#endif + + return 0; + } +@@ -975,11 +984,12 @@ static void pvt_disable_clks(void *data) + + static int pvt_request_clks(struct pvt_hwmon *pvt) + { +- int ret; ++ int ret = 0; + + pvt->clks[PVT_CLOCK_APB].id = "pclk"; + pvt->clks[PVT_CLOCK_REF].id = "ref"; + ++#ifdef BT1_PVT_DIRECT_REG_ACCESS + ret = devm_clk_bulk_get(pvt->dev, PVT_CLOCK_NUM, pvt->clks); + if (ret) { + dev_err(pvt->dev, "Couldn't get PVT clocks descriptors\n"); +@@ -997,8 +1007,11 @@ static int pvt_request_clks(struct pvt_hwmon *pvt) + dev_err(pvt->dev, "Can't add PVT clocks disable action\n"); + return ret; + } +- +- return 0; ++#else ++ pvt->clks[PVT_CLOCK_APB].clk = NULL; ++ pvt->clks[PVT_CLOCK_REF].clk = NULL; ++#endif ++ return ret; + } + + static int pvt_check_pwr(struct pvt_hwmon *pvt) +@@ -1038,14 +1051,17 @@ static int pvt_check_pwr(struct pvt_hwmon *pvt) + + static int pvt_init_iface(struct pvt_hwmon *pvt) + { +- unsigned long rate; + u32 trim, temp; + ++#ifdef BT1_PVT_DIRECT_REG_ACCESS ++ unsigned long rate; ++ + rate = clk_get_rate(pvt->clks[PVT_CLOCK_REF].clk); + if (!rate) { + dev_err(pvt->dev, "Invalid reference clock rate\n"); + return -ENODEV; + } ++#endif + + /* + * Make sure all interrupts and controller are disabled so not to +@@ -1074,6 +1090,7 @@ static int pvt_init_iface(struct pvt_hwmon *pvt) + * polled. In that case the formulae will look a bit different: + * Ttotal = 5 * (N / Fclk + Tmin) + */ ++#if defined(BT1_PVT_DIRECT_REG_ACCESS) + #if defined(CONFIG_SENSORS_BT1_PVT_ALARMS) + pvt->timeout = ktime_set(PVT_SENSORS_NUM * PVT_TOUT_DEF, 0); + pvt->timeout = ktime_divns(pvt->timeout, rate); +@@ -1083,6 +1100,9 @@ static int pvt_init_iface(struct pvt_hwmon *pvt) + pvt->timeout = ktime_divns(pvt->timeout, rate); + pvt->timeout = ktime_add_ns(pvt->timeout, PVT_TOUT_MIN); + #endif ++#else ++ pvt->timeout = ktime_set(0, PVT_TOUT_MIN * PVT_SENSORS_NUM); ++#endif + + trim = PVT_TRIM_DEF; + if (!of_property_read_u32(pvt->dev->of_node, +-- +2.31.1 + diff --git a/0615-bt1-pvt-added-compatible-baikal-pvt.patch b/0615-bt1-pvt-added-compatible-baikal-pvt.patch new file mode 100644 index 0000000..3d88af9 --- /dev/null +++ b/0615-bt1-pvt-added-compatible-baikal-pvt.patch @@ -0,0 +1,27 @@ +From 7028d81bce581b1075c55b34f2596f16ae8686ce Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Thu, 3 Dec 2020 19:24:00 +0400 +Subject: [PATCH 615/625] bt1-pvt: added compatible baikal,pvt + +So the driver will be loaded on existing BE-M1000 based boards. + +X-DONTUPSTREAM +--- + drivers/hwmon/bt1-pvt.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/hwmon/bt1-pvt.c b/drivers/hwmon/bt1-pvt.c +index 38774ec33ee1..585614a384e1 100644 +--- a/drivers/hwmon/bt1-pvt.c ++++ b/drivers/hwmon/bt1-pvt.c +@@ -1240,6 +1240,7 @@ static int pvt_probe(struct platform_device *pdev) + + static const struct of_device_id pvt_of_match[] = { + { .compatible = "baikal,bt1-pvt" }, ++ { .compatible = "baikal,pvt" }, + { } + }; + MODULE_DEVICE_TABLE(of, pvt_of_match); +-- +2.31.1 + diff --git a/0616-Baikal-M-PCIe-driver-from-SDK-M-4.3.patch b/0616-Baikal-M-PCIe-driver-from-SDK-M-4.3.patch new file mode 100644 index 0000000..e7614fe --- /dev/null +++ b/0616-Baikal-M-PCIe-driver-from-SDK-M-4.3.patch @@ -0,0 +1,1228 @@ +From 72b2f9de7609df9b7e7a60e4a9bfca45463cfac5 Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Fri, 20 Mar 2020 13:57:57 +0400 +Subject: [PATCH 616/625] Baikal-M: PCIe driver from SDK-M 4.3 + +Improvements: + +* Adjusted the driver so it can built as a module. Hardware + initialization takes about 60 seconds on MBM1.0 board, and + the screen is blank during that time. When built as a module + probing runs concurrently with other boot activities (unless + booting from a PCIe device) + +* Avoid loading the driver on boards with incompatible firmware + (from SDK-M 4.4) since it causes the kernel panic during probe: + +[ 9.317236] SError Interrupt on CPU4, code 0xbf000002 -- SError +[ 9.317239] CPU: 4 PID: 899 Comm: systemd-udevd Not tainted 5.4.80-std-def-alt1 #1 +[ 9.317241] Hardware name: Baikal Electronics Baikal-M mitx board (DT) +[ 9.317243] pstate: 20400085 (nzCv daIf +PAN -UAO) +[ 9.317246] pc : regmap_mmio_read32le+0x28/0x60 +[ 9.317247] lr : regmap_mmio_read+0x48/0x70 +[ 9.317249] sp : ffff800011ca3750 +[ 9.317251] x29: ffff800011ca3750 x28: ffff800008e09258 +[ 9.317254] x27: 0000000000000028 x26: ffff800008e07040 +[ 9.317257] x25: ffff00097170c1c0 x24: ffff800008e08420 +[ 9.317260] x23: ffff800011ca3874 x22: 00000000000500e8 +[ 9.317262] x21: ffff800011ca3874 x20: ffff0009727d5980 +[ 9.317265] x19: 00000000000500e8 x18: 0000000000000001 +[ 9.317268] x17: 0000000000000000 x16: ffff800011ca37f4 +[ 9.317270] x15: ffff00097170c6d8 x14: ffffffffffffffff +[ 9.317273] x13: ffff000974e747c0 x12: 0000000000000018 +[ 9.317276] x11: 0101010101010101 x10: 7f7f7f7f7f7f7f7f +[ 9.317279] x9 : fefefefeff736472 x8 : 7f7f7f7f7f7f7f7f +[ 9.317281] x7 : 64712c2f6468626f x6 : ffff0009727d568c +[ 9.317284] x5 : ffff000972eee168 x4 : 0000000000000000 +[ 9.317286] x3 : ffff800010813c38 x2 : ffff800010814100 +[ 9.317289] x1 : 00000000000500e8 x0 : 0000000000000000 +[ 9.317292] Kernel panic - not syncing: Asynchronous SError Interrupt +[ 9.317294] CPU: 4 PID: 899 Comm: systemd-udevd Not tainted 5.4.80-std-def-alt1 #1 +[ 9.317296] Hardware name: Baikal Electronics Baikal-M mitx board (DT) +[ 9.317298] Call trace: +[ 9.317299] dump_backtrace+0x0/0x160 +[ 9.317301] show_stack+0x24/0x30 +[ 9.317302] dump_stack+0xb4/0x114 +[ 9.317304] panic+0x150/0x368 +[ 9.317306] nmi_panic+0x94/0x98 +[ 9.317307] arm64_serror_panic+0x84/0x90 +[ 9.317309] do_serror+0x11c/0x120 +[ 9.317310] el1_error+0xbc/0x160 +[ 9.317312] regmap_mmio_read32le+0x28/0x60 +[ 9.317314] regmap_mmio_read+0x48/0x70 +[ 9.317315] _regmap_bus_reg_read+0x38/0x48 +[ 9.317317] _regmap_read+0x6c/0x168 +[ 9.317319] regmap_read+0x50/0x78 +[ 9.317320] baikal_pcie_hw_init_m+0xe4/0x170 [pcie_baikal] +[ 9.317322] baikal_pcie_probe+0x294/0x530 [pcie_baikal] +[ 9.317324] platform_drv_probe+0x58/0xa8 +[ 9.317325] really_probe+0xe0/0x330 +[ 9.317327] driver_probe_device+0x5c/0xf0 +[ 9.317329] device_driver_attach+0x74/0x80 +[ 9.317330] __driver_attach+0x64/0xe0 +[ 9.317332] bus_for_each_dev+0x80/0xd0 +[ 9.317334] driver_attach+0x30/0x40 +[ 9.317335] bus_add_driver+0x154/0x1e8 +[ 9.317337] driver_register+0x64/0x110 +[ 9.317338] __platform_driver_register+0x54/0x60 +[ 9.317340] baikal_pcie_driver_init+0x24/0x1000 [pcie_baikal] +[ 9.317342] do_one_initcall+0x50/0x24c +[ 9.317343] do_init_module+0x5c/0x248 +[ 9.317345] load_module+0x1e08/0x2258 +[ 9.317347] __do_sys_finit_module+0xd0/0xe8 +[ 9.317348] __arm64_sys_finit_module+0x28/0x38 +[ 9.317350] el0_svc_common.constprop.0+0x74/0x168 +[ 9.317352] el0_svc_handler+0x34/0xa0 +[ 9.317353] el0_svc+0x8/0x260 +[ 9.324036] SMP: stopping secondary CPUs +[ 9.324038] Kernel Offset: disabled +[ 9.324039] CPU features: 0x0002,20006008 +[ 9.324041] Memory Limit: none + +Note: detection of new firmware is not 100% reliable. +--- + drivers/pci/controller/Kconfig | 12 + + drivers/pci/controller/dwc/Makefile | 1 + + drivers/pci/controller/dwc/pcie-baikal.c | 722 +++++++++++++++++++++++ + drivers/pci/controller/dwc/pcie-baikal.h | 217 +++++++ + include/linux/mfd/baikal/lcru-pcie.h | 140 +++++ + 5 files changed, 1092 insertions(+) + create mode 100644 drivers/pci/controller/dwc/pcie-baikal.c + create mode 100644 drivers/pci/controller/dwc/pcie-baikal.h + create mode 100644 include/linux/mfd/baikal/lcru-pcie.h + +diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig +index 64e2f5e379aa..b8a5eb633259 100644 +--- a/drivers/pci/controller/Kconfig ++++ b/drivers/pci/controller/Kconfig +@@ -281,6 +281,18 @@ config PCIE_BRCMSTB + Say Y here to enable PCIe host controller support for + Broadcom STB based SoCs, like the Raspberry Pi 4. + ++config PCI_BAIKAL ++ tristate "Baikal SoC PCIe controller" ++ default m if ARCH_BAIKAL ++ depends on ARCH_BAIKAL ++ depends on OF && HAS_IOMEM ++ depends on PCI_MSI_IRQ_DOMAIN ++ select PCIE_DW ++ help ++ Enables support for the PCIe controller in the Baikal SoC. There ++ are three instances of PCIe controller in Baikal-M. Two of the controllers ++ support PCIe 3.0 x4 and the remaining one supports PCIe 3.0 x8. ++ + config PCI_HYPERV_INTERFACE + tristate "Hyper-V PCI Interface" + depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64 +diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile +index a751553fa0db..85e6ad1954e5 100644 +--- a/drivers/pci/controller/dwc/Makefile ++++ b/drivers/pci/controller/dwc/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_PCI_MESON) += pci-meson.o + obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o + obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o + obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o ++obj-$(CONFIG_PCI_BAIKAL) += pcie-baikal.o + + # The following drivers are for devices that use the generic ACPI + # pci_root.c driver but don't support standard ECAM config access. +diff --git a/drivers/pci/controller/dwc/pcie-baikal.c b/drivers/pci/controller/dwc/pcie-baikal.c +new file mode 100644 +index 000000000000..1eb5f0e780c4 +--- /dev/null ++++ b/drivers/pci/controller/dwc/pcie-baikal.c +@@ -0,0 +1,722 @@ ++/* ++ * pcie-baikal - PCIe controller driver for Baikal SoCs ++ * ++ * Copyright (C) 2019 Baikal Electronics JSC ++ * Author: Pavel Parkhomenko ++ * ++ * Parts of this file were based on sources as follows: ++ * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com ++ * Author: Kishon Vijay Abraham I ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#define DEBUG 1 ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pcie-designware.h" ++#include "pcie-baikal.h" ++ ++ ++#define PCIE_MSI_ADDR_LO 0x820 ++#define PCIE_MSI_ADDR_HI 0x824 ++ ++ ++struct baikal_pcie { ++ struct dw_pcie *pci; ++ int bus_nr; ++ struct regmap *lcru; ++ struct gpio_desc *reset_gpio; ++ char reset_name[32]; ++}; ++ ++#define to_baikal_pcie(x) dev_get_drvdata((x)->dev) ++#define LINK_RETRAIN_TIMEOUT HZ ++ ++#define PORT_LINK_FAST_LINK_MODE (1 << 7) /* Fast Link Mode. */ ++ ++#define PCIE_PHY_RETRIES 1000000 ++#define PHY_ALL_LANES 0xF ++#define PHY_LANE0 0x1 ++ ++/* Baikal-specific registers. */ ++#define PCIE_BK_MGMT_SEL_LANE (0xd04) /* Select lane. */ ++#define PCIE_BK_MGMT_CTRL (0xd08) /* Control management register. */ ++#define PCIE_BK_MGMT_WRITE_DATA (0xd0c) /* Data write register. */ ++#define PCIE_BK_MGMT_READ_DATA (0xd10) /* Data read register. */ ++ ++#define PCIE_MISC_CONTROL_1_OFF (0x8bc) /* to open RO DBI register. */ ++#define DBI_RO_RW_EN (1 << 0) ++ ++#define PCIE_COHERENCE_CONTROL_3_OFF (0x8e8) /* to set cache coherence register. */ ++ ++/* PCIE_BK_MGMT_CTRL */ ++#define BK_MGMT_CTRL_ADDR_MASK (0xFFFFF) /* bits [20:0] */ ++#define BK_MGMT_CTRL_READ (0 << 29) ++#define BK_MGMT_CTRL_WRITE (1 << 29) ++#define BK_MGMT_CTRL_DONE (1 << 30) ++#define BK_MGMT_CTRL_BUSY (1 << 31) ++ ++#define PCIE_LINK_CAPABILITIES_REG (0x7c) /* Link Capabilities Register. */ ++#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG (0x8c) /* Root Control and Capabilities Register. */ ++ ++#define PCIE_LINK_CONTROL_LINK_STATUS_REG (0x80) /* Link Control and Status Register. */ ++/* LINK_CONTROL_LINK_STATUS_REG */ ++#define PCIE_CAP_LINK_SPEED_SHIFT 16 ++#define PCIE_CAP_LINK_SPEED_MASK 0xF0000 ++#define PCIE_CAP_LINK_SPEED_GEN1 0x1 ++#define PCIE_CAP_LINK_SPEED_GEN2 0x2 ++#define PCIE_CAP_LINK_SPEED_GEN3 0x3 ++#define PCIE_STA_LINK_TRAINING 0x8000000 ++#define PCIE_STA_LINK_WIDTH_MASK 0x3f00000 ++#define PCIE_STA_LINK_WIDTH_SHIFT (20) ++ ++#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG (0xa0) /* Link Control 2 and Status 2 Register. */ ++/* PCIE_LINK_CONTROL2_LINK_STATUS2 */ ++#define PCIE_LINK_CONTROL2_GEN_MASK (0xF) ++#define PCIE_LINK_CONTROL2_GEN1 (1) ++#define PCIE_LINK_CONTROL2_GEN2 (2) ++#define PCIE_LINK_CONTROL2_GEN3 (3) ++ ++static inline int dw_pcie_link_is_training(struct dw_pcie *pci) ++{ ++ int reg = dw_pcie_readl_dbi(pci, PCIE_LINK_CONTROL_LINK_STATUS_REG); ++ return reg & PCIE_STA_LINK_TRAINING; ++} ++ ++static void dw_wait_pcie_link_training_done(struct dw_pcie *pci) ++{ ++ unsigned long start_jiffies = jiffies; ++ while (dw_pcie_link_is_training(pci)) { ++ if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) { ++ pr_err("%s: link retrained for too long, timeout occured\n", __func__); ++ break; ++ } ++ udelay(100); ++ } ++} ++ ++static int dw_report_link_performance(struct dw_pcie *pci) ++{ ++ int reg = dw_pcie_readl_dbi(pci, PCIE_LINK_CONTROL_LINK_STATUS_REG); ++ int speed = (reg & PCIE_CAP_LINK_SPEED_MASK) >> PCIE_CAP_LINK_SPEED_SHIFT; ++ int width = (reg & PCIE_STA_LINK_WIDTH_MASK) >> PCIE_STA_LINK_WIDTH_SHIFT; ++ dev_info(pci->dev, "Link Status is GEN%d, x%d\n", speed, width); ++ return speed; ++} ++ ++static inline void dw_pcie_link_retrain(struct dw_pcie *pci, int target_speed) ++{ ++ int reg; ++ unsigned long start_jiffies; ++ ++ // In case link is already training wait for training to complete ++ dw_wait_pcie_link_training_done(pci); ++ ++ // Set desired speed ++ reg = dw_pcie_readl_dbi(pci, PCIE_LINK_CONTROL2_LINK_STATUS2_REG); ++ reg &= ~PCIE_LINK_CONTROL2_GEN_MASK; ++ reg |= target_speed; ++ dw_pcie_writel_dbi(pci, PCIE_LINK_CONTROL2_LINK_STATUS2_REG, reg); ++ ++ // Set Retrain Link bit ++ reg = dw_pcie_readl_dbi(pci, PCIE_LINK_CONTROL_LINK_STATUS_REG); ++ reg |= PCI_EXP_LNKCTL_RL; ++ dw_pcie_writel_dbi(pci, PCIE_LINK_CONTROL_LINK_STATUS_REG, reg); ++ ++ /* Wait for link training begin */ ++ start_jiffies = jiffies; ++ while (!dw_pcie_link_is_training(pci)) { ++ if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) { ++ pr_err("%s: link retrained for too long, timeout occured\n", __func__); ++ break; ++ } ++ udelay(100); ++ } ++ ++ /* Wait for link training end */ ++ dw_wait_pcie_link_training_done(pci); ++ ++ if(dw_pcie_wait_for_link(pci) == 0) { ++ dw_report_link_performance(pci); ++ } ++} ++ ++ ++static void baikal_pcie_link_speed_fixup(struct pci_dev *pdev) ++{ ++ int reg, speed, width, target_speed; ++ struct pcie_port *pp = pdev->bus->sysdata; ++ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ ++ reg = dw_pcie_readl_dbi(pci, PCIE_LINK_CAPABILITIES_REG); ++ speed = reg & PCI_EXP_LNKCAP_SLS; ++ if (speed > PCI_EXP_LNKCAP_SLS_2_5GB) { ++ pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®); ++ speed = reg & PCI_EXP_LNKCAP_SLS; ++ width = (reg & PCI_EXP_LNKCAP_MLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; ++ dev_info(&pdev->dev, "Link Capability is GEN%d, x%d\n", speed, width); ++ if (speed > PCI_EXP_LNKCAP_SLS_2_5GB) { ++ target_speed = speed; ++ if (dw_report_link_performance(pci) < target_speed) { ++ dev_info(&pdev->dev, "retrain link to GEN%d\n", target_speed); ++ dw_pcie_link_retrain(pci, target_speed); ++ dw_report_link_performance(pci); ++ return; ++ } ++ } ++ } ++} ++ ++static void baikal_pcie_retrain_links(const struct pci_bus *bus) ++{ ++ struct pci_dev *dev; ++ struct pci_bus *child; ++ ++ list_for_each_entry(dev, &bus->devices, bus_list) ++ baikal_pcie_link_speed_fixup(dev); ++ ++ list_for_each_entry(dev, &bus->devices, bus_list) { ++ child = dev->subordinate; ++ if (child) ++ baikal_pcie_retrain_links(child); ++ } ++} ++ ++static int baikal_pcie_link_up(struct dw_pcie *pci) ++{ ++ struct baikal_pcie *rc = to_baikal_pcie(pci); ++ uint32_t misc_reg; ++ uint32_t class_reg; ++ u32 lcru_reg, reg; ++ ++ // Set class ++ lcru_reg = baikal_pcie_lcru_readl(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->bus_nr)); ++ baikal_pcie_lcru_writel(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->bus_nr), lcru_reg & (~BAIKAL_PCIE_DBI2_MODE)); ++ ++ misc_reg = dw_pcie_readl_dbi(pci, PCIE_MISC_CONTROL_1_OFF); ++ misc_reg |= DBI_RO_RW_EN; ++ ++ dw_pcie_writel_dbi(pci, PCIE_MISC_CONTROL_1_OFF, misc_reg); ++ class_reg = dw_pcie_readl_dbi(pci, PCI_CLASS_REVISION); ++ ++ class_reg = (0x604 << 16) | (class_reg & 0xff); // class PCI_PCI_BRIDGE=0x604 ++ dw_pcie_writel_dbi(pci, PCI_CLASS_REVISION, class_reg); ++ ++ misc_reg &= ~DBI_RO_RW_EN; ++ dw_pcie_writel_dbi(pci, PCIE_MISC_CONTROL_1_OFF, misc_reg); ++ baikal_pcie_lcru_writel(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->bus_nr), lcru_reg); ++ reg = baikal_pcie_lcru_readl(rc->lcru, BAIKAL_LCRU_PCIE_STATUS(rc->bus_nr)); ++ return !!(reg & (BAIKAL_PCIE_RDLH_LINKUP | BAIKAL_PCIE_SMLH_LINKUP)); ++} ++ ++static void baikal_pcie_cease_link(struct baikal_pcie *rc) ++{ ++ u32 reg; ++ reg = baikal_pcie_lcru_readl(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->bus_nr)); ++ reg &= ~BAIKAL_PCIE_LTSSM_ENABLE; ++ baikal_pcie_lcru_writel(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->bus_nr), reg); ++} ++ ++static int baikal_pcie_establish_link(struct baikal_pcie *rc) ++{ ++ struct dw_pcie *pci = rc->pci; ++ struct device *dev = pci->dev; ++ u32 reg; ++ int ok; ++ ++ if (baikal_pcie_link_up(pci)) { ++ dev_err(dev, "link is already up\n"); ++ return 0; ++ } ++ ++ reg = baikal_pcie_lcru_readl(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->bus_nr)); ++ reg |= BAIKAL_PCIE_LTSSM_ENABLE; ++ baikal_pcie_lcru_writel(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->bus_nr), reg); ++ ++ ok = dw_pcie_wait_for_link(pci); ++ if(ok == 0) { ++ dw_report_link_performance(pci); ++ } ++ return ok; ++} ++ ++static int baikal_pcie_host_init(struct pcie_port *pp) ++{ ++ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ struct baikal_pcie *baikal_pcie = to_baikal_pcie(pci); ++ ++ dw_pcie_setup_rc(pp); ++ baikal_pcie_establish_link(baikal_pcie); ++ return 0; ++} ++ ++static int baikal_pcie_msi_host_init(struct pcie_port *pp) ++{ ++ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ struct device *dev = pci->dev; ++ struct device_node *np = dev->of_node; ++ struct device_node *msi_node; ++ ++ /* ++ * The MSI domain is set by the generic of_msi_configure(). This ++ * .msi_host_init() function keeps us from doing the default MSI ++ * domain setup in dw_pcie_host_init() and also enforces the ++ * requirement that "msi-parent" exists. ++ */ ++ msi_node = of_parse_phandle(np, "msi-parent", 0); ++ if (!msi_node) { ++ dev_warn(dev, "failed to find msi-parent\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static const struct dw_pcie_host_ops baikal_pcie_host_ops = { ++ .host_init = baikal_pcie_host_init, ++ .msi_host_init = baikal_pcie_msi_host_init, ++}; ++ ++static const struct dw_pcie_ops baikal_pcie_ops = { ++ .link_up = baikal_pcie_link_up, ++}; ++ ++static int baikal_pcie_get_msi(struct baikal_pcie *rc, ++ struct device_node *msi_node, ++ u64 *msi_addr) ++{ ++ struct dw_pcie *pci = rc->pci; ++ struct device *dev = pci->dev; ++ int ret; ++ struct resource res; ++ memset(&res, 0, sizeof(res)); ++ ++ /* ++ * Check if 'msi-parent' points to ARM GICv3 ITS, which is the only ++ * supported MSI controller. ++ */ ++ if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) { ++ dev_err(dev, "unable to find compatible MSI controller\n"); ++ return -ENODEV; ++ } ++ ++ /* derive GITS_TRANSLATER address from GICv3 */ ++ ret = of_address_to_resource(msi_node, 0, &res); ++ if (ret < 0) { ++ dev_err(dev, "unable to obtain MSI controller resources\n"); ++ return ret; ++ } ++ ++ *msi_addr = res.start + GITS_TRANSLATER; ++ return 0; ++} ++ ++static int baikal_pcie_msi_steer(struct baikal_pcie *rc, ++ struct device_node *msi_node) ++{ ++ struct dw_pcie *pci = rc->pci; ++ struct device *dev = pci->dev; ++ int ret; ++ u64 msi_addr; ++ ++ ret = baikal_pcie_get_msi(rc, msi_node, &msi_addr); ++ if (ret < 0) { ++ dev_err(dev, "MSI steering failed\n"); ++ return ret; ++ } ++ ++ /* Program the msi_data */ ++ dw_pcie_write(pci->dbi_base + PCIE_MSI_ADDR_LO, 4, ++ lower_32_bits(msi_addr)); ++ dw_pcie_write(pci->dbi_base + PCIE_MSI_ADDR_HI, 4, ++ upper_32_bits(msi_addr)); ++ ++ return 0; ++} ++ ++int baikal_msi_init(struct baikal_pcie *rc, struct device_node *node) ++{ ++ if (!of_find_property(node, "msi-controller", NULL)) { ++ pr_err("%s: couldn't find msi-controller property in FDT\n", __func__); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ ++static int baikal_pcie_msi_enable(struct baikal_pcie *rc) ++{ ++ struct dw_pcie *pci = rc->pci; ++ struct device *dev = pci->dev; ++ struct device_node *msi_node; ++ int ret; ++ ++ /* ++ * The "msi-parent" phandle needs to exist ++ * for us to obtain the MSI node. ++ */ ++ ++ msi_node = of_parse_phandle(dev->of_node, "msi-parent", 0); ++ if (!msi_node) { ++ dev_err(dev, "failed to read msi-parent from FDT\n"); ++ return -ENODEV; ++ } ++ ++ ret = baikal_pcie_msi_steer(rc, msi_node); ++ if (ret) ++ goto out_put_node; ++ ++out_put_node: ++ of_node_put(msi_node); ++ return ret; ++} ++ ++static irqreturn_t baikal_pcie_handle_error_irq(struct baikal_pcie *rc) ++{ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t baikal_pcie_err_irq_handler(int irq, void *priv) ++{ ++ struct baikal_pcie *rc = priv; ++ ++ return baikal_pcie_handle_error_irq(rc); ++} ++ ++static int baikal_add_pcie_port(struct baikal_pcie *rc, ++ struct platform_device *pdev) ++{ ++ struct dw_pcie *pci = rc->pci; ++ struct pcie_port *pp = &pci->pp; ++ struct resource *res; ++ int irq; ++ int ret; ++ ++ pci->dev = &pdev->dev; ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); ++ if (res) { ++ pci->dbi_base = devm_ioremap_resource(pci->dev, res); ++ if (IS_ERR(pci->dbi_base)) { ++ dev_err(pci->dev, "error with ioremap\n"); ++ return PTR_ERR(pci->dbi_base); ++ } ++ } else { ++ dev_err(pci->dev, "missing *dbi* reg space\n"); ++ return -EINVAL; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ dev_err(pci->dev, "missing IRQ resource: %d\n", irq); ++ return irq; ++ } ++ ++ /* TODO enable it later */ ++ ret = request_irq(irq, baikal_pcie_err_irq_handler, IRQF_SHARED, ++ "baikal-pcie-error-irq", rc); ++ if (ret < 0) { ++ dev_err(pci->dev, "failed to request error IRQ %d\n", ++ irq); ++ return ret; ++ } ++ /* end TODO */ ++ ++ if (IS_ENABLED(CONFIG_PCI_MSI)) { ++ ret = baikal_pcie_msi_enable(rc); ++ if (ret) { ++ dev_err(pci->dev, "failed to initialize MSI\n"); ++ return ret; ++ } ++ } ++ ++ pp->ops = &baikal_pcie_host_ops; ++ ++ ret = dw_pcie_host_init(pp); ++ if (ret) { ++ dev_err(pci->dev, "failed to initialize host\n"); ++ return ret; ++ } ++ baikal_pcie_retrain_links(pp->bridge->bus); ++ ++ return 0; ++} ++ ++static int baikal_pcie_hw_init_m(struct baikal_pcie *rc) ++{ ++ u32 reg; ++ ++ // TODO add PHY configuration if needed ++ ++ /* Deassert PHY reset */ ++ reg = baikal_pcie_lcru_readl(rc->lcru, BAIKAL_LCRU_PCIE_RESET(rc->bus_nr)); ++ reg &= ~BAIKAL_PCIE_PHY_RESET; ++ baikal_pcie_lcru_writel(rc->lcru, BAIKAL_LCRU_PCIE_RESET(rc->bus_nr), reg); ++ ++ // TODO timeout? ++ ++ /* Enable access to the PHY registers */ ++ reg = baikal_pcie_lcru_readl(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->bus_nr)); ++ reg |= (BAIKAL_PCIE_PHY_MGMT_ENABLE | BAIKAL_PCIE_DBI2_MODE); ++ baikal_pcie_lcru_writel(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->bus_nr), reg); ++ ++ // TODO timeout? ++ ++ /* Clear all software controlled resets of the controller */ ++ reg = baikal_pcie_lcru_readl(rc->lcru, BAIKAL_LCRU_PCIE_RESET(rc->bus_nr)); ++ reg &= ~(BAIKAL_PCIE_ADB_PWRDWN | BAIKAL_PCIE_HOT_RESET | ++ BAIKAL_PCIE_NONSTICKY_RST | BAIKAL_PCIE_STICKY_RST | ++ BAIKAL_PCIE_PWR_RST | BAIKAL_PCIE_CORE_RST | BAIKAL_PCIE_PIPE_RESET); ++ baikal_pcie_lcru_writel(rc->lcru, BAIKAL_LCRU_PCIE_RESET(rc->bus_nr), reg); ++ ++ // TODO timeout? ++ ++ if (IS_ENABLED(CONFIG_PCI_MSI)) { ++ ++ /* Set up the MSI translation mechanism: */ ++ ++ /* First, set MSI_AWUSER to 0 */ ++ reg = baikal_pcie_lcru_readl(rc->lcru, BAIKAL_LCRU_PCIE_MSI_TRANS_CTL0); ++ reg &= ~BAIKAL_PCIE_MSI_AWUSER_MASK; ++ reg |= (0 << BAIKAL_PCIE_MSI_AWUSER_SHIFT); ++ baikal_pcie_lcru_writel(rc->lcru, BAIKAL_LCRU_PCIE_MSI_TRANS_CTL0, reg); ++ ++ // TODO timeout? ++ ++ /* Second, enable MSI, the RC number for all RC is 0*/ ++ reg = baikal_pcie_lcru_readl(rc->lcru, BAIKAL_LCRU_PCIE_MSI_TRANS_CTL2); ++ reg |= BAIKAL_PCIE_MSI_TRANS_EN(rc->bus_nr); ++ reg &= ~BAIKAL_PCIE_MSI_RCNUM_MASK(rc->bus_nr); ++ baikal_pcie_lcru_writel(rc->lcru, BAIKAL_LCRU_PCIE_MSI_TRANS_CTL2, reg); ++ ++ } ++ ++ return 0; ++ ++} ++ ++static const struct of_device_id of_baikal_pcie_match[] = { ++ { ++ .compatible = "baikal,pcie-m", ++ .data = baikal_pcie_hw_init_m, ++ }, ++ {}, ++}; ++ ++/* XXX: this driver is incompatible with firmware from SDK-M version 4.4 ++ * (and possibly later versions). Unfortunately the vendor does not provide ++ * any reasonable way to find out the firmware version. Hence this guess: ++ * if the "/soc" node exists - it's SDK-M 4.4 ++ * otherwise it's SDK-M 4.3 (hopefully) ++ */ ++static int guess_incompat_firmware(void) ++{ ++ int ret = 0; ++ struct device_node *np = NULL; ++ np = of_find_node_by_path("/soc"); ++ if (np) { ++ ret = 1; ++ of_node_put(np); ++ } ++ return ret; ++} ++ ++static int baikal_pcie_probe(struct platform_device *pdev) ++{ ++ struct dw_pcie *pci; ++ struct baikal_pcie *pcie; ++ struct device *dev = &pdev->dev; ++ const struct of_device_id *of_id; ++ int err; ++ int (*hw_init_fn)(struct baikal_pcie *); ++ u32 index[2]; ++ enum of_gpio_flags flags; ++ int reset_gpio; ++ pr_info("%s: ENTER\n", __func__); ++ ++ if (guess_incompat_firmware()) { ++ dev_err(dev, "detected incompatible firmware, bailing out\n"); ++ return -ENODEV; ++ } ++ ++ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); ++ if (!pcie) { ++ dev_err(dev, "failed to allocate memory\n"); ++ return -ENOMEM; ++ } ++ ++ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); ++ if (!pci) { ++ dev_err(dev, "failed to allocate memory [2]\n"); ++ return -ENOMEM; ++ } ++ pci->dev = dev; ++ pci->ops = &baikal_pcie_ops; ++ ++ pcie->pci = pci; ++ ++ pcie->lcru = syscon_regmap_lookup_by_phandle(dev->of_node, ++ "baikal,pcie-lcru"); ++ if (IS_ERR(pcie->lcru)) { ++ dev_err(dev, "No LCRU phandle specified\n"); ++ pcie->lcru = NULL; ++ return -EINVAL; ++ } ++ ++ if (of_property_read_u32_array(dev->of_node, ++ "baikal,pcie-lcru", index, 2)) { ++ dev_err(dev, "failed to read LCRU\n"); ++ pcie->lcru = NULL; ++ return -EINVAL; ++ } ++ pcie->bus_nr = index[1]; ++ ++ of_id = of_match_device(of_baikal_pcie_match, dev); ++ if (!of_id || !of_id->data) { ++ dev_err(dev, "device can't be handled by pcie-baikal\n"); ++ return -EINVAL; ++ } ++ hw_init_fn = of_id->data; ++ ++ pm_runtime_enable(dev); ++ err = pm_runtime_get_sync(dev); ++ if (err < 0) { ++ dev_err(dev, "pm_runtime_get_sync failed\n"); ++ goto err_pm_disable; ++ } ++ ++ ++ baikal_pcie_cease_link(pcie); ++ ++ /* LINK DISABLED */ ++ reset_gpio = of_get_named_gpio_flags(dev->of_node, "reset-gpios", 0, &flags); ++ if (reset_gpio != -EPROBE_DEFER && gpio_is_valid(reset_gpio)) { ++ unsigned long gpio_flags; ++ ++ snprintf(pcie->reset_name, 32, "pcie%d-reset", pcie->bus_nr); ++ if (flags & OF_GPIO_ACTIVE_LOW) ++ gpio_flags = GPIOF_ACTIVE_LOW | GPIOF_OUT_INIT_LOW; ++ else ++ gpio_flags = GPIOF_OUT_INIT_HIGH; ++ err = devm_gpio_request_one(dev, reset_gpio, gpio_flags, ++ pcie->reset_name); ++ if (err) { ++ dev_err(dev, "request GPIO failed (%d)\n", err); ++ goto err_pm_disable; ++ } ++ pcie->reset_gpio = gpio_to_desc(reset_gpio); ++ ++ udelay(100); ++//vvv: do it now or later in baikal_pcie_host_init()? ++ gpiod_set_value_cansleep(pcie->reset_gpio, 0); ++ } ++ ++ err = hw_init_fn(pcie); ++ if (err) { ++ //dev_info(dev, "PCIe link down\n"); // TODO PHY not initialized! ++ err = 0; ++ goto err_pm_put; ++ } ++ /* PHY INITIALIZED */ ++ platform_set_drvdata(pdev, pcie); ++ ++ err = baikal_add_pcie_port(pcie, pdev); ++ if (err < 0) ++ //goto err_gpio; TODO ++ goto err_pm_put; ++ ++ return 0; ++ ++err_pm_put: ++ pm_runtime_put(dev); ++ ++err_pm_disable: ++ pm_runtime_disable(dev); ++ ++err_phy: ++ return err; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int baikal_pcie_suspend(struct device *dev) ++{ ++ struct baikal_pcie *rc = dev_get_drvdata(dev); ++ struct dw_pcie *pci = rc->pci; ++ u32 val; ++ ++ /* clear MSE */ ++ val = dw_pcie_readl_dbi(pci, PCI_COMMAND); ++ val &= ~PCI_COMMAND_MEMORY; ++ dw_pcie_writel_dbi(pci, PCI_COMMAND, val); ++ ++ return 0; ++} ++ ++static int baikal_pcie_resume(struct device *dev) ++{ ++ struct baikal_pcie *rc = dev_get_drvdata(dev); ++ struct dw_pcie *pci = rc->pci; ++ u32 val; ++ ++ /* set MSE */ ++ val = dw_pcie_readl_dbi(pci, PCI_COMMAND); ++ val |= PCI_COMMAND_MEMORY; ++ dw_pcie_writel_dbi(pci, PCI_COMMAND, val); ++ ++ return 0; ++} ++ ++static int baikal_pcie_suspend_noirq(struct device *dev) ++{ ++ return 0; ++} ++ ++static int baikal_pcie_resume_noirq(struct device *dev) ++{ ++ return 0; ++} ++#endif ++ ++static const struct dev_pm_ops baikal_pcie_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(baikal_pcie_suspend, baikal_pcie_resume) ++ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(baikal_pcie_suspend_noirq, ++ baikal_pcie_resume_noirq) ++}; ++ ++static struct platform_driver baikal_pcie_driver = { ++ .driver = { ++ .name = "baikal-pcie", ++ .of_match_table = of_baikal_pcie_match, ++ .suppress_bind_attrs = true, ++ .pm = &baikal_pcie_pm_ops, ++ }, ++ .probe = baikal_pcie_probe, ++}; ++ ++MODULE_DEVICE_TABLE(of, of_baikal_pcie_match); ++module_platform_driver(baikal_pcie_driver); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/pci/controller/dwc/pcie-baikal.h b/drivers/pci/controller/dwc/pcie-baikal.h +new file mode 100644 +index 000000000000..f59100cf0c6d +--- /dev/null ++++ b/drivers/pci/controller/dwc/pcie-baikal.h +@@ -0,0 +1,217 @@ ++/* ++ * pcie-baikal - PCIe controller driver for Baikal SoCs ++ * ++ * Copyright (C) 2019 Baikal Electronics JSC ++ * Author: Pavel Parkhomenko ++ * ++ * Parts of this file were based on sources as follows: ++ * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com ++ * Author: Kishon Vijay Abraham I ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#define PCI_VENDOR_ID_BAIKAL 0x1d39 ++ ++#define PCIE_GEN2_CTRL_OFF (0x80c) /* Link Width and Speed Change Control Register. */ ++ ++/* PHY control registers. */ ++#define PCIE_PHY_DWC_GLBL_PLL_CFG_0 (0x1c000) /* PLL Global Configuration Register #0 */ ++#define PCIE_PHY_DWC_GLBL_PLL_CFG_1 (0x1c001) /* PLL Global Configuration Register #1 */ ++#define PCIE_PHY_DWC_GLBL_PLL_CFG_2 (0x1c002) /* PLL Global Configuration Register #2 */ ++#define PCIE_PHY_DWC_GLBL_PLL_CFG_3 (0x1c003) /* PLL Global Configuration Register #3 */ ++#define PCIE_PHY_DWC_GLBL_PLL_CFG_4 (0x1c004) /* PLL Global Configuration Register #4 */ ++#define PCIE_PHY_DWC_GLBL_MISC_CONFIG_0 (0x1c005) /* Global Miscellaneous Configuration #0 */ ++#define PCIE_PHY_DWC_GLBL_MISC_CONFIG_1 (0x1c006) /* Global Miscellaneous Configuration #1 */ ++#define PCIE_PHY_DWC_SLICE_CFG (0x1c00c) /* Slice Configuration */ ++#define PCIE_PHY_DWC_GLBL_REGU_CFG (0x1c00d) /* Global Regulator Configuration */ ++#define PCIE_PHY_DWC_GLBL_TERM_CFG (0x1c00e) /* Global Termination Calibration Configuration */ ++#define PCIE_PHY_DWC_GLBL_CAL_CFG (0x1c00f) /* Global PLL Calibration Configuration */ ++#define PCIE_PHY_DWC_GLBL_RD_SYNC_STATUS (0x1c010) /* Global Read Synchronization Status */ ++#define PCIE_PHY_DWC_RX_PWR_CTRL_P0 (0x1c014) /* RX Power Controls in Power State P0 */ ++#define PCIE_PHY_DWC_RX_PWR_CTRL_P0S (0x1c015) /* RX Power Controls in Power State P0S */ ++#define PCIE_PHY_DWC_RX_PWR_CTRL_P1 (0x1c016) /* RX Power Controls in Power State P1 */ ++#define PCIE_PHY_DWC_RX_PWR_CTRL_P2 (0x1c017) /* RX Power Controls in Power State P2 */ ++#define PCIE_PHY_DWC_TX_PWR_CTRL_P0_P0S (0x1c018) /* TX Power Controls in Power States P0 and POS */ ++#define PCIE_PHY_DWC_TX_PWR_CTRL_P1_P2 (0x1c019) /* TX Power Controls in Power States P1 and P2 */ ++#define PCIE_PHY_DWC_GLBL_PWR_CTRL (0x1c01a) /* Global Power State Machine Control Override */ ++#define PCIE_PHY_DWC_RX_TXDIR_CTRL_0 (0x1c01d) /* Far-end TX Direction Control Register #0 */ ++#define PCIE_PHY_DWC_RX_TXDIR_CTRL_1 (0x1c01e) /* Far-end TX Direction Control Register #1 */ ++#define PCIE_PHY_DWC_RX_TXDIR_CTRL_2 (0x1c01f) /* Far-end TX Direction Control Register #2 */ ++#define PCIE_PHY_DWC_GLBL_PLL_MONITOR (0x1c020) /* Monitor for SerDes Global to Raw PCS Global Interface */ ++#define PCIE_PHY_DWC_GLBL_TERM_MON_1 (0x1c022) /* Monitor for SerDes Global to Raw PCS Global Interface */ ++#define PCIE_PHY_DWC_GLBL_SDS_PIN_MON_0 (0x1c023) /* Monitor for Raw PCS Global to SerDes Global to Raw PCS Interface */ ++#define PCIE_PHY_DWC_GLBL_SDS_PIN_MON_1 (0x1c024) /* Monitor for Raw PCS Global to SerDes Global to Raw PCS Interface */ ++#define PCIE_PHY_DWC_GLBL_PWR_MON_0 (0x1c025) /* Monitor of Global Power State Machine Values */ ++#define PCIE_PHY_DWC_GLBL_PWR_MON_1 (0x1c026) /* Monitor of Global Power State Machine Values */ ++#define PCIE_PHY_DWC_GLBL_PWR_MON_2 (0x1c027) /* Monitor of Global Power State Machine Values */ ++#define PCIE_PHY_DWC_GLBL_PLL_SSC_FRAC_BASE (0x1c060) /* Global PLL SSC Fractional Base */ ++#define PCIE_PHY_DWC_GLBL_PLL_SSC_CYCLES (0x1c061) /* Global PLL SSC Cycles Configuration */ ++#define PCIE_PHY_DWC_GLBL_PLL_SSC_FMFREQ (0x1c062) /* Global PLL SSC Modulation Frequency */ ++#define PCIE_PHY_DWC_GLBL_PLL_SSC_FREF (0x1c063) /* Global PLL SSC Reference Frequency */ ++#define PCIE_PHY_DWC_GLBL_PLL_SSC_PPM (0x1c064) /* Global PLL SSC PPM */ ++#define PCIE_PHY_DWC_GLBL_PLL_SSC_CFG (0x1c065) /* Global PLL SSC Configuration */ ++#define PCIE_PHY_DWC_GLBL_PLL_SSC_ALU_CMD (0x1c067) /* Global PLL SSC ALU Command */ ++#define PCIE_PHY_DWC_GLBL_PLL_SSC_MON (0x1c069) /* Global PLL SSC Monitor */ ++#define PCIE_PHY_DWC_GLBL_PLL_SSC_ALU_OUT_0 (0x1c06b) /* Global PLL SSC ALU Output Register #0 */ ++#define PCIE_PHY_DWC_GLBL_PLL_SSC_ALU_OUT_1 (0x1c06c) /* Global PLL SSC ALU Output Register #1 */ ++#define PCIE_PHY_DWC_GLBL_PLL_SSC_DIV (0x1c06d) /* Global PLL SSC Divider */ ++#define PCIE_PHY_DWC_GLBL_PLL_SSC_FRAC (0x1c06e) /* Global PLL SSC Fraction */ ++#define PCIE_PHY_DWC_GLBL_TAD (0x1c080) /* Global Test Analog and Digital Monitor */ ++#define PCIE_PHY_DWC_GLBL_TM_ADMON (0x1c081) /* Global Test Mode Analog/Digital Monitor Enable */ ++#define PCIE_PHY_DWC_EQ_WAIT_TIME (0x3c000) /* TX and RX Equalization Wait Times */ ++#define PCIE_PHY_DWC_RDET_TIME (0x3c001) /* Receiver Detect Wait Times */ ++#define PCIE_PHY_DWC_PCS_LANE_LINK_CFG (0x3c002) /* Link Configuration Override */ ++#define PCIE_PHY_DWC_PCS_PLL_CTLIFC_0 (0x3c003) /* PLL Control Interface Override Register #0 */ ++#define PCIE_PHY_DWC_PCS_PLL_CTLIFC_1 (0x3c004) /* PLL Control Interface Override Register #1 */ ++#define PCIE_PHY_DWC_PCS_REG_RD_TIMEOUT (0x3c005) /* Register Read Timeout */ ++#define PCIE_PHY_DWC_PCS_PLL_PCIE1_MODE_0 (0x3c006) /* PLL Configuration Register #0 for PCIe1 */ ++#define PCIE_PHY_DWC_PCS_PLL_PCIE1_MODE_1 (0x3c007) /* PLL Configuration Register #1 for PCIe1 */ ++#define PCIE_PHY_DWC_PCS_LANE_PCIE1_MODE_0 (0x3c008) /* Lane Configuration Register #0 for PCIe1 */ ++#define PCIE_PHY_DWC_PCS_LANE_PCIE1_MODE_1 (0x3c009) /* Lane Configuration Register #1 for PCIe1 */ ++#define PCIE_PHY_DWC_PCS_PLL_PCIE2_MODE_0 (0x3c00a) /* PLL Configuration Register #0 for PCIe2 */ ++#define PCIE_PHY_DWC_PCS_PLL_PCIE2_MODE_1 (0x3c00b) /* PLL Configuration Register #1 for PCIe2 */ ++#define PCIE_PHY_DWC_PCS_LANE_PCIE2_MODE_0 (0x3c00c) /* Lane Configuration Register #0 for PCIe2 */ ++#define PCIE_PHY_DWC_PCS_LANE_PCIE2_MODE_1 (0x3c00d) /* Lane Configuration Register #1 for PCIe2 */ ++#define PCIE_PHY_DWC_PCS_PLL_PCIE3_MODE_0 (0x3c00e) /* PLL Configuration Register #0 for PCIe3 */ ++#define PCIE_PHY_DWC_PCS_PLL_PCIE3_MODE_1 (0x3c00f) /* PLL Configuration Register #1 for PCIe3 */ ++#define PCIE_PHY_DWC_PCS_LANE_PCIE3_MODE_0 (0x3c010) /* Lane Configuration Register #0 for PCIe3 */ ++#define PCIE_PHY_DWC_PCS_LANE_PCIE3_MODE_1 (0x3c011) /* Lane Configuration Register #1 for PCIe3 */ ++#define PCIE_PHY_DWC_PCS_PLL_KX_MODE_1 (0x3c013) /* PLL Configuration Register #1 for KX */ ++#define PCIE_PHY_DWC_PCS_LANE_KX_MODE_0 (0x3c014) /* Lane Configuration Register #0 for KX */ ++#define PCIE_PHY_DWC_PCS_LANE_KX_MODE_1 (0x3c015) /* Lane Configuration Register #1 for KX */ ++#define PCIE_PHY_DWC_PCS_PLL_KX4_MODE_0 (0x3c016) /* PLL Configuration Register #0 for KX4 */ ++#define PCIE_PHY_DWC_PCS_PLL_KX4_MODE_1 (0x3c017) /* PLL Configuration Register #1 for KX4 */ ++#define PCIE_PHY_DWC_PCS_LANE_KX4_MODE_0 (0x3c018) /* Lane Configuration Register #0 for KX4 */ ++#define PCIE_PHY_DWC_PCS_LANE_KX4_MODE_1 (0x3c019) /* Lane Configuration Register #1 for KX4 */ ++#define PCIE_PHY_DWC_PCS_PLL_KR_MODE_0 (0x3c01a) /* PLL Configuration Register #0 for KR */ ++#define PCIE_PHY_DWC_PCS_PLL_KR_MODE_1 (0x3c01b) /* PLL Configuration Register #1 for KR */ ++#define PCIE_PHY_DWC_PCS_LANE_KR_MODE_0 (0x3c01c) /* Lane Configuration Register #0 for KR */ ++#define PCIE_PHY_DWC_PCS_LANE_KR_MODE_1 (0x3c01d) /* Lane Configuration Register #1 for KR */ ++#define PCIE_PHY_DWC_PCS_PLL_SGMII_MODE_0 (0x3c01e) /* PLL Configuration Register #0 for SGMII */ ++#define PCIE_PHY_DWC_PCS_PLL_SGMII_MODE_1 (0x3c01f) /* PLL Configuration Register #1 for SGMII */ ++#define PCIE_PHY_DWC_PCS_LANE_SGMII_MODE_0 (0x3c020) /* Lane Configuration Register #0 for SGMII */ ++#define PCIE_PHY_DWC_PCS_LANE_SGMII_MODE_1 (0x3c021) /* Lane Configuration Register #1 for SGMII */ ++#define PCIE_PHY_DWC_PCS_PLL_QSGMII_MODE_0 (0x3c022) /* PLL Configuration Register #0 for QSGMII */ ++#define PCIE_PHY_DWC_PCS_PLL_QSGMII_MODE_1 (0x3c023) /* PLL Configuration Register #1 for QSGMII */ ++#define PCIE_PHY_DWC_PCS_LANE_QSGMII_MODE_0 (0x3c024) /* Lane Configuration Register #0 for QSGMII */ ++#define PCIE_PHY_DWC_PCS_LANE_QSGMII_MODE_1 (0x3c025) /* Lane Configuration Register #1 for QSGMII */ ++#define PCIE_PHY_DWC_PCS_PLL_CEI_MODE_0 (0x3c026) /* PLL Configuration Register #0 for CEI */ ++#define PCIE_PHY_DWC_PCS_PLL_CEI_MODE_1 (0x3c027) /* PLL Configuration Register #1 for CEI */ ++#define PCIE_PHY_DWC_PCS_LANE_CEI_MODE_0 (0x3c028) /* Lane Configuration Register #0 for CEI */ ++#define PCIE_PHY_DWC_PCS_LANE_CEI_MODE_1 (0x3c029) /* Lane Configuration Register #1 for CEI */ ++#define PCIE_PHY_DWC_PCS_PLL_PCIE1_125M_MODE_0 (0x3c02a) /* PLL Configuration Register #0 for PCIe1 with 125MHz refclk */ ++#define PCIE_PHY_DWC_PCS_PLL_PCIE1_125M_MODE_1 (0x3c02b) /* PLL Configuration Register #1 for PCIe1 with 125MHz refclk */ ++#define PCIE_PHY_DWC_PCS_LANE_PCIE1_125M_MODE_0 (0x3c02c) /* Lane Configuration Register #0 for PCIe1 with 125MHz refclk */ ++#define PCIE_PHY_DWC_PCS_LANE_PCIE1_125M_MODE_1 (0x3c02d) /* Lane Configuration Register #1 for PCIe1 with 125MHz refclk */ ++#define PCIE_PHY_DWC_PCS_PLL_PCIE2_125M_MODE_0 (0x3c02e) /* PLL Configuration Register #0 for PCIe2 with 125MHz refclk */ ++#define PCIE_PHY_DWC_PCS_PLL_PCIE2_125M_MODE_1 (0x3c02f) /* PLL Configuration Register #1 for PCIe2 with 125MHz refclk */ ++#define PCIE_PHY_DWC_PCS_LANE_PCIE2_125M_MODE_0 (0x3c030) /* Lane Configuration Register #0 for PCIe2 with 125MHz refclk */ ++#define PCIE_PHY_DWC_PCS_LANE_PCIE2_125M_MODE_1 (0x3c031) /* Lane Configuration Register #1 for PCIe2 with 125MHz refclk */ ++#define PCIE_PHY_DWC_PCS_PLL_PCIE3_125M_MODE_0 (0x3c032) /* PLL Configuration Register #0 for PCIe3 with 125MHz refclk */ ++#define PCIE_PHY_DWC_PCS_PLL_PCIE3_125M_MODE_1 (0x3c033) /* PLL Configuration Register #1 for PCIe3 with 125MHz refclk */ ++#define PCIE_PHY_DWC_PCS_LANE_PCIE3_125M_MODE_0 (0x3c034) /* Lane Configuration Register #0 for PCIe3 with 125MHz refclk */ ++#define PCIE_PHY_DWC_PCS_LANE_PCIE3_125M_MODE_1 (0x3c035) /* Lane Configuration Register #1 for PCIe3 with 125MHz refclk */ ++#define PCIE_PHY_DWC_PCS_LANE_VMA_COARSE_CTRL_0 (0x3c036) /* Lane VMA Coarse Control Register #0 */ ++#define PCIE_PHY_DWC_PCS_LANE_VMA_COARSE_CTRL_1 (0x3c037) /* Lane VMA Coarse Control Register #1 */ ++#define PCIE_PHY_DWC_PCS_LANE_VMA_COARSE_CTRL_2 (0x3c038) /* Lane VMA Coarse Control Register #2 */ ++#define PCIE_PHY_DWC_PCS_LANE_VMA_FINE_CTRL_0 (0x3c039) /* Lane VMA Fine Control Register #0 */ ++#define PCIE_PHY_DWC_PCS_LANE_VMA_FINE_CTRL_1 (0x3c03a) /* Lane VMA Fine Control Register #1 */ ++#define PCIE_PHY_DWC_PCS_LANE_VMA_FINE_CTRL_2 (0x3c03b) /* Lane VMA Fine Control Register #2 */ ++#define PCIE_PHY_DWC_PCS_LANE_MODE_OVRD (0x3c03c) /* Lane Mode Override in Raw PCS Global and Slice */ ++#define PCIE_PHY_DWC_PCS_LANE_LINK_MON (0x3c040) /* Monitor of MAC to Raw PCS Link Configuration Interface */ ++#define PCIE_PHY_DWC_PCS_MAC_PLLIFC_MON_2 (0x3c043) /* Monitor of MAC to Raw PCS PLL_PCS Divider Value */ ++#define PCIE_PHY_DWC_PCS_MAC_PLLIFC_MON_3 (0x3c044) /* Monitor of MAC to Raw PCS PLL OP_Range and Divider Values */ ++#define PCIE_PHY_DWC_SLICE_TRIM (0x1c040) /* Slice TX and RX Bias Trim Settings */ ++#define PCIE_PHY_DWC_RX_LDLL_CTRL (0x1c043) /* RX Lane DLL Test Controls */ ++#define PCIE_PHY_DWC_RX_SDLL_CTRL (0x1c044) /* RX Slice DLL test controls */ ++#define PCIE_PHY_DWC_SLICE_PCIE1_MODE (0x1c045) /* Slice Configuration Settings for PCIE1 @ 100MHz */ ++#define PCIE_PHY_DWC_SLICE_PCIE2_MODE (0x1c046) /* Slice Configuration Settings for PCIE2 @ 100Mhz */ ++#define PCIE_PHY_DWC_SLICE_PCIE3_MODE (0x1c047) /* Slice Configuration Settings for PCIE3 @ 100Mhz */ ++#define PCIE_PHY_DWC_SLICE_KX_MODE (0x1c048) /* Slice Configuration Settings for KX */ ++#define PCIE_PHY_DWC_SLICE_KX4_MODE (0x1c049) /* Slice Configuration Settings for KX4 */ ++#define PCIE_PHY_DWC_SLICE_KR_MODE (0x1c04a) /* Slice Configuration Settings for KR */ ++#define PCIE_PHY_DWC_SLICE_SGMII_MODE (0x1c04b) /* Slice Configuration Settings for SGMII */ ++#define PCIE_PHY_DWC_SLICE_QSGMII_MODE (0x1c04c) /* Slice Configuration Settings for QSGMII */ ++#define PCIE_PHY_DWC_SLICE_CEI_MODE (0x1c04d) /* Slice Configuration Settings for CEI */ ++#define PCIE_PHY_DWC_SLICE_PCIE1_125M_MODE (0x1c04e) /* Slice Configuration Settings for PCIE1 @ 125MHz */ ++#define PCIE_PHY_DWC_SLICE_PCIE2_125M_MODE (0x1c04f) /* Slice Configuration Settings for PCIE2 @ 125MHz */ ++#define PCIE_PHY_DWC_SLICE_PCIE3_125M_MODE (0x1c050) /* Slice Configuration Settings for PCIE3 @ 125MHz */ ++#define PCIE_PHY_DWC_SLICE_OVRD_MODE (0x1c051) /* Slice Configuration Settings Override */ ++#define PCIE_PHY_DWC_RX_CFG_0 (0x18000) /* Lane RX Configuration Register #0 */ ++#define PCIE_PHY_DWC_RX_CFG_1 (0x18001) /* Lane RX Configuration Register #1 */ ++#define PCIE_PHY_DWC_RX_CFG_2 (0x18002) /* Lane RX Configuration Register #2 */ ++#define PCIE_PHY_DWC_RX_CFG_3 (0x18003) /* Lane RX Configuration Register #3 */ ++#define PCIE_PHY_DWC_RX_CFG_4 (0x18004) /* Lane RX Configuration Register #4 */ ++#define PCIE_PHY_DWC_RX_CFG_5 (0x18005) /* Lane RX Configuration Register #5 */ ++#define PCIE_PHY_DWC_RX_CDR_CTRL_0 (0x18006) /* Lane RX CDR Control Register #0 */ ++#define PCIE_PHY_DWC_RX_CDR_CTRL_1 (0x18007) /* Lane RX CDR Control Register #1 */ ++#define PCIE_PHY_DWC_RX_CDR_CTRL_2 (0x18008) /* Lane RX CDR Control Register #2 */ ++#define PCIE_PHY_DWC_RX_LOOP_CTRL (0x18009) /* Lane RX Loop Control */ ++#define PCIE_PHY_DWC_RX_MISC_CTRL (0x1800a) /* Lane RX Miscellaneous Control */ ++#define PCIE_PHY_DWC_RX_CTLE_CTRL (0x1800b) /* Lane RX CTLE Control */ ++#define PCIE_PHY_DWC_RX_PRECORR_CTRL (0x1800c) /* Lane RX Pre-Correlation Control */ ++#define PCIE_PHY_DWC_RX_PHS_ACCM_CTRL (0x1800d) /* Lane RX Phase Accumulator Control */ ++#define PCIE_PHY_DWC_RX_PHS_ACCM_FR_VAL (0x1800e) /* Lane RX Phase Accumulator Frequency Portion Control */ ++#define PCIE_PHY_DWC_RX_PRECORR_VAL (0x1800f) /* Lane RX Pre-Correlation Count */ ++#define PCIE_PHY_DWC_RX_DELTA_PM_0 (0x18010) /* Lane RX VMA Performance Metric Register #0 */ ++#define PCIE_PHY_DWC_RX_DELTA_PM_1 (0x18011) /* Lane RX VMA Performance Metric Register #1 */ ++#define PCIE_PHY_DWC_TX_CAPT_CTRL (0x18012) /* Lane TX Latch Control */ ++#define PCIE_PHY_DWC_TX_CFG_0 (0x18015) /* Lane TX Configuration Register #0 */ ++#define PCIE_PHY_DWC_TX_CFG_1 (0x18016) /* Lane TX Configuration Register #1 */ ++#define PCIE_PHY_DWC_TX_CFG_2 (0x18017) /* Lane TX Configuration Register #2 */ ++#define PCIE_PHY_DWC_TX_CFG_3 (0x18018) /* Lane TX Configuration Register #3 */ ++#define PCIE_PHY_DWC_TX_PREEMPH_0 (0x18019) /* Lane TX Pre-Emphasis */ ++#define PCIE_PHY_DWC_PMA_LOOPBACK_CTRL (0x1801a) /* Lane PMA Loopback Control */ ++#define PCIE_PHY_DWC_LANE_PWR_CTRL (0x1801b) /* Lane Power Control */ ++#define PCIE_PHY_DWC_TERM_CTRL (0x1801c) /* Lane Termination Control */ ++#define PCIE_PHY_DWC_RX_MISC_STATUS (0x18025) /* RX Miscellaneous Status */ ++#define PCIE_PHY_DWC_SDS_PIN_MON_0 (0x18026) /* SerDes Pin Monitor 0 */ ++#define PCIE_PHY_DWC_SDS_PIN_MON_1 (0x18027) /* SerDes Pin Monitor 1 */ ++#define PCIE_PHY_DWC_SDS_PIN_MON_2 (0x18028) /* SerDes Pin Monitor 2 */ ++#define PCIE_PHY_DWC_RX_PWR_MON_0 (0x18029) /* RX Power State Machine Monitor 0 */ ++#define PCIE_PHY_DWC_RX_PWR_MON_1 (0x1802a) /* RX Power State Machine Monitor 1 */ ++#define PCIE_PHY_DWC_RX_PWR_MON_2 (0x1802b) /* RX Power State Machine Monitor 2 */ ++#define PCIE_PHY_DWC_TX_PWR_MON_0 (0x1802c) /* TX Power State Machine Monitor 0 */ ++#define PCIE_PHY_DWC_TX_PWR_MON_1 (0x1802d) /* TX Power State Machine Monitor 1 */ ++#define PCIE_PHY_DWC_TX_PWR_MON_2 (0x1802e) /* TX Power State Machine Monitor 2 */ ++#define PCIE_PHY_DWC_RX_VMA_CTRL (0x18040) /* Lane RX VMA Control */ ++#define PCIE_PHY_DWC_RX_CDR_MISC_CTRL_0 (0x18041) /* Lane RX CDR Miscellaneous Control Register #0 */ ++#define PCIE_PHY_DWC_RX_CDR_MISC_CTRL_1 (0x18042) /* Lane RX CDR Miscellaneous Control Register #1 */ ++#define PCIE_PHY_DWC_RX_PWR_CTRL (0x18043) /* Lane RX Power Control */ ++#define PCIE_PHY_DWC_RX_OS_MVALBBD_0 (0x18045) /* Lane RX Offset Calibration Manual Control Register #0 */ ++#define PCIE_PHY_DWC_RX_OS_MVALBBD_1 (0x18046) /* Lane RX Offset Calibration Manual Control Register #1 */ ++#define PCIE_PHY_DWC_RX_OS_MVALBBD_2 (0x18047) /* Lane RX Offset Calibration Manual Control Register #2 */ ++#define PCIE_PHY_DWC_RX_AEQ_VALBBD_0 (0x18048) /* Lane RX Adaptive Equalizer Control Register #0 */ ++#define PCIE_PHY_DWC_RX_AEQ_VALBBD_1 (0x18049) /* Lane RX Adaptive Equalizer Control Register #1 */ ++#define PCIE_PHY_DWC_RX_AEQ_VALBBD_2 (0x1804a) /* Lane RX Adaptive Equalizer Control Register #2 */ ++#define PCIE_PHY_DWC_RX_MISC_OVRRD (0x1804b) /* Lane RX Miscellaneous Override Controls */ ++#define PCIE_PHY_DWC_RX_OVRRD_PHASE_ACCUM_ADJ (0x1804c) /* Lane RX Phase Accumulator Adjust Override */ ++#define PCIE_PHY_DWC_RX_AEQ_OUT_0 (0x18050) /* Lane RX Adaptive Equalizer Status Register #0 */ ++#define PCIE_PHY_DWC_RX_AEQ_OUT_1 (0x18051) /* Lane RX Adaptive Equalizer Status Register #1 */ ++#define PCIE_PHY_DWC_RX_AEQ_OUT_2 (0x18052) /* Lane RX Adaptive Equalizer Status Register #2 */ ++#define PCIE_PHY_DWC_RX_OS_OUT_0 (0x18053) /* Lane RX Offset Calibration Status Register #0 */ ++#define PCIE_PHY_DWC_RX_OS_OUT_1 (0x18054) /* Lane RX Offset Calibration Status Register #1 */ ++#define PCIE_PHY_DWC_RX_OS_OUT_2 (0x18055) /* Lane RX Offset Calibration Status Register #2 */ ++#define PCIE_PHY_DWC_RX_OS_OUT_3 (0x18056) /* Lane RX Offset Calibration Status Register #3 */ ++#define PCIE_PHY_DWC_RX_VMA_STATUS_0 (0x18057) /* Lane RX CDR Status Register #0 */ ++#define PCIE_PHY_DWC_RX_VMA_STATUS_1 (0x18058) /* Lane RX CDR Status Register #1 */ ++#define PCIE_PHY_DWC_RX_CDR_STATUS_0 (0x18059) /* Lane RX CDR Status Register #0 */ ++#define PCIE_PHY_DWC_RX_CDR_STATUS_1 (0x1805a) /* Lane RX CDR Status Register #1 */ ++#define PCIE_PHY_DWC_RX_CDR_STATUS_2 (0x1805b) /* Lane RX CDR Status Register #2 */ ++#define PCIE_PHY_DWC_PCS_MISC_CFG_0 (0x38000) /* Lane Miscellaneous Configuration Register #0 */ ++#define PCIE_PHY_DWC_PCS_MISC_CFG_1 (0x38001) /* Lane Raw PCS Miscellaneous Configuration Register #1 */ ++#define PCIE_PHY_DWC_PCS_LBERT_PAT_CFG (0x38003) /* LBERT Pattern Configuration */ ++#define PCIE_PHY_DWC_PCS_LBERT_CFG (0x38004) /* LBERT Configuration */ ++#define PCIE_PHY_DWC_PCS_LBERT_ECNT (0x38005) /* LBERT Error Counter */ ++#define PCIE_PHY_DWC_PCS_RESET_0 (0x38006) /* Lane Raw PCS Reset Register #0 */ ++#define PCIE_PHY_DWC_PCS_RESET_1 (0x38007) /* Lane Raw PCS Reset Register #1 */ ++#define PCIE_PHY_DWC_PCS_RESET_2 (0x38008) /* Lane Raw PCS Reset Register #2 */ ++#define PCIE_PHY_DWC_PCS_RESET_3 (0x38009) /* Lane Raw PCS Reset Register #3 */ ++#define PCIE_PHY_DWC_PCS_CTLIFC_CTRL_0 (0x3800c) /* Lane Raw PCS Control Interface Configuration Register #0 */ ++#define PCIE_PHY_DWC_PCS_CTLIFC_CTRL_1 (0x3800d) /* Lane Raw PCS Control Interface Configuration Register #1 */ ++#define PCIE_PHY_DWC_PCS_CTLIFC_CTRL_2 (0x3800e) /* Lane Raw PCS Control Interface Configuration Register #2 */ ++#define PCIE_PHY_DWC_PCS_MACIFC_MON_0 (0x38021) /* MAC to Raw PCS Interface Monitor Register #0 */ ++#define PCIE_PHY_DWC_PCS_MACIFC_MON_2 (0x38023) /* MAC to Raw PCS Interface Monitor Register #1 */ +diff --git a/include/linux/mfd/baikal/lcru-pcie.h b/include/linux/mfd/baikal/lcru-pcie.h +new file mode 100644 +index 000000000000..40562d00ab85 +--- /dev/null ++++ b/include/linux/mfd/baikal/lcru-pcie.h +@@ -0,0 +1,140 @@ ++/* ++ * Baikal SoC series Local Clock and Reset Unit (LCRU) register offsets ++ * and bit definitions. ++ * ++ * Copyright (C) 2019 Baikal Electronics JSC. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _LINUX_MFD_SYSCON_BAIKAL_LCRU_H_ ++#define _LINUX_MFD_SYSCON_BAIKAL_LCRU_H_ ++ ++#include ++ ++//#define BAIKAL_CMU_PCIE_STEP 0x30 ++ ++//#define BAIKAL_CMU_PCIE_MSTRCLK 0x20 ++//#define BAIKAL_CMU_PCIE_SLVCLK 0x30 ++//#define BAIKAL_CMU_PCIE_CFGCLK 0x40 ++ ++#define BAIKAL_LCRU_PCIE_RESET_BASE 0x50000 /* GPR0_RW */ ++#define BAIKAL_LCRU_PCIE_RESET(x) ((x * 0x20) + BAIKAL_LCRU_PCIE_RESET_BASE) ++#define BAIKAL_PCIE_ADB_PWRDWN (1 << 13) ++#define BAIKAL_PCIE_HOT_RESET (1 << 12) ++#define BAIKAL_PCIE_NONSTICKY_RST (1 << 11) ++#define BAIKAL_PCIE_STICKY_RST (1 << 10) ++#define BAIKAL_PCIE_PWR_RST (1 << 9) ++#define BAIKAL_PCIE_CORE_RST (1 << 8) ++#define BAIKAL_PCIE_PIPE1_RESET (1 << 5) /* x8 controller only */ ++#define BAIKAL_PCIE_PIPE0_RESET (1 << 4) /* x8 controller only */ ++#define BAIKAL_PCIE_PIPE_RESET (1 << 4) /* x4 controllers only */ ++#define BAIKAL_PCIE_PHY_RESET (1 << 0) ++ ++#define BAIKAL_LCRU_PCIE_STATUS_BASE 0x50004 /* GPR0_RO */ ++#define BAIKAL_LCRU_PCIE_STATUS(x) ((x * 0x20) + BAIKAL_LCRU_PCIE_STATUS_BASE) ++#define BAIKAL_PCIE_TURNOFF_ACK (1 << 31) ++#define BAIKAL_PCIE_ADB_PWRACK (1 << 30) ++#define BAIKAL_PCIE_WAKE_DET (1 << 24) ++#define BAIKAL_PCIE_AUX_PM_EN (1 << 22) ++#define BAIKAL_PCIE_PM_PME_STATUS (1 << 21) ++#define BAIKAL_PCIE_PM_PME_EN (1 << 20) ++#define BAIKAL_PCIE_PM_DSTATE_SHIFT 16 ++#define BAIKAL_PCIE_PM_DSTATE_MASK 0x7 ++#define BAIKAL_PCIE_PM_DSTATE_D0 0 ++#define BAIKAL_PCIE_PM_DSTATE_D1 1 ++#define BAIKAL_PCIE_PM_DSTATE_D2 2 ++#define BAIKAL_PCIE_PM_DSTATE_D3 3 ++#define BAIKAL_PCIE_PM_DSTATE_UNINIT 4 ++#define BAIKAL_PCIE_LTSSM_RCVRY_EQ (1 << 15) ++#define BAIKAL_PCIE_PIPE_CLK_REQ (1 << 14) ++#define BAIKAL_PCIE_SMLH_REQ_RST (1 << 13) ++#define BAIKAL_PCIE_LINK_REQ_RST (1 << 12) ++#define BAIKAL_PCIE_PM_LINKSTATE_L2 (1 << 10) ++#define BAIKAL_PCIE_PM_LINKSTATE_L1 (1 << 9) ++#define BAIKAL_PCIE_PM_LINKSTATE_L0S (1 << 8) ++#define BAIKAL_PCIE_RDLH_LINKUP (1 << 7) ++#define BAIKAL_PCIE_SMLH_LINKUP (1 << 6) ++#define BAIKAL_PCIE_LTSSM_STATE_SHIFT 0 ++#define BAIKAL_PCIE_LTSSM_STATE_MASK 0x3F ++#define BAIKAL_PCIE_LTSSM_STATE_DETECT_QUIET 0x00 ++#define BAIKAL_PCIE_LTSSM_STATE_DETECT_ACT 0x01 ++#define BAIKAL_PCIE_LTSSM_STATE_POLLING_ACTIVE 0x02 ++#define BAIKAL_PCIE_LTSSM_STATE_POLLING_COMPLIANCE 0x03 ++#define BAIKAL_PCIE_LTSSM_STATE_POLLING_CONFIG 0x04 ++#define BAIKAL_PCIE_LTSSM_STATE_PRE_DETECT_QUIET 0x05 ++#define BAIKAL_PCIE_LTSSM_STATE_DETECT_WAIT 0x06 ++#define BAIKAL_PCIE_LTSSM_STATE_CFG_LINK_WD_START 0x07 ++#define BAIKAL_PCIE_LTSSM_STATE_CFG_LINK_WD_ACCEPT 0x08 ++#define BAIKAL_PCIE_LTSSM_STATE_CFG_LANE_NUM_WAIT 0x09 ++#define BAIKAL_PCIE_LTSSM_STATE_CFG_LANE_NUM_ACCEPT 0x0A ++#define BAIKAL_PCIE_LTSSM_STATE_CFG_COMPLETE 0x0B ++#define BAIKAL_PCIE_LTSSM_STATE_CFG_IDLE 0x0C ++#define BAIKAL_PCIE_LTSSM_STATE_RCVRY_LOCK 0x0D ++#define BAIKAL_PCIE_LTSSM_STATE_RCVRY_SPEED 0x0E ++#define BAIKAL_PCIE_LTSSM_STATE_RCVRY_RCVR_CFG 0x0F ++#define BAIKAL_PCIE_LTSSM_STATE_RCVRY_IDLE 0x10 ++#define BAIKAL_PCIE_LTSSM_STATE_RCVRY_EQ0 0x20 ++#define BAIKAL_PCIE_LTSSM_STATE_RCVRY_EQ1 0x21 ++#define BAIKAL_PCIE_LTSSM_STATE_RCVRY_EQ2 0x22 ++#define BAIKAL_PCIE_LTSSM_STATE_RCVRY_EQ3 0x23 ++#define BAIKAL_PCIE_LTSSM_STATE_L0 0x11 ++#define BAIKAL_PCIE_LTSSM_STATE_L0S 0x12 ++#define BAIKAL_PCIE_LTSSM_STATE_L123_SEND_IDLE 0x13 ++#define BAIKAL_PCIE_LTSSM_STATE_L1_IDLE 0x14 ++#define BAIKAL_PCIE_LTSSM_STATE_L2_IDLE 0x15 ++#define BAIKAL_PCIE_LTSSM_STATE_L2_WAKE 0x16 ++#define BAIKAL_PCIE_LTSSM_STATE_DISABLED_ENTRY 0x17 ++#define BAIKAL_PCIE_LTSSM_STATE_DISABLED_IDLE 0x18 ++#define BAIKAL_PCIE_LTSSM_STATE_DISABLED 0x19 ++#define BAIKAL_PCIE_LTSSM_STATE_LOOPBACK_ENTRY 0x1A ++#define BAIKAL_PCIE_LTSSM_STATE_LOOPBACK_ACTIVE 0x1B ++#define BAIKAL_PCIE_LTSSM_STATE_LOOPBACK_EXIT 0x1C ++#define BAIKAL_PCIE_LTSSM_STATE_LOOPBACK_EXIT_TIMEOUT 0x1D ++#define BAIKAL_PCIE_LTSSM_STATE_HOT_RESET_ENTRY 0x1E ++#define BAIKAL_PCIE_LTSSM_STATE_HOT_RESET 0x1F ++ ++#define BAIKAL_LCRU_PCIE_GEN_CTL_BASE 0x50008 /* GPR1_RW*/ ++#define BAIKAL_LCRU_PCIE_GEN_CTL(x) ((x * 0x20) + BAIKAL_LCRU_PCIE_GEN_CTL_BASE) ++#define BAIKAL_PCIE_AUX_PWR_DET (1 << 24) ++#define BAIKAL_PCIE_TXLANE_FLIP_EN (1 << 17) ++#define BAIKAL_PCIE_RXLANE_FLIP_EN (1 << 16) ++#define BAIKAL_PCIE_PHY_MGMT_ENABLE (1 << 3) ++#define BAIKAL_PCIE_DBI2_MODE (1 << 2) ++#define BAIKAL_PCIE_LTSSM_ENABLE (1 << 1) ++ ++#define BAIKAL_LCRU_PCIE_POWER_CTL_BASE 0x50010 /* GPR2_RW */ ++#define BAIKAL_LCRU_PCIE_POWER_CTL(x) ((x * 0x20) + BAIKAL_LCRU_POWER_CTL_BASE) ++#define BAIKAL_PCIE_PHY_CLK_REQ (1 << 27) ++#define BAIKAL_PCIE_APP_CLK_REQ (1 << 26) ++#define BAIKAL_PCIE_PERSTN (1 << 25) ++#define BAIKAL_PCIE_TURNOFF_REQ (1 << 24) ++#define BAIKAL_PCIE_REQ_EXIT_L1 (1 << 17) ++#define BAIKAL_PCIE_L1_PENDING (1 << 16) ++#define BAIKAL_PCIE_MAC_CLK_REQ (1 << 5) ++#define BAIKAL_PCIE_PCS_CLK_REQ (1 << 4) ++ ++#define BAIKAL_LCRU_PCIE_MSI_TRANS_CTL0 0x500E8 ++#define BAIKAL_PCIE_MSI_AWUSER_SHIFT 0 ++#define BAIKAL_PCIE_MSI_AWUSER_MASK 0xF ++ ++#define BAIKAL_LCRU_PCIE_MSI_TRANS_CTL2 0x500F8 ++#define BAIKAL_PCIE_MSI_TRANS_EN(x) (1 << (9 + (x))) ++#define BAIKAL_PCIE_MSI_RCNUM(x) ((x) << (2 * (x))) ++#define BAIKAL_PCIE_MSI_RCNUM_MASK(x) (0x3 << (2 * (x))) ++ ++inline u32 baikal_pcie_lcru_readl(struct regmap *lcru, u32 offset) ++{ ++ u32 val; ++ regmap_read(lcru, offset, &val); ++ return val; ++} ++ ++inline void baikal_pcie_lcru_writel(struct regmap *lcru, u32 offset, u32 val) ++{ ++ regmap_write(lcru, offset, val); ++} ++ ++#endif /* _LINUX_MFD_SYSCON_BAIKAL_LCRU_H_ */ +-- +2.31.1 + diff --git a/0617-Baikal-M-PCIe-driver-from-SDK-M-4.4.patch b/0617-Baikal-M-PCIe-driver-from-SDK-M-4.4.patch new file mode 100644 index 0000000..b3a5906 --- /dev/null +++ b/0617-Baikal-M-PCIe-driver-from-SDK-M-4.4.patch @@ -0,0 +1,861 @@ +From 1865253e6f0bd9dd35495cf5c5cc0db1c5df071b Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Thu, 14 Jan 2021 12:25:44 +0400 +Subject: [PATCH 617/625] Baikal-M: PCIe driver from SDK-M 4.4 + +Appears to successfully probe the hardware, lspci -vv output +looks good. No other testing has been done yet. +--- + drivers/pci/controller/dwc/Makefile | 2 +- + drivers/pci/controller/dwc/pcie-baikal-v44.c | 826 +++++++++++++++++++ + 2 files changed, 827 insertions(+), 1 deletion(-) + create mode 100644 drivers/pci/controller/dwc/pcie-baikal-v44.c + +diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile +index 85e6ad1954e5..dcd23d7d5430 100644 +--- a/drivers/pci/controller/dwc/Makefile ++++ b/drivers/pci/controller/dwc/Makefile +@@ -20,7 +20,7 @@ obj-$(CONFIG_PCI_MESON) += pci-meson.o + obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o + obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o + obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o +-obj-$(CONFIG_PCI_BAIKAL) += pcie-baikal.o ++obj-$(CONFIG_PCI_BAIKAL) += pcie-baikal.o pcie-baikal-v44.o + + # The following drivers are for devices that use the generic ACPI + # pci_root.c driver but don't support standard ECAM config access. +diff --git a/drivers/pci/controller/dwc/pcie-baikal-v44.c b/drivers/pci/controller/dwc/pcie-baikal-v44.c +new file mode 100644 +index 000000000000..5e5f0a9e59e2 +--- /dev/null ++++ b/drivers/pci/controller/dwc/pcie-baikal-v44.c +@@ -0,0 +1,826 @@ ++/* ++ * PCIe root complex driver for Baikal SoCs ++ * ++ * Copyright (C) 2019-2020 Baikal Electronics, JSC ++ * Authors: Pavel Parkhomenko ++ * Mikhail Ivanov ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pcie-designware.h" ++ ++#ifdef CONFIG_PCI_DEBUG ++#define DEBUG ++#endif ++ ++struct baikal_pcie { ++ struct dw_pcie pp; ++ unsigned bus_nr; ++ struct regmap *lcru; ++ struct gpio_desc *reset_gpio; ++ unsigned reset_active_low; ++ char reset_name[32]; ++ unsigned retrained; ++ unsigned num_lanes; ++}; ++ ++#define to_baikal_pcie(x) container_of((x), struct baikal_pcie, pp) ++ ++#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_REG 0x78 ++#define PCIE_CAP_CORR_ERR_REPORT_EN BIT(0) ++#define PCIE_CAP_NON_FATAL_ERR_REPORT_EN BIT(1) ++#define PCIE_CAP_FATAL_ERR_REPORT_EN BIT(2) ++#define PCIE_CAP_UNSUPPORT_REQ_REP_EN BIT(3) ++ ++#define PCIE_LINK_CAPABILITIES_REG 0x7c ++#define PCIE_CAP_MAX_LINK_WIDTH_MASK 0x3f0 ++#define PCIE_CAP_MAX_LINK_WIDTH_SHIFT 4 ++ ++#define PCIE_LINK_CONTROL_LINK_STATUS_REG 0x80 ++#define PCIE_CAP_LINK_SPEED_MASK 0xf0000 ++#define PCIE_CAP_LINK_SPEED_SHIFT 16 ++#define PCIE_CAP_NEGO_LINK_WIDTH_MASK 0x3f00000 ++#define PCIE_CAP_NEGO_LINK_WIDTH_SHIFT 20 ++#define PCIE_CAP_LINK_TRAINING BIT(27) ++ ++#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG 0x8c ++#define PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN BIT(0) ++#define PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN BIT(1) ++#define PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN BIT(2) ++#define PCIE_CAP_PME_INT_EN BIT(3) ++ ++#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG 0xa0 ++#define PCIE_CAP_TARGET_LINK_SPEED_MASK 0xf ++ ++#define PCIE_UNCORR_ERR_STATUS_REG 0x104 ++#define PCIE_CORR_ERR_STATUS_REG 0x110 ++ ++#define PCIE_ROOT_ERR_CMD_REG 0x12c ++#define PCIE_CORR_ERR_REPORTING_EN BIT(0) ++#define PCIE_NON_FATAL_ERR_REPORTING_EN BIT(1) ++#define PCIE_FATAL_ERR_REPORTING_EN BIT(2) ++ ++#define PCIE_ROOT_ERR_STATUS_REG 0x130 ++ ++#define PCIE_GEN2_CTRL_REG 0x80c ++#define PCIE_DIRECT_SPEED_CHANGE BIT(17) ++ ++#define PCIE_MSI_CTRL_ADDR_LO_REG 0x820 ++#define PCIE_MSI_CTRL_ADDR_HI_REG 0x824 ++ ++#define PCIE_MISC_CONTROL_1_REG 0x8bc ++#define PCIE_DBI_RO_RW_EN BIT(0) ++ ++#define PCIE_IATU_VIEWPORT_REG 0x900 ++#define PCIE_IATU_REGION_INBOUND BIT(31) ++#define PCIE_IATU_REGION_OUTBOUND 0 ++#define PCIE_IATU_REGION_CTRL_2_REG 0x908 ++ ++static const struct of_device_id of_baikal_pcie_match[] = { ++ { .compatible = "baikal,pcie-m", }, ++ {}, ++}; ++ ++static unsigned baikal_pcie_link_is_training(struct dw_pcie *pp) ++{ ++ unsigned long reg; ++ reg = dw_pcie_readl_dbi(pp, PCIE_LINK_CONTROL_LINK_STATUS_REG); ++ return reg & PCIE_CAP_LINK_TRAINING; ++} ++ ++static bool baikal_wait_pcie_link_training_done(struct dw_pcie *pp) ++{ ++ unsigned long start_jiffies = jiffies; ++ while (baikal_pcie_link_is_training(pp)) { ++ if (time_after(jiffies, start_jiffies + HZ)) { ++ pr_err("%s: link retrained for too long, timeout occured\n", __func__); ++ return false; ++ } ++ udelay(100); ++ } ++ return true; ++} ++ ++static void baikal_print_link_status(struct dw_pcie *pp) ++{ ++ unsigned long reg; ++ unsigned speed, width; ++ ++ reg = dw_pcie_readl_dbi(pp, PCIE_LINK_CONTROL_LINK_STATUS_REG); ++ speed = (reg & PCIE_CAP_LINK_SPEED_MASK) >> PCIE_CAP_LINK_SPEED_SHIFT; ++ width = (reg & PCIE_CAP_NEGO_LINK_WIDTH_MASK) >> ++ PCIE_CAP_NEGO_LINK_WIDTH_SHIFT; ++ ++ dev_info(pp->dev, "link status is Gen%u, x%u\n", speed, width); ++} ++ ++static void baikal_pcie_link_retrain(struct dw_pcie *pp, int target_speed) ++{ ++ unsigned long reg; ++ unsigned long start_jiffies; ++ ++ dev_info(pp->dev, "retrain link to Gen%u\n", target_speed); ++ ++ /* In case link is already training wait for training to complete */ ++ baikal_wait_pcie_link_training_done(pp); ++ ++ /* Set desired speed */ ++ reg = dw_pcie_readl_dbi(pp, PCIE_LINK_CONTROL2_LINK_STATUS2_REG); ++ reg &= ~PCIE_CAP_TARGET_LINK_SPEED_MASK; ++ reg |= target_speed; ++ dw_pcie_writel_dbi(pp, PCIE_LINK_CONTROL2_LINK_STATUS2_REG, reg); ++ ++ /* Set DIRECT_SPEED_CHANGE bit */ ++ reg = dw_pcie_readl_dbi(pp, PCIE_GEN2_CTRL_REG); ++ reg &= ~PCIE_DIRECT_SPEED_CHANGE; ++ dw_pcie_writel_dbi(pp, PCIE_GEN2_CTRL_REG, reg); ++ reg |= PCIE_DIRECT_SPEED_CHANGE; ++ dw_pcie_writel_dbi(pp, PCIE_GEN2_CTRL_REG, reg); ++ ++ /* Wait for link training begin */ ++ start_jiffies = jiffies; ++ while (baikal_pcie_link_is_training(pp) == 0) { ++ if (time_after(jiffies, start_jiffies + HZ)) { ++ pr_err("%s: link retrained for too long, timeout occured\n", __func__); ++ break; ++ } ++ udelay(100); ++ } ++ ++ /* Wait for link training end */ ++ baikal_wait_pcie_link_training_done(pp); ++ ++ if (dw_pcie_wait_for_link(pp) == 0) { ++ baikal_print_link_status(pp); ++ } ++} ++ ++static void baikal_pcie_link_speed_fixup(struct pci_dev *pdev) ++{ ++ struct pcie_port *portp = pdev->bus->sysdata; ++ struct dw_pcie *pp = to_dw_pcie_from_pp(portp); ++ struct baikal_pcie *pcie = to_baikal_pcie(pp); ++ unsigned dev_lnkcap_speed; ++ unsigned dev_lnkcap_width; ++ unsigned rc_lnkcap_speed; ++ unsigned rc_lnksta_speed; ++ unsigned rc_target_speed; ++ u32 reg; ++ ++ /* Skip Root Bridge */ ++ if (!pdev->bus->self) { ++ return; ++ } ++ ++ /* Skip any devices not directly connected to the RC */ ++ if (pdev->bus->self->bus->number != portp->bridge->bus->number) { ++ return; ++ } ++ ++ /* Skip if the bus has already been retrained */ ++ if (pcie->retrained) { ++ return; ++ } ++ ++ reg = dw_pcie_readl_dbi(pp, PCIE_LINK_CAPABILITIES_REG); ++ rc_lnkcap_speed = reg & PCI_EXP_LNKCAP_SLS; ++ ++ reg = dw_pcie_readl_dbi(pp, PCIE_LINK_CONTROL_LINK_STATUS_REG); ++ rc_lnksta_speed = (reg & PCIE_CAP_LINK_SPEED_MASK) >> ++ PCIE_CAP_LINK_SPEED_SHIFT; ++ ++ rc_target_speed = rc_lnksta_speed < 3? rc_lnksta_speed + 1 : 3; ++ ++ pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®); ++ dev_lnkcap_speed = (reg & PCI_EXP_LNKCAP_SLS); ++ dev_lnkcap_width = (reg & PCI_EXP_LNKCAP_MLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; ++ ++ baikal_print_link_status(pp); ++ dev_info(&pdev->dev, "device link capability is Gen%u, x%u\n", ++ dev_lnkcap_speed, dev_lnkcap_width); ++ ++ while (rc_target_speed > rc_lnksta_speed && ++ rc_target_speed <= rc_lnkcap_speed && ++ rc_target_speed <= dev_lnkcap_speed) { ++ /* Try to change link speed */ ++ baikal_pcie_link_retrain(pp, rc_target_speed); ++ reg = dw_pcie_readl_dbi(pp, PCIE_LINK_CONTROL_LINK_STATUS_REG); ++ rc_lnksta_speed = (reg & PCIE_CAP_LINK_SPEED_MASK) >> ++ PCIE_CAP_LINK_SPEED_SHIFT; ++ ++ /* Check if the targeted speed has not been reached */ ++ if (rc_lnksta_speed < rc_target_speed) { ++ /* Check if the retraining has led to speed regression */ ++ if (rc_lnksta_speed < (rc_target_speed - 1)) { ++ /* Fall back to the previous speed */ ++ --rc_target_speed; ++ baikal_pcie_link_retrain(pp, rc_target_speed); ++ } ++ ++ break; ++ } ++ ++ ++rc_target_speed; ++ } ++ ++ pcie->retrained = 1; ++} ++ ++static void baikal_pcie_retrain_links(const struct pci_bus *bus) ++{ ++ struct pci_dev *dev; ++ struct pci_bus *child; ++ ++ list_for_each_entry(dev, &bus->devices, bus_list) ++ baikal_pcie_link_speed_fixup(dev); ++ ++ list_for_each_entry(dev, &bus->devices, bus_list) { ++ child = dev->subordinate; ++ if (child) ++ baikal_pcie_retrain_links(child); ++ } ++} ++ ++static int baikal_pcie_link_up(struct dw_pcie *pp) ++{ ++ struct baikal_pcie *pcie = to_baikal_pcie(pp); ++ unsigned long reg; ++ ++ reg = baikal_pcie_lcru_readl(pcie->lcru, ++ BAIKAL_LCRU_PCIE_GEN_CTL(pcie->bus_nr)); ++ ++ if ((reg & BAIKAL_PCIE_LTSSM_ENABLE) == 0) { ++ return 0; ++ } ++ ++ reg = baikal_pcie_lcru_readl(pcie->lcru, ++ BAIKAL_LCRU_PCIE_STATUS(pcie->bus_nr)); ++ ++ return (reg & BAIKAL_PCIE_SMLH_LINKUP) && ++ (reg & BAIKAL_PCIE_RDLH_LINKUP); ++} ++ ++static int baikal_pcie_get_msi(struct baikal_pcie *pcie, ++ struct device_node *msi_node, ++ u64 *msi_addr) ++{ ++ struct device *dev = pcie->pp.dev; ++ int ret; ++ struct resource res; ++ ++ /* ++ * Check if 'msi-parent' points to ARM GICv3 ITS, which is the only ++ * supported MSI controller. ++ */ ++ if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) { ++ dev_err(dev, "unable to find compatible MSI controller\n"); ++ return -ENODEV; ++ } ++ ++ /* Derive GITS_TRANSLATER address from GICv3 */ ++ ret = of_address_to_resource(msi_node, 0, &res); ++ if (ret < 0) { ++ dev_err(dev, "unable to obtain MSI controller resources\n"); ++ return ret; ++ } ++ ++ *msi_addr = res.start + GITS_TRANSLATER; ++ return 0; ++} ++ ++static int baikal_pcie_msi_steer(struct baikal_pcie *pcie, ++ struct device_node *msi_node) ++{ ++ struct dw_pcie *pp = &pcie->pp; ++ struct device *dev = pp->dev; ++ int ret; ++ u64 msi_addr; ++ ++ ret = baikal_pcie_get_msi(pcie, msi_node, &msi_addr); ++ if (ret < 0) { ++ dev_err(dev, "MSI steering failed\n"); ++ return ret; ++ } ++ ++ /* Program the msi_data */ ++ dw_pcie_write(pp->dbi_base + PCIE_MSI_CTRL_ADDR_LO_REG, 4, ++ lower_32_bits(msi_addr)); ++ dw_pcie_write(pp->dbi_base + PCIE_MSI_CTRL_ADDR_HI_REG, 4, ++ upper_32_bits(msi_addr)); ++ return 0; ++} ++ ++static int baikal_pcie_msi_enable(struct baikal_pcie *pcie) ++{ ++ struct device *dev = pcie->pp.dev; ++ struct device_node *msi_node; ++ int ret; ++ ++ /* ++ * The "msi-parent" phandle needs to exist ++ * for us to obtain the MSI node. ++ */ ++ msi_node = of_parse_phandle(dev->of_node, "msi-parent", 0); ++ if (!msi_node) { ++ dev_err(dev, "failed to read msi-parent node from FDT\n"); ++ return -ENODEV; ++ } ++ ++ ret = baikal_pcie_msi_steer(pcie, msi_node); ++ if (ret) { ++ goto out_put_node; ++ } ++ ++out_put_node: ++ of_node_put(msi_node); ++ return ret; ++} ++ ++static irqreturn_t baikal_pcie_err_irq_handler(int irq, void *priv) ++{ ++ struct baikal_pcie *pcie = priv; ++ struct device *dev = pcie->pp.dev; ++ unsigned long corr_err_status; ++ unsigned long dev_ctrl_dev_status; ++ unsigned long root_err_status; ++ unsigned long uncorr_err_status; ++ ++ uncorr_err_status = dw_pcie_readl_dbi(&pcie->pp, ++ PCIE_UNCORR_ERR_STATUS_REG); ++ corr_err_status = dw_pcie_readl_dbi(&pcie->pp, ++ PCIE_CORR_ERR_STATUS_REG); ++ root_err_status = dw_pcie_readl_dbi(&pcie->pp, ++ PCIE_ROOT_ERR_STATUS_REG); ++ dev_ctrl_dev_status = dw_pcie_readl_dbi(&pcie->pp, ++ PCIE_DEVICE_CONTROL_DEVICE_STATUS_REG); ++ dev_err(dev, ++ "dev_err:0x%lx root_err:0x%lx uncorr_err:0x%lx corr_err:0x%lx\n", ++ (dev_ctrl_dev_status & 0xf0000) >> 16, ++ root_err_status, uncorr_err_status, corr_err_status); ++ ++ dw_pcie_writel_dbi(&pcie->pp, ++ PCIE_UNCORR_ERR_STATUS_REG, uncorr_err_status); ++ dw_pcie_writel_dbi(&pcie->pp, ++ PCIE_CORR_ERR_STATUS_REG, corr_err_status); ++ dw_pcie_writel_dbi(&pcie->pp, ++ PCIE_ROOT_ERR_STATUS_REG, root_err_status); ++ dw_pcie_writel_dbi(&pcie->pp, ++ PCIE_DEVICE_CONTROL_DEVICE_STATUS_REG, dev_ctrl_dev_status); ++ ++ return IRQ_HANDLED; ++} ++ ++static int baikal_pcie_host_init(struct pcie_port *port) ++{ ++ struct dw_pcie* pp = to_dw_pcie_from_pp(port); ++ struct device *dev = pp->dev; ++ struct baikal_pcie *pcie = to_baikal_pcie(pp); ++ int err; ++ int linkup; ++ unsigned idx; ++ unsigned long reg; ++ ++ /* Disable access to PHY registers and DBI2 mode */ ++ reg = baikal_pcie_lcru_readl(pcie->lcru, ++ BAIKAL_LCRU_PCIE_GEN_CTL(pcie->bus_nr)); ++ ++ reg &= ~(BAIKAL_PCIE_PHY_MGMT_ENABLE | ++ BAIKAL_PCIE_DBI2_MODE); ++ ++ baikal_pcie_lcru_writel(pcie->lcru, ++ BAIKAL_LCRU_PCIE_GEN_CTL(pcie->bus_nr), reg); ++ ++ pcie->retrained = 0; ++ linkup = baikal_pcie_link_up(pp); ++ ++ /* If link is not established yet, reset the RC */ ++ if (!linkup) { ++ /* Disable link training */ ++ reg = baikal_pcie_lcru_readl(pcie->lcru, ++ BAIKAL_LCRU_PCIE_GEN_CTL(pcie->bus_nr)); ++ ++ reg &= ~BAIKAL_PCIE_LTSSM_ENABLE; ++ baikal_pcie_lcru_writel(pcie->lcru, ++ BAIKAL_LCRU_PCIE_GEN_CTL(pcie->bus_nr), reg); ++ ++ /* Assert PERST pin */ ++ if (pcie->reset_gpio != NULL) { ++ unsigned long gpio_flags; ++ ++ if (pcie->reset_active_low) { ++ gpio_flags = GPIOF_ACTIVE_LOW | ++ GPIOF_OUT_INIT_LOW; ++ } else { ++ gpio_flags = GPIOF_OUT_INIT_HIGH; ++ } ++ ++ err = devm_gpio_request_one(dev, ++ desc_to_gpio(pcie->reset_gpio), ++ gpio_flags, pcie->reset_name); ++ ++ if (err) { ++ dev_err(dev, "request GPIO failed (%d)\n", err); ++ return -ENODEV; ++ } ++ } ++ ++ /* Reset the RC */ ++ reg = baikal_pcie_lcru_readl(pcie->lcru, ++ BAIKAL_LCRU_PCIE_RESET(pcie->bus_nr)); ++ ++ reg |= BAIKAL_PCIE_NONSTICKY_RST | ++ BAIKAL_PCIE_STICKY_RST | ++ BAIKAL_PCIE_PWR_RST | ++ BAIKAL_PCIE_CORE_RST | ++ BAIKAL_PCIE_PHY_RESET; ++ ++ /* If the RC is PCIe x8, reset PIPE0 and PIPE1 */ ++ if (pcie->bus_nr == 2) { ++ reg |= BAIKAL_PCIE_PIPE0_RESET | ++ BAIKAL_PCIE_PIPE1_RESET; ++ } else { ++ reg |= BAIKAL_PCIE_PIPE_RESET; ++ } ++ ++ baikal_pcie_lcru_writel(pcie->lcru, ++ BAIKAL_LCRU_PCIE_RESET(pcie->bus_nr), reg); ++ ++ usleep_range(20000, 30000); ++ ++ if (pcie->reset_gpio != NULL) { ++ /* Deassert PERST pin */ ++ gpiod_set_value_cansleep(pcie->reset_gpio, 0); ++ } ++ ++ /* Deassert PHY reset */ ++ reg = baikal_pcie_lcru_readl(pcie->lcru, ++ BAIKAL_LCRU_PCIE_RESET(pcie->bus_nr)); ++ ++ reg &= ~BAIKAL_PCIE_PHY_RESET; ++ baikal_pcie_lcru_writel(pcie->lcru, ++ BAIKAL_LCRU_PCIE_RESET(pcie->bus_nr), reg); ++ ++ /* Deassert all software controlled resets */ ++ reg = baikal_pcie_lcru_readl(pcie->lcru, ++ BAIKAL_LCRU_PCIE_RESET(pcie->bus_nr)); ++ ++ reg &= ~(BAIKAL_PCIE_ADB_PWRDWN | ++ BAIKAL_PCIE_HOT_RESET | ++ BAIKAL_PCIE_NONSTICKY_RST | ++ BAIKAL_PCIE_STICKY_RST | ++ BAIKAL_PCIE_PWR_RST | ++ BAIKAL_PCIE_CORE_RST | ++ BAIKAL_PCIE_PHY_RESET); ++ ++ if (pcie->bus_nr == 2) { ++ reg &= ~(BAIKAL_PCIE_PIPE0_RESET | ++ BAIKAL_PCIE_PIPE1_RESET); ++ } else { ++ reg &= ~BAIKAL_PCIE_PIPE_RESET; ++ } ++ ++ baikal_pcie_lcru_writel(pcie->lcru, ++ BAIKAL_LCRU_PCIE_RESET(pcie->bus_nr), reg); ++ } ++ ++ /* Deinitialise all iATU regions */ ++ for (idx = 0; idx < pp->num_viewport; ++idx) { ++ dw_pcie_writel_dbi(pp, PCIE_IATU_VIEWPORT_REG, ++ PCIE_IATU_REGION_OUTBOUND | idx); ++ dw_pcie_writel_dbi(pp, PCIE_IATU_REGION_CTRL_2_REG, 0); ++ } ++ ++ /* ++ * Enable writing to config regs. This is required as the DW driver ++ * changes the class code. That register needs DBI write enable. ++ */ ++ reg = dw_pcie_readl_dbi(pp, PCIE_MISC_CONTROL_1_REG); ++ reg |= PCIE_DBI_RO_RW_EN; ++ dw_pcie_writel_dbi(pp, PCIE_MISC_CONTROL_1_REG, reg); ++ ++ dw_pcie_setup_rc(port); ++ ++ /* Set prog-if = 1 */ ++ reg = dw_pcie_readl_dbi(pp, PCI_CLASS_REVISION); ++ reg = (1 << 8) | (reg & 0xffff00ff); ++ dw_pcie_writel_dbi(pp, PCI_CLASS_REVISION, reg); ++ ++ /* Set max link width in accordance with 'num-lanes' value */ ++ reg = dw_pcie_readl_dbi(pp, PCIE_LINK_CAPABILITIES_REG); ++ reg &= ~PCIE_CAP_MAX_LINK_WIDTH_MASK; ++ reg |= (pcie->num_lanes) << PCIE_CAP_MAX_LINK_WIDTH_SHIFT; ++ dw_pcie_writel_dbi(pp, PCIE_LINK_CAPABILITIES_REG, reg); ++ ++ /* Disable writing to config regs */ ++ reg = dw_pcie_readl_dbi(pp, PCIE_MISC_CONTROL_1_REG); ++ reg &= ~PCIE_DBI_RO_RW_EN; ++ dw_pcie_writel_dbi(pp, PCIE_MISC_CONTROL_1_REG, reg); ++ ++ if (IS_ENABLED(CONFIG_PCI_MSI)) { ++ err = baikal_pcie_msi_enable(pcie); ++ if (err) { ++ dev_err(pp->dev, "failed to initialize MSI\n"); ++ return -EIO; ++ } ++ } ++ ++ /* Enable error reporting */ ++ reg = dw_pcie_readl_dbi(pp, PCIE_ROOT_ERR_CMD_REG); ++ reg |= PCIE_CORR_ERR_REPORTING_EN | ++ PCIE_NON_FATAL_ERR_REPORTING_EN | ++ PCIE_FATAL_ERR_REPORTING_EN; ++ dw_pcie_writel_dbi(pp, PCIE_ROOT_ERR_CMD_REG, reg); ++ ++ reg = dw_pcie_readl_dbi(pp, PCIE_DEVICE_CONTROL_DEVICE_STATUS_REG); ++ reg |= PCIE_CAP_CORR_ERR_REPORT_EN | ++ PCIE_CAP_NON_FATAL_ERR_REPORT_EN | ++ PCIE_CAP_FATAL_ERR_REPORT_EN | ++ PCIE_CAP_UNSUPPORT_REQ_REP_EN; ++ dw_pcie_writel_dbi(pp, PCIE_DEVICE_CONTROL_DEVICE_STATUS_REG, reg); ++ ++ reg = dw_pcie_readl_dbi(pp, PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG); ++ reg |= PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN | ++ PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN | ++ PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN | ++ PCIE_CAP_PME_INT_EN; ++ dw_pcie_writel_dbi(pp, PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG, reg); ++ ++ if (linkup) { ++ dev_info(dev, "link is already up\n"); ++ return 0; ++ } ++ ++ /* Use Gen1 mode for link establishing */ ++ reg = dw_pcie_readl_dbi(pp, PCIE_LINK_CONTROL2_LINK_STATUS2_REG); ++ reg &= ~PCIE_CAP_TARGET_LINK_SPEED_MASK; ++ reg |= 1; ++ dw_pcie_writel_dbi(pp, PCIE_LINK_CONTROL2_LINK_STATUS2_REG, reg); ++ ++ /* ++ * Clear DIRECT_SPEED_CHANGE bit. It has been set by dw_pcie_setup_rc. ++ * This bit causes link retraining. However, link retraining should be ++ * performed later by calling a speed fixup function. ++ */ ++ reg = dw_pcie_readl_dbi(pp, PCIE_GEN2_CTRL_REG); ++ reg &= ~PCIE_DIRECT_SPEED_CHANGE; ++ dw_pcie_writel_dbi(pp, PCIE_GEN2_CTRL_REG, reg); ++ ++ /* Establish link */ ++ reg = baikal_pcie_lcru_readl(pcie->lcru, ++ BAIKAL_LCRU_PCIE_GEN_CTL(pcie->bus_nr)); ++ ++ reg |= BAIKAL_PCIE_LTSSM_ENABLE; ++ baikal_pcie_lcru_writel(pcie->lcru, ++ BAIKAL_LCRU_PCIE_GEN_CTL(pcie->bus_nr), reg); ++ ++ dw_pcie_wait_for_link(pp); ++ /* XXX: ++ * - return OK even if the link is down ++ * - on error dw_pcie_wait_for_link prints a warning on its own, ++ * there's no need to print more messages here ++ */ ++ return 0; ++} ++ ++static int baikal_pcie_msi_host_init(struct pcie_port *pp) ++{ ++ struct dw_pcie* pcie = to_dw_pcie_from_pp(pp); ++ struct device *dev = pcie->dev; ++ struct device_node *np = dev->of_node; ++ struct device_node *msi_node; ++ ++ /* ++ * The MSI domain is set by the generic of_msi_configure(). This ++ * .msi_host_init() function keeps us from doing the default MSI domain ++ * setup in dw_pcie_host_init() and also enforces the requirement that ++ * "msi-parent" exists. ++ */ ++ msi_node = of_parse_phandle(np, "msi-parent", 0); ++ if (!msi_node) { ++ dev_err(dev, "failed to find msi-parent\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static const struct dw_pcie_host_ops baikal_pcie_host_ops = { ++ .host_init = baikal_pcie_host_init, ++ .msi_host_init = baikal_pcie_msi_host_init, ++}; ++ ++static const struct dw_pcie_ops baikal_pcie_ops = { ++ .link_up = baikal_pcie_link_up, ++}; ++ ++static int baikal_add_pcie_port(struct baikal_pcie *pcie, ++ struct platform_device *pdev) ++{ ++ struct dw_pcie *dw_pci = &pcie->pp; ++ struct pcie_port *pp = &dw_pci->pp; ++ struct resource *res; ++ int irq; ++ int ret; ++ ++ dw_pci->dev = &pdev->dev; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); ++ if (res) { ++ devm_request_resource(dw_pci->dev, &iomem_resource, res); ++ dw_pci->dbi_base = devm_ioremap_resource(dw_pci->dev, res); ++ if (IS_ERR(dw_pci->dbi_base)) { ++ dev_err(dw_pci->dev, "error with ioremap\n"); ++ return -ENOMEM; ++ } ++ } else { ++ dev_err(dw_pci->dev, "missing *dbi* reg space\n"); ++ return -EINVAL; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ dev_err(dw_pci->dev, "missing IRQ resource: %d\n", irq); ++ return irq; ++ } ++ ++ ret = devm_request_irq(dw_pci->dev, irq, baikal_pcie_err_irq_handler, ++ IRQF_SHARED | IRQF_NO_THREAD, ++ "baikal-pcie-error-irq", pcie); ++ if (ret) { ++ dev_err(dw_pci->dev, "failed to request IRQ\n"); ++ return ret; ++ } ++ ++ pp->ops = &baikal_pcie_host_ops; ++ ret = dw_pcie_host_init(pp); ++ if (ret) { ++ dev_err(dw_pci->dev, "failed to initialize host\n"); ++ return ret; ++ } ++ baikal_pcie_retrain_links(pp->bridge->bus); ++ ++ return 0; ++} ++ ++static bool has_incompat_firmware(void) { ++ bool gotcha = false; ++ struct device_node *np = NULL; ++ np = of_find_node_by_path("/soc"); ++ if (np) { ++ of_node_put(np); ++ } else { ++ gotcha = true; ++ } ++ return gotcha; ++} ++ ++static int baikal_pcie_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct baikal_pcie *pcie; ++ int err; ++ u32 index[2]; ++ enum of_gpio_flags gpio_flags; ++ int reset_gpio; ++ ++ if (has_incompat_firmware()) { ++ dev_err(dev, "detected incompatible firmware, bailing out\n"); ++ return -EINVAL; ++ } ++ if (!of_match_device(of_baikal_pcie_match, dev)) { ++ return -EINVAL; ++ } ++ ++ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); ++ if (!pcie) { ++ return -ENOMEM; ++ } ++ pcie->pp.dev = dev; ++ pcie->pp.ops = &baikal_pcie_ops; ++ ++ err = of_property_read_u32(dev->of_node, "num-lanes", &pcie->num_lanes); ++ if (err) { ++ dev_err(dev, "property num-lanes isn't found\n"); ++ return -EINVAL; ++ } ++ pcie->lcru = syscon_regmap_lookup_by_phandle(dev->of_node, ++ "baikal,pcie-lcru"); ++ if (IS_ERR(pcie->lcru)) { ++ dev_err(dev, "No LCRU phandle specified\n"); ++ pcie->lcru = NULL; ++ return -EINVAL; ++ } ++ ++ if (of_property_read_u32_array(dev->of_node, "baikal,pcie-lcru", index, 2)) { ++ pcie->lcru = NULL; ++ return -EINVAL; ++ } ++ ++ pcie->bus_nr = index[1]; ++ ++ pm_runtime_enable(dev); ++ err = pm_runtime_get_sync(dev); ++ if (err < 0) { ++ dev_err(dev, "pm_runtime_get_sync failed\n"); ++ goto err_pm_disable; ++ } ++ ++ reset_gpio = of_get_named_gpio_flags(dev->of_node, "reset-gpios", 0, ++ &gpio_flags); ++ if (gpio_is_valid(reset_gpio)) { ++ pcie->reset_gpio = gpio_to_desc(reset_gpio); ++ pcie->reset_active_low = gpio_flags & OF_GPIO_ACTIVE_LOW; ++ snprintf(pcie->reset_name, sizeof pcie->reset_name, ++ "pcie%u-reset", pcie->bus_nr); ++ } else { ++ pcie->reset_gpio = NULL; ++ } ++ ++ err = baikal_add_pcie_port(pcie, pdev); ++ if (err < 0) { ++ goto err_pm_put; ++ } ++ ++ platform_set_drvdata(pdev, pcie); ++ return 0; ++ ++err_pm_put: ++ pm_runtime_put(dev); ++ ++err_pm_disable: ++ pm_runtime_disable(dev); ++ ++ return err; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int baikal_pcie_suspend(struct device *dev) ++{ ++ struct baikal_pcie *pcie = dev_get_drvdata(dev); ++ struct dw_pcie *pp = &pcie->pp; ++ u32 val; ++ ++ /* Clear Memory Space Enable (MSE) bit */ ++ val = dw_pcie_readl_dbi(pp, PCI_COMMAND); ++ val &= ~PCI_COMMAND_MEMORY; ++ dw_pcie_writel_dbi(pp, PCI_COMMAND, val); ++ return 0; ++} ++ ++static int baikal_pcie_resume(struct device *dev) ++{ ++ struct baikal_pcie *pcie = dev_get_drvdata(dev); ++ struct dw_pcie *pp = &pcie->pp; ++ u32 val; ++ ++ /* Set Memory Space Enable (MSE) bit */ ++ val = dw_pcie_readl_dbi(pp, PCI_COMMAND); ++ val |= PCI_COMMAND_MEMORY; ++ dw_pcie_writel_dbi(pp, PCI_COMMAND, val); ++ return 0; ++} ++ ++static int baikal_pcie_suspend_noirq(struct device *dev) ++{ ++ return 0; ++} ++ ++static int baikal_pcie_resume_noirq(struct device *dev) ++{ ++ return 0; ++} ++#endif ++ ++static const struct dev_pm_ops baikal_pcie_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(baikal_pcie_suspend, baikal_pcie_resume) ++ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(baikal_pcie_suspend_noirq, ++ baikal_pcie_resume_noirq) ++}; ++ ++static struct platform_driver baikal_pcie_driver = { ++ .driver = { ++ .name = "baikal-pcie-v2", ++ .of_match_table = of_baikal_pcie_match, ++ .suppress_bind_attrs = true, ++ .pm = &baikal_pcie_pm_ops, ++ }, ++ .probe = baikal_pcie_probe, ++}; ++ ++MODULE_DEVICE_TABLE(of, of_baikal_pcie_match); ++module_platform_driver(baikal_pcie_driver); ++MODULE_LICENSE("GPL v2"); +-- +2.31.1 + diff --git a/0618-baikal_vdu-avoid-using-SMC-calls-for-updating-frameb.patch b/0618-baikal_vdu-avoid-using-SMC-calls-for-updating-frameb.patch new file mode 100644 index 0000000..268dba1 --- /dev/null +++ b/0618-baikal_vdu-avoid-using-SMC-calls-for-updating-frameb.patch @@ -0,0 +1,223 @@ +From 74a27e95a02db904c452f4b06b0e976cbecf113e Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Thu, 28 Jan 2021 18:44:36 +0400 +Subject: [PATCH 618/625] baikal_vdu: avoid using SMC calls for updating + framebuffer address + +(from SDK-M 4.4) +--- + drivers/gpu/drm/baikal/baikal_vdu_drm.h | 16 ----- + drivers/gpu/drm/baikal/baikal_vdu_drv.c | 2 - + drivers/gpu/drm/baikal/baikal_vdu_plane.c | 88 ++++++++--------------- + 3 files changed, 28 insertions(+), 78 deletions(-) + +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_drm.h b/drivers/gpu/drm/baikal/baikal_vdu_drm.h +index d049335dab1d..2db3fb73c9e7 100644 +--- a/drivers/gpu/drm/baikal/baikal_vdu_drm.h ++++ b/drivers/gpu/drm/baikal/baikal_vdu_drm.h +@@ -22,23 +22,12 @@ + + #include + #include +-#include + + struct clk; + struct drm_device; + struct drm_fbdev_cma; + struct drm_panel; + +-/*struct baikal_vdu_framebuffer { +- u32 base; +- u32 size; +- u32 index; +- u32 reg_base; +- u32 reg_size; +- u32 reg_width; +- u32 reg_height; +-};*/ +- + struct baikal_vdu_drm_connector { + struct drm_connector connector; + struct drm_panel *panel; +@@ -61,8 +50,6 @@ struct baikal_vdu_private { + + u32 fb_addr; + u32 fb_end; +- +- struct delayed_work update_work; + }; + + #define to_baikal_vdu_drm_connector(x) \ +@@ -89,7 +76,4 @@ int baikal_vdu_dumb_create(struct drm_file *file_priv, + + void baikal_vdu_debugfs_init(struct drm_minor *minor); + +-/* Worker functions */ +-void baikal_vdu_update_work(struct work_struct *work); +- + #endif /* __BAIKAL_VDU_DRM_H__ */ +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_drv.c b/drivers/gpu/drm/baikal/baikal_vdu_drv.c +index 0caa97dcb2e9..5deab510ea57 100644 +--- a/drivers/gpu/drm/baikal/baikal_vdu_drv.c ++++ b/drivers/gpu/drm/baikal/baikal_vdu_drv.c +@@ -152,8 +152,6 @@ static int vdu_modeset_init(struct drm_device *dev) + } + + arm_smccc_smc(BAIKAL_SMC_SCP_LOG_DISABLE, 0, 0, 0, 0, 0, 0, 0, &res); +- INIT_DEFERRABLE_WORK(&priv->update_work, +- baikal_vdu_update_work); + + drm_mode_config_reset(dev); + +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_plane.c b/drivers/gpu/drm/baikal/baikal_vdu_plane.c +index 9817af3c6de8..5a047835e154 100644 +--- a/drivers/gpu/drm/baikal/baikal_vdu_plane.c ++++ b/drivers/gpu/drm/baikal/baikal_vdu_plane.c +@@ -17,7 +17,6 @@ + * + */ + +-#include + #include + #include + #include +@@ -32,42 +31,6 @@ + #include "baikal_vdu_drm.h" + #include "baikal_vdu_regs.h" + +-#define BAIKAL_SMC_VDU_UPDATE_HDMI 0x82000100 +- +-void baikal_vdu_update_work(struct work_struct *work) +-{ +- struct arm_smccc_res res; +- unsigned long flags; +- struct baikal_vdu_private *priv = container_of(work, struct baikal_vdu_private, +- update_work.work); +- int count = 0; +- u64 t1, t2; +- t1 = read_sysreg(CNTVCT_EL0); +- spin_lock_irqsave(&priv->lock, flags); +- arm_smccc_smc(BAIKAL_SMC_VDU_UPDATE_HDMI, priv->fb_addr, priv->fb_end, 0, 0, 0, 0, 0, &res); +- spin_unlock_irqrestore(&priv->lock, flags); +- if (res.a0 == -EBUSY) +- priv->counters[15]++; +- else +- priv->counters[16]++; +- while (res.a0 == -EBUSY && count < 10) { +- count++; +- usleep_range(10000, 20000); +- res.a0 = 0; +- spin_lock_irqsave(&priv->lock, flags); +- arm_smccc_smc(BAIKAL_SMC_VDU_UPDATE_HDMI, priv->fb_addr, priv->fb_end, 0, 0, 0, 0, 0, &res); +- spin_unlock_irqrestore(&priv->lock, flags); +- if (res.a0 == -EBUSY) +- priv->counters[15]++; +- else +- priv->counters[16]++; +- } +- t2 = read_sysreg(CNTVCT_EL0); +- priv->counters[17] = t2 - t1; +- priv->counters[18] = count; +- priv->counters[19]++; +-} +- + static int baikal_vdu_primary_plane_atomic_check(struct drm_plane *plane, + struct drm_plane_state *state) + { +@@ -76,6 +39,7 @@ static int baikal_vdu_primary_plane_atomic_check(struct drm_plane *plane, + struct drm_crtc_state *crtc_state; + struct drm_display_mode *mode; + int rate, ret; ++ u32 cntl; + + if (!state->crtc) + return 0; +@@ -86,6 +50,9 @@ static int baikal_vdu_primary_plane_atomic_check(struct drm_plane *plane, + if (rate == clk_get_rate(priv->clk)) + return 0; + ++ /* hold clock domain reset; disable clocking */ ++ writel(0, priv->regs + PCTR); ++ + if (__clk_is_enabled(priv->clk)) + clk_disable_unprepare(priv->clk); + ret = clk_set_rate(priv->clk, rate); +@@ -94,15 +61,23 @@ static int baikal_vdu_primary_plane_atomic_check(struct drm_plane *plane, + if (ret < 0) { + DRM_ERROR("Cannot set desired pixel clock (%d Hz)\n", + rate); +- return -EINVAL; +- } +- clk_prepare_enable(priv->clk); +- if (!__clk_is_enabled(priv->clk)) { +- DRM_ERROR("PLL could not lock at desired frequency (%d Hz)\n", ++ ret = -EINVAL; ++ } else { ++ clk_prepare_enable(priv->clk); ++ if (__clk_is_enabled(priv->clk)) ++ ret = 0; ++ else { ++ DRM_ERROR("PLL could not lock at desired frequency (%d Hz)\n", + rate); +- return -EINVAL; ++ ret = -EINVAL; ++ } + } +- return 0; ++ ++ /* release clock domain reset; enable clocking */ ++ cntl = readl(priv->regs + PCTR); ++ cntl |= PCTR_PCR + PCTR_PCI; ++ ++ return ret; + } + + static void baikal_vdu_primary_plane_atomic_update(struct drm_plane *plane, +@@ -112,28 +87,13 @@ static void baikal_vdu_primary_plane_atomic_update(struct drm_plane *plane, + struct baikal_vdu_private *priv = dev->dev_private; + struct drm_plane_state *state = plane->state; + struct drm_framebuffer *fb = state->fb; +- struct arm_smccc_res res; + u32 cntl, addr, end; +- unsigned long flags; + + if (!fb) + return; + + addr = drm_fb_cma_get_gem_addr(fb, state, 0); +- end = ((addr + fb->height * fb->pitches[0] - 1) & MRR_DEAR_MRR_MASK) | MRR_OUTSTND_RQ(4); +- +- spin_lock_irqsave(&priv->lock, flags); +- arm_smccc_smc(BAIKAL_SMC_VDU_UPDATE_HDMI, addr, end, 0, 0, 0, 0, 0, &res); +- spin_unlock_irqrestore(&priv->lock, flags); +- +- if (res.a0 == -EBUSY) { +- priv->counters[15]++; +- priv->fb_addr = addr; +- priv->fb_end = end; +- smp_wmb(); +- schedule_delayed_work(&priv->update_work, usecs_to_jiffies(250)); +- } else +- priv->counters[16]++; ++ priv->fb_addr = addr & 0xfffffff8; + + cntl = readl(priv->regs + CR1); + cntl &= ~CR1_BPP_MASK; +@@ -178,6 +138,14 @@ static void baikal_vdu_primary_plane_atomic_update(struct drm_plane *plane, + break; + } + ++ writel(priv->fb_addr, priv->regs + DBAR); ++ end = ((priv->fb_addr + fb->height * fb->pitches[0] - 1) & MRR_DEAR_MRR_MASK) | \ ++ MRR_OUTSTND_RQ(4); ++ ++ if (priv->fb_end < end) { ++ writel(end, priv->regs + MRR); ++ priv->fb_end = end; ++ } + writel(cntl, priv->regs + CR1); + } + +-- +2.31.1 + diff --git a/0619-panfrost-compatibility-with-Baikal-M-firmware-from-S.patch b/0619-panfrost-compatibility-with-Baikal-M-firmware-from-S.patch new file mode 100644 index 0000000..2ff757a --- /dev/null +++ b/0619-panfrost-compatibility-with-Baikal-M-firmware-from-S.patch @@ -0,0 +1,30 @@ +From 190b6e5664f8a541f0f38da5dff65d39adf1b549 Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Tue, 16 Feb 2021 17:12:40 +0400 +Subject: [PATCH 619/625] panfrost: compatibility with Baikal-M firmware from + SDK-M 4.3 + +Added .compatible string so the driver can be used on Baikal-M +systems with firmware from SDK-M 4.3. + +Note: the driver should be explicitly enabled with +enable_broken_machines=y module parameter +--- + drivers/gpu/drm/panfrost/panfrost_drv.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c +index 689be734ed20..7376b17bc44a 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_drv.c ++++ b/drivers/gpu/drm/panfrost/panfrost_drv.c +@@ -681,6 +681,7 @@ static const struct of_device_id dt_match[] = { + { .compatible = "arm,mali-t860", .data = &default_data, }, + { .compatible = "arm,mali-t880", .data = &default_data, }, + { .compatible = "arm,mali-bifrost", .data = &default_data, }, ++ { .compatible = "arm,mali-midgard", .data = &default_data, }, + {} + }; + MODULE_DEVICE_TABLE(of, dt_match); +-- +2.31.1 + diff --git a/0620-cpufreq-dt-don-t-load-on-BE-M1000-SoC.patch b/0620-cpufreq-dt-don-t-load-on-BE-M1000-SoC.patch new file mode 100644 index 0000000..76c2717 --- /dev/null +++ b/0620-cpufreq-dt-don-t-load-on-BE-M1000-SoC.patch @@ -0,0 +1,136 @@ +From 7c3c753e3d32b250467bcc172f5abeb08dead01e Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Fri, 19 Feb 2021 12:55:03 +0400 +Subject: [PATCH 620/625] cpufreq-dt: don't load on BE-M1000 SoC + +Apparently the driver deadlocks the kernel in a few minutes: + +[ 454.690508] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks: +[ 454.696839] (detected by 4, t=26002 jiffies, g=22561, q=15) +[ 454.703017] rcu: All QSes seen, last rcu_preempt kthread activity 25992 (4295121102-4295095110), jiffies_till_next_fqs=3, root ->qsmask 0x0 +[ 454.715570] rcu: rcu_preempt kthread starved for 25992 jiffies! g22561 f0x2 RCU_GP_WAIT_FQS(5) ->state=0x200 ->cpu=1 +[ 454.726117] rcu: Unless rcu_preempt kthread gets sufficient CPU time, OOM is now expected behavior. +[ 454.735273] rcu: RCU grace-period kthread stack dump: +[ 454.740344] task:rcu_preempt state:R stack: 0 pid: 13 ppid: 2 flags:0x00000028 +[ 454.748731] Call trace: +[ 454.751204] __switch_to+0x114/0x170 +[ 454.754803] __schedule+0x370/0xa3c +[ 454.758310] schedule+0x50/0x104 +[ 454.761557] schedule_timeout+0x9c/0x114 +[ 454.765503] rcu_gp_kthread+0x598/0xb50 +[ 454.769360] kthread+0x150/0x160 +[ 454.772607] ret_from_fork+0x10/0x38 +[ 454.778130] +[ 454.779631] ================================ +[ 454.783912] WARNING: inconsistent lock state +[ 454.788196] 5.10.17-00041-g454ed3004040-dirty #1 Not tainted +[ 454.793867] -------------------------------- +[ 454.798147] inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage. +[ 454.804168] swapper/4/0 [HC0[0]:SC1[1]:HE0:SE0] takes: +[ 454.809319] ffff800011198498 (rcu_node_0){?.-.}-{2:2}, at: rcu_sched_clock_irq+0x480/0xce0 +[ 454.817615] {IN-HARDIRQ-W} state was registered at: +[ 454.822508] __lock_acquire+0xad8/0x2094 +[ 454.826530] lock_acquire.part.0+0xfc/0x360 +[ 454.830813] lock_acquire+0x68/0x84 +[ 454.834399] _raw_spin_lock_irqsave+0x84/0x158 +[ 454.838941] rcu_exp_handler+0xcc/0x140 +[ 454.842878] flush_smp_call_function_queue+0xec/0x304 +[ 454.848029] generic_smp_call_function_single_interrupt+0x20/0x2c +[ 454.854225] ipi_handler+0x1d8/0x39c +[ 454.857899] handle_percpu_devid_fasteoi_ipi+0xb0/0xe0 +[ 454.863137] __handle_domain_irq+0xbc/0x13c +[ 454.867419] gic_handle_irq+0xcc/0x14c +[ 454.871265] el1_irq+0xc4/0x180 +[ 454.874504] lock_acquire.part.0+0x120/0x360 +[ 454.878873] lock_acquire+0x68/0x84 +[ 454.882461] lock_page_memcg+0x5c/0x150 +[ 454.886399] page_add_file_rmap+0x28/0x27c +[ 454.890595] alloc_set_pte+0xb8/0x5c0 +[ 454.894356] filemap_map_pages+0x4a4/0x4c0 +[ 454.898551] handle_mm_fault+0xbcc/0xf50 +[ 454.902572] do_page_fault+0x14c/0x404 +[ 454.906418] do_translation_fault+0xbc/0xd8 +[ 454.910701] do_mem_abort+0x4c/0xac +[ 454.914287] el0_ia+0x68/0xcc +[ 454.917351] el0_sync_handler+0x180/0x1b0 +[ 454.921458] el0_sync+0x174/0x180 +[ 454.924868] irq event stamp: 449729 +[ 454.928368] hardirqs last enabled at (449725): [] default_idle_call+0x24/0xdc +[ 454.937171] hardirqs last disabled at (449726): [] enter_el1_irq_or_nmi+0x10/0x20 +[ 454.946237] softirqs last enabled at (449728): [] _local_bh_enable+0x30/0x54 +[ 454.954952] softirqs last disabled at (449729): [] __irq_exit_rcu+0x1b0/0x1bc +[ 454.963665] +[ 454.963665] other info that might help us debug this: +[ 454.970206] Possible unsafe locking scenario: +[ 454.970206] +[ 454.976136] CPU0 +[ 454.978590] ---- +[ 454.981043] lock(rcu_node_0); +[ 454.984198] +[ 454.986825] lock(rcu_node_0); +[ 454.990155] +[ 454.990155] *** DEADLOCK *** +[ 454.990155] +[ 454.996087] 1 lock held by swapper/4/0: +[ 454.999932] #0: ffff800011198498 (rcu_node_0){?.-.}-{2:2}, at: rcu_sched_clock_irq+0x480/0xce0 +[ 455.008662] +[ 455.008662] stack backtrace: +[ 455.013033] CPU: 4 PID: 0 Comm: swapper/4 Not tainted 5.10.17-00041-g454ed3004040-dirty #1 +[ 455.021313] Hardware name: Baikal Electronics Baikal-M mitx board (DT) +[ 455.027854] Call trace: +[ 455.030311] dump_backtrace+0x0/0x1e4 +[ 455.033985] show_stack+0x24/0x80 +[ 455.037312] dump_stack+0xec/0x154 +[ 455.040723] print_usage_bug.part.0+0x208/0x22c +[ 455.045265] mark_lock+0x88c/0x934 +[ 455.048677] mark_held_locks+0x58/0x90 +[ 455.052437] lockdep_hardirqs_on_prepare+0xe4/0x23c +[ 455.057330] trace_hardirqs_on+0x78/0x2e0 +[ 455.061350] __do_softirq+0x114/0x6d0 +[ 455.065022] __irq_exit_rcu+0x1b0/0x1bc +[ 455.068868] irq_exit+0x1c/0x54 +[ 455.072020] __handle_domain_irq+0xc0/0x13c +[ 455.076214] gic_handle_irq+0xcc/0x14c +[ 455.079972] el1_irq+0xc4/0x180 +[ 455.083124] arch_cpu_idle+0x18/0x30 +[ 455.086710] default_idle_call+0x5c/0xdc +[ 455.090645] do_idle+0x260/0x2e0 +[ 455.093883] cpu_startup_entry+0x30/0x8c +[ 455.097818] secondary_start_kernel+0x138/0x184 +[ 455.102410] BUG: scheduling while atomic: swapper/4/0/0x00000002 +[ 455.108449] INFO: lockdep is turned off. +[ 455.112399] Modules linked in: dm_mod designware_i2s sdhci_of_dwcmshc snd_soc_core sdhci_pltfm dw_hdmi_ahb_audio snd_pcm_dmaengine ac97_bus evdev sdhci snd_pcm at24 panfrost mmc_core snd_timer pcie_baikal_v44 snd pcie_baikal bt1_pvt gpu_sched soundcore cpufreq_dt fuse configfs efivarfs ipv6 +[ 455.138295] Preemption disabled at: +[ 455.138305] [] secondary_start_kernel+0xb4/0x184 +[ 455.148020] CPU: 4 PID: 0 Comm: swapper/4 Not tainted 5.10.17-00041-g454ed3004040-dirty #1 +[ 455.156299] Hardware name: Baikal Electronics Baikal-M mitx board (DT) +[ 455.162840] Call trace: +[ 455.165296] dump_backtrace+0x0/0x1e4 +[ 455.168969] show_stack+0x24/0x80 +[ 455.172295] dump_stack+0xec/0x154 +[ 455.175711] __schedule_bug+0xcc/0xe0 +[ 455.179383] __schedule+0x928/0xa3c +[ 455.182881] schedule_idle+0x34/0x5c +[ 455.186467] do_idle+0x1dc/0x2e0 +[ 455.189706] cpu_startup_entry+0x30/0x8c +[ 455.193640] secondary_start_kernel+0x138/0x184 +--- + drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c +index 1c192a42f11e..2885ad3779bf 100644 +--- a/drivers/cpufreq/cpufreq-dt-platdev.c ++++ b/drivers/cpufreq/cpufreq-dt-platdev.c +@@ -105,6 +105,8 @@ static const struct of_device_id blacklist[] __initconst = { + + { .compatible = "arm,vexpress", }, + ++ { .compatible = "baikal,baikal-m", }, ++ + { .compatible = "calxeda,highbank", }, + { .compatible = "calxeda,ecx-2000", }, + +-- +2.31.1 + diff --git a/0621-baikal_clk-compatibility-with-SDK-M-5.1-firmware.patch b/0621-baikal_clk-compatibility-with-SDK-M-5.1-firmware.patch new file mode 100644 index 0000000..455e2ce --- /dev/null +++ b/0621-baikal_clk-compatibility-with-SDK-M-5.1-firmware.patch @@ -0,0 +1,38 @@ +From 3a2d37d8f2aacdd8711f0f90a4c04d75eccd7a1f Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Fri, 19 Feb 2021 12:38:34 +0400 +Subject: [PATCH 621/625] baikal_clk: compatibility with SDK-M 5.1 firmware + +Without this patch the kernel seems to locks up within 10 -- 20 seconds +after the boot on a board with firmware from SDK-M 5.1 + +baikal_clk_set_rate: fixed parent rate calculation (from SDK-M 4.4) +--- + drivers/clk/baikal/clk-baikal.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/baikal/clk-baikal.c b/drivers/clk/baikal/clk-baikal.c +index ddf1d328eeaf..d9709322b2ee 100644 +--- a/drivers/clk/baikal/clk-baikal.c ++++ b/drivers/clk/baikal/clk-baikal.c +@@ -181,11 +181,15 @@ static int baikal_clk_set_rate(struct clk_hw *hw, unsigned long rate, + struct arm_smccc_res res; + struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); + uint32_t cmd; ++ unsigned long parent; + +- if (pclk->is_clk_ch) ++ if (pclk->is_clk_ch) { + cmd = CMU_CLK_CH_SET_RATE; +- else ++ parent = pclk->parent; ++ } else { + cmd = CMU_PLL_SET_RATE; ++ parent = parent_rate; ++ } + + pr_debug("[%s, %x:%d:%s] %s, %ld\n", + pclk->name, +-- +2.31.1 + diff --git a/0622-stmmac_mdio-implemented-reset-via-MAC-GP-out-pin.patch b/0622-stmmac_mdio-implemented-reset-via-MAC-GP-out-pin.patch new file mode 100644 index 0000000..ee74817 --- /dev/null +++ b/0622-stmmac_mdio-implemented-reset-via-MAC-GP-out-pin.patch @@ -0,0 +1,106 @@ +From ae07645b9fa53d7e863dc49998c266333d34906a Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Wed, 24 Feb 2021 13:46:49 +0400 +Subject: [PATCH 622/625] stmmac_mdio: implemented reset via MAC GP out pin + +BE-M1000 variant of stmmac mdio needs a special reset routine. + +Related: #39714 +--- + .../net/ethernet/stmicro/stmmac/stmmac_mdio.c | 68 ++++++++++++++++++- + 1 file changed, 66 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c +index b2a707e2ef43..fa7b13e932e3 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c +@@ -287,6 +287,63 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, + 100, 10000); + } + ++#define MAC_GPIO 0xe0 /* GPIO register */ ++#define MAC_GPIO_GPO0 (1 << 8) /* 0-output port */ ++ ++/** ++ * Reset the MII bus via MAC GP out pin ++ */ ++static int stmmac_mdio_reset_gp_out(struct stmmac_priv *priv) { ++#if IS_ENABLED(CONFIG_STMMAC_PLATFORM) && IS_ENABLED(CONFIG_OF) ++ u32 value, high, low; ++ u32 delays[3] = { 0, 0, 0 }; ++ bool active_low = false; ++ struct device_node *np = priv->device->of_node; ++ ++ if (!np) ++ return -ENODEV; ++ ++ if (!of_property_read_bool(np, "snps,reset-gp-out")) { ++ dev_warn(priv->device, "snps,reset-gp-out is not set\n"); ++ return -ENODEV; ++ } ++ ++ active_low = of_property_read_bool(np, "snsps,reset-active-low"); ++ of_property_read_u32_array(np, "snps,reset-delays-us", delays, 3); ++ ++ value = readl(priv->ioaddr + MAC_GPIO); ++ if (active_low) { ++ high = value | MAC_GPIO_GPO0; ++ low = value & ~MAC_GPIO_GPO0; ++ } else { ++ high = value & ~MAC_GPIO_GPO0; ++ low = value | MAC_GPIO_GPO0; ++ } ++ ++ writel(high, priv->ioaddr + MAC_GPIO); ++ if (delays[0]) ++ msleep(DIV_ROUND_UP(delays[0], 1000)); ++ ++ writel(low, priv->ioaddr + MAC_GPIO); ++ if (delays[1]) ++ msleep(DIV_ROUND_UP(delays[1], 1000)); ++ ++ writel(high, priv->ioaddr + MAC_GPIO); ++ if (delays[2]) ++ msleep(DIV_ROUND_UP(delays[2], 1000)); ++ ++ /* Clear PHY reset */ ++ udelay(10); ++ value = readl(priv->ioaddr + MAC_GPIO); ++ value |= MAC_GPIO_GPO0; ++ writel(value, priv->ioaddr + MAC_GPIO); ++ mdelay(1000); ++ dev_info(priv->device, "mdio reset completed\n"); ++ return 0; ++#endif ++ return -ENODEV; ++} ++ + /** + * stmmac_mdio_reset + * @bus: points to the mii_bus structure +@@ -302,13 +359,20 @@ int stmmac_mdio_reset(struct mii_bus *bus) + #ifdef CONFIG_OF + if (priv->device->of_node) { + struct gpio_desc *reset_gpio; ++ bool need_reset_gp_out; + u32 delays[3] = { 0, 0, 0 }; + + reset_gpio = devm_gpiod_get_optional(priv->device, + "snps,reset", + GPIOD_OUT_LOW); +- if (IS_ERR(reset_gpio)) +- return PTR_ERR(reset_gpio); ++ if (IS_ERR(reset_gpio)) { ++ need_reset_gp_out = of_property_read_bool(priv->device->of_node, ++ "snps,reset-gp-out"); ++ if (need_reset_gp_out) ++ return stmmac_mdio_reset_gp_out(priv); ++ else ++ return PTR_ERR(reset_gpio); ++ } + + device_property_read_u32_array(priv->device, + "snps,reset-delays-us", +-- +2.31.1 + diff --git a/0623-dwmac_baikal-clear-PHY-reset-before-calling-generic-.patch b/0623-dwmac_baikal-clear-PHY-reset-before-calling-generic-.patch new file mode 100644 index 0000000..f2e5447 --- /dev/null +++ b/0623-dwmac_baikal-clear-PHY-reset-before-calling-generic-.patch @@ -0,0 +1,60 @@ +From b7110f36a3ea12867eabcd5caeb104d23e1a3f4a Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Wed, 24 Feb 2021 16:45:30 +0400 +Subject: [PATCH 623/625] dwmac_baikal: clear PHY reset before calling generic + setup routine + +Without this attaching to Micrel PHY fails with the following error: + +[ 17.596114] Micrel KSZ9031 Gigabit PHY stmmac-2:03: phy_poll_reset failed: -110 +[ 17.603602] baikal-dwmac 30250000.eth1 eth1: no phy at addr -1 +[ 17.609468] baikal-dwmac 30250000.eth1 eth1: stmmac_open: Cannot attach to PHY (error: -19) + +Closes: #39714 +--- + .../net/ethernet/stmicro/stmmac/dwmac-baikal.c | 15 +++++++++++---- + 1 file changed, 11 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-baikal.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-baikal.c +index 646051cd500d..e706ece9b4f5 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-baikal.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-baikal.c +@@ -34,6 +34,14 @@ struct baikal_dwmac { + struct clk *tx2_clk; + }; + ++static void clear_phy_reset(void __iomem *ioaddr) ++{ ++ u32 value; ++ value = readl(ioaddr + MAC_GPIO); ++ value |= MAC_GPIO_GPO0; ++ writel(value, ioaddr + MAC_GPIO); ++} ++ + static int baikal_dwmac_dma_reset(void __iomem *ioaddr) + { + int err; +@@ -44,10 +52,7 @@ static int baikal_dwmac_dma_reset(void __iomem *ioaddr) + writel(value, ioaddr + DMA_BUS_MODE); + + udelay(10); +- /* Clear PHY reset */ +- value = readl(ioaddr + MAC_GPIO); +- value |= MAC_GPIO_GPO0; +- writel(value, ioaddr + MAC_GPIO); ++ clear_phy_reset(ioaddr); + pr_info("PHY re-inited for Baikal DWMAC\n"); + + err = readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, +@@ -90,6 +95,8 @@ static struct mac_device_info* baikal_dwmac_setup(void *ppriv) + if (!mac) + return NULL; + ++ clear_phy_reset(priv->ioaddr); ++ + mac->dma = &baikal_dwmac_dma_ops; + old_mac = priv->hw; + priv->hw = mac; +-- +2.31.1 + diff --git a/0624-BROKEN-dwc-i2s-support-BE-M1000-SoC.patch b/0624-BROKEN-dwc-i2s-support-BE-M1000-SoC.patch new file mode 100644 index 0000000..c853911 --- /dev/null +++ b/0624-BROKEN-dwc-i2s-support-BE-M1000-SoC.patch @@ -0,0 +1,101 @@ +From c0b58206fc41cad2dcf7ae9193d69aafdce89173 Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Mon, 29 Mar 2021 12:22:11 +0400 +Subject: [PATCH 624/625] (BROKEN) dwc-i2s: support BE-M1000 SoC + +* dw_i2s_probe: request all IRQs specified in device tree +* dw_i2s_startup: set the correct DAI clock frequency + +Note that the sound frequency is distorted (i.e. playing 440 Hz +sine wave results in 467 Hz), for more details see + +https://github.com/edelweiss-tech/kernel/issues/2 +--- + sound/soc/dwc/dwc-i2s.c | 36 ++++++++++++++++++++++++++---------- + sound/soc/dwc/local.h | 1 + + 2 files changed, 27 insertions(+), 10 deletions(-) + +diff --git a/sound/soc/dwc/dwc-i2s.c b/sound/soc/dwc/dwc-i2s.c +index fd4160289fac..e1efad33b522 100644 +--- a/sound/soc/dwc/dwc-i2s.c ++++ b/sound/soc/dwc/dwc-i2s.c +@@ -100,6 +100,7 @@ static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream, + + static irqreturn_t i2s_irq_handler(int irq, void *dev_id) + { ++ unsigned int rxor_count; + struct dw_i2s_dev *dev = dev_id; + bool irq_valid = false; + u32 isr[4]; +@@ -136,9 +137,13 @@ static irqreturn_t i2s_irq_handler(int irq, void *dev_id) + irq_valid = true; + } + +- /* Error Handling: TX */ ++ /* Error Handling: RX */ + if (isr[i] & ISR_RXFO) { +- dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i); ++ rxor_count = READ_ONCE(dev->rx_overrun_count); ++ if (!(rxor_count & 0x3ff)) ++ dev_dbg(dev->dev, "RX overrun (ch_id=%d)\n", i); ++ rxor_count++; ++ WRITE_ONCE(dev->rx_overrun_count, rxor_count); + irq_valid = true; + } + } +@@ -622,7 +627,8 @@ static int dw_i2s_probe(struct platform_device *pdev) + const struct i2s_platform_data *pdata = pdev->dev.platform_data; + struct dw_i2s_dev *dev; + struct resource *res; +- int ret, irq; ++ int ret, irq, irq_count; ++ unsigned idx; + struct snd_soc_dai_driver *dw_i2s_dai; + const char *clk_id; + +@@ -643,13 +649,23 @@ static int dw_i2s_probe(struct platform_device *pdev) + + dev->dev = &pdev->dev; + +- irq = platform_get_irq(pdev, 0); +- if (irq >= 0) { +- ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0, +- pdev->name, dev); +- if (ret < 0) { +- dev_err(&pdev->dev, "failed to request irq\n"); +- return ret; ++ irq_count = platform_irq_count(pdev); ++ if (irq_count < 0) /* - EPROBE_DEFER */ ++ return irq_count; ++ else if (!irq_count) { ++ dev_err(&pdev->dev, "no IRQs found for device\n"); ++ return -ENODEV; ++ } ++ ++ for (idx = 0; idx < (unsigned)irq_count; idx++) { ++ irq = platform_get_irq(pdev, idx); ++ if (irq >= 0) { ++ ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0, ++ pdev->name, dev); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to request irq\n"); ++ return ret; ++ } + } + } + +diff --git a/sound/soc/dwc/local.h b/sound/soc/dwc/local.h +index 91dc70a826f8..49167d89daae 100644 +--- a/sound/soc/dwc/local.h ++++ b/sound/soc/dwc/local.h +@@ -117,6 +117,7 @@ struct dw_i2s_dev { + bool *period_elapsed); + unsigned int tx_ptr; + unsigned int rx_ptr; ++ unsigned int rx_overrun_count; + }; + + #if IS_ENABLED(CONFIG_SND_DESIGNWARE_PCM) +-- +2.31.1 + diff --git a/0625-baikal_vdu_drm-LVDS-panel-support.patch b/0625-baikal_vdu_drm-LVDS-panel-support.patch new file mode 100644 index 0000000..84cfd2f --- /dev/null +++ b/0625-baikal_vdu_drm-LVDS-panel-support.patch @@ -0,0 +1,548 @@ +From d38a793e0efeb27e49b1ac0bad855f49f840684b Mon Sep 17 00:00:00 2001 +From: Alexey Sheplyakov +Date: Tue, 16 Mar 2021 12:45:43 +0400 +Subject: [PATCH 625/625] baikal_vdu_drm: (LVDS) panel support + +--- + drivers/gpu/drm/baikal/Makefile | 2 - + drivers/gpu/drm/baikal/baikal_vdu_connector.c | 54 ++++++++++++------ + drivers/gpu/drm/baikal/baikal_vdu_crtc.c | 55 ++++++++++++++----- + drivers/gpu/drm/baikal/baikal_vdu_drm.h | 32 +++-------- + drivers/gpu/drm/baikal/baikal_vdu_drv.c | 42 ++++++++------ + drivers/gpu/drm/baikal/baikal_vdu_encoder.c | 51 ----------------- + drivers/gpu/drm/baikal/baikal_vdu_gem.c | 37 ------------- + drivers/gpu/drm/baikal/baikal_vdu_regs.h | 13 +---- + 8 files changed, 113 insertions(+), 173 deletions(-) + delete mode 100644 drivers/gpu/drm/baikal/baikal_vdu_encoder.c + delete mode 100644 drivers/gpu/drm/baikal/baikal_vdu_gem.c + +diff --git a/drivers/gpu/drm/baikal/Makefile b/drivers/gpu/drm/baikal/Makefile +index 4c3e9e67befb..eb029494e823 100644 +--- a/drivers/gpu/drm/baikal/Makefile ++++ b/drivers/gpu/drm/baikal/Makefile +@@ -2,8 +2,6 @@ + baikal_vdu_drm-y += baikal_vdu_connector.o \ + baikal_vdu_crtc.o \ + baikal_vdu_drv.o \ +- baikal_vdu_encoder.o \ +- baikal_vdu_gem.o \ + baikal_vdu_plane.o + + baikal_vdu_drm-$(CONFIG_DEBUG_FS) += baikal_vdu_debugfs.o +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_connector.c b/drivers/gpu/drm/baikal/baikal_vdu_connector.c +index ca48e230f174..2f20cf3da627 100644 +--- a/drivers/gpu/drm/baikal/baikal_vdu_connector.c ++++ b/drivers/gpu/drm/baikal/baikal_vdu_connector.c +@@ -34,6 +34,9 @@ + #include "baikal_vdu_drm.h" + #include "baikal_vdu_regs.h" + ++#define to_baikal_vdu_private(x) \ ++ container_of(x, struct baikal_vdu_private, connector) ++ + static void baikal_vdu_drm_connector_destroy(struct drm_connector *connector) + { + drm_connector_unregister(connector); +@@ -43,10 +46,9 @@ static void baikal_vdu_drm_connector_destroy(struct drm_connector *connector) + static enum drm_connector_status baikal_vdu_drm_connector_detect( + struct drm_connector *connector, bool force) + { +- struct baikal_vdu_drm_connector *vdu_connector = +- to_baikal_vdu_drm_connector(connector); ++ struct baikal_vdu_private *priv = to_baikal_vdu_private(connector); + +- return (vdu_connector->panel ? ++ return (priv->panel ? + connector_status_connected : + connector_status_disconnected); + } +@@ -54,24 +56,18 @@ static enum drm_connector_status baikal_vdu_drm_connector_detect( + static int baikal_vdu_drm_connector_helper_get_modes( + struct drm_connector *connector) + { +- struct baikal_vdu_drm_connector *vdu_connector = +- to_baikal_vdu_drm_connector(connector); ++ struct baikal_vdu_private *priv = to_baikal_vdu_private(connector); + +- if (!vdu_connector) { +- pr_err("%s: vdu_connector == NULL\n", __func__); +- return 0; +- } +- if (!vdu_connector->panel) ++ if (!priv->panel) + return 0; + +- return drm_panel_get_modes(vdu_connector->panel, connector); ++ return drm_panel_get_modes(priv->panel, connector); + } + + const struct drm_connector_funcs connector_funcs = { + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = baikal_vdu_drm_connector_destroy, + .detect = baikal_vdu_drm_connector_detect, +- //.dpms = drm_atomic_helper_connector_dpms, // TODO enable it? + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +@@ -85,14 +81,38 @@ static const struct drm_encoder_funcs encoder_funcs = { + .destroy = drm_encoder_cleanup, + }; + +-int baikal_vdu_connector_create(struct drm_device *dev) ++int baikal_vdu_lvds_connector_create(struct drm_device *dev) + { + struct baikal_vdu_private *priv = dev->dev_private; +- struct baikal_vdu_drm_connector *vdu_connector = &priv->connector; +- struct drm_connector *connector = &vdu_connector->connector; ++ struct drm_connector *connector = &priv->connector; ++ struct drm_encoder *encoder = &priv->encoder; ++ int ret = 0; + +- drm_connector_init(dev, connector, &connector_funcs, ++ ret = drm_connector_init(dev, connector, &connector_funcs, + DRM_MODE_CONNECTOR_LVDS); ++ if (ret) { ++ dev_err(dev->dev, "drm_connector_init failed: %d\n", ret); ++ goto out; ++ } + drm_connector_helper_add(connector, &connector_helper_funcs); +- return 0; ++ ret = drm_encoder_init(dev, encoder, &encoder_funcs, ++ DRM_MODE_ENCODER_LVDS, NULL); ++ if (ret) { ++ dev_err(dev->dev, "drm_encoder_init failed: %d\n", ret); ++ goto out; ++ } ++ encoder->crtc = &priv->crtc; ++ encoder->possible_crtcs = drm_crtc_mask(encoder->crtc); ++ ret = drm_connector_attach_encoder(connector, encoder); ++ if (ret) { ++ dev_err(dev->dev, "drm_connector_attach_encoder failed: %d\n", ret); ++ goto out; ++ } ++ ret = drm_connector_register(connector); ++ if (ret) { ++ dev_err(dev->dev, "drm_connector_register failed: %d\n", ret); ++ goto out; ++ } ++out: ++ return ret; + } +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_crtc.c b/drivers/gpu/drm/baikal/baikal_vdu_crtc.c +index 6ef61791e299..d8bc1182bb77 100644 +--- a/drivers/gpu/drm/baikal/baikal_vdu_crtc.c ++++ b/drivers/gpu/drm/baikal/baikal_vdu_crtc.c +@@ -134,8 +134,13 @@ static void baikal_vdu_crtc_helper_mode_set_nofb(struct drm_crtc *crtc) + drm_mode_debug_printmodeline(mode); + + ppl = mode->hdisplay / 16; +- hsw = mode->hsync_end - mode->hsync_start - 1; +- hfp = mode->hsync_start - mode->hdisplay; ++ if (priv->panel) { ++ hsw = mode->hsync_end - mode->hsync_start; ++ hfp = mode->hsync_start - mode->hdisplay - 1; ++ } else { ++ hsw = mode->hsync_end - mode->hsync_start - 1; ++ hfp = mode->hsync_start - mode->hdisplay; ++ } + hbp = mode->htotal - mode->hsync_end; + + lpp = mode->vdisplay; +@@ -188,12 +193,15 @@ static void baikal_vdu_crtc_helper_enable(struct drm_crtc *crtc, + struct drm_crtc_state *old_state) + { + struct baikal_vdu_private *priv = crtc->dev->dev_private; +- u32 cntl; ++ struct drm_panel *panel = priv->panel; ++ struct device_node *panel_node; ++ const char *data_mapping; ++ u32 cntl, gpio; + + DRM_DEV_DEBUG_DRIVER(crtc->dev->dev, "enabling pixel clock\n"); + clk_prepare_enable(priv->clk); + +- drm_panel_prepare(priv->connector.panel); ++ drm_panel_prepare(panel); + + writel(ISCR_VSC_VFP, priv->regs + ISCR); + +@@ -202,13 +210,37 @@ static void baikal_vdu_crtc_helper_enable(struct drm_crtc *crtc, + cntl |= PCTR_PCR + PCTR_PCI; + writel(cntl, priv->regs + PCTR); + +- /* Set 16-word input FIFO watermark and 24-bit LCD interface mode */ ++ /* Set 16-word input FIFO watermark */ + /* Enable and Power Up */ + cntl = readl(priv->regs + CR1); +- cntl |= CR1_LCE + CR1_FDW_16_WORDS + CR1_OPS_LCD24; ++ cntl &= ~CR1_FDW_MASK; ++ cntl |= CR1_LCE + CR1_FDW_16_WORDS; ++ ++ if (priv->type == VDU_TYPE_LVDS) { ++ panel_node = panel->dev->of_node; ++ if (of_property_read_string(panel_node, "data-mapping", &data_mapping)) { ++ cntl |= CR1_OPS_LCD18; ++ } else if (strncmp(data_mapping, "vesa-24", 7)) ++ cntl |= CR1_OPS_LCD24; ++ else if (strncmp(data_mapping, "jeida-18", 8)) ++ cntl |= CR1_OPS_LCD18; ++ else { ++ dev_warn(crtc->dev->dev, "%s data mapping is not supported, vesa-24 is set\n", data_mapping); ++ cntl |= CR1_OPS_LCD24; ++ } ++ gpio = GPIOR_UHD_ENB; ++ if (priv->ep_count == 4) ++ gpio |= GPIOR_UHD_QUAD_PORT; ++ else if (priv->ep_count == 2) ++ gpio |= GPIOR_UHD_DUAL_PORT; ++ else ++ gpio |= GPIOR_UHD_SNGL_PORT; ++ writel(gpio, priv->regs + GPIOR); ++ } else ++ cntl |= CR1_OPS_LCD24; + writel(cntl, priv->regs + CR1); + +- drm_panel_enable(priv->connector.panel); ++ drm_panel_enable(priv->panel); + drm_crtc_vblank_on(crtc); + } + +@@ -217,12 +249,9 @@ void baikal_vdu_crtc_helper_disable(struct drm_crtc *crtc) + struct baikal_vdu_private *priv = crtc->dev->dev_private; + + drm_crtc_vblank_off(crtc); +- drm_panel_disable(priv->connector.panel); ++ drm_panel_disable(priv->panel); + +- /* Disable and Power Down */ +- //writel(0, priv->regs + CR1); +- +- drm_panel_unprepare(priv->connector.panel); ++ drm_panel_unprepare(priv->panel); + + /* Disable clock */ + DRM_DEV_DEBUG_DRIVER(crtc->dev->dev, "disabling pixel clock\n"); +@@ -250,8 +279,6 @@ static int baikal_vdu_enable_vblank(struct drm_crtc *crtc) + { + struct baikal_vdu_private *priv = crtc->dev->dev_private; + +- //clk_prepare_enable(priv->clk); +- + /* clear interrupt status */ + writel(0x3ffff, priv->regs + ISR); + +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_drm.h b/drivers/gpu/drm/baikal/baikal_vdu_drm.h +index 2db3fb73c9e7..9ab6303a4195 100644 +--- a/drivers/gpu/drm/baikal/baikal_vdu_drm.h ++++ b/drivers/gpu/drm/baikal/baikal_vdu_drm.h +@@ -23,22 +23,16 @@ + #include + #include + +-struct clk; +-struct drm_device; +-struct drm_fbdev_cma; +-struct drm_panel; +- +-struct baikal_vdu_drm_connector { +- struct drm_connector connector; +- struct drm_panel *panel; +-}; ++#define VDU_TYPE_HDMI 0 ++#define VDU_TYPE_LVDS 1 + + struct baikal_vdu_private { + struct drm_device *drm; + +- struct baikal_vdu_drm_connector connector; ++ struct drm_connector connector; + struct drm_crtc crtc; + struct drm_encoder encoder; ++ struct drm_panel *panel; + struct drm_bridge *bridge; + struct drm_plane primary; + +@@ -47,16 +41,12 @@ struct baikal_vdu_private { + spinlock_t lock; + u32 counters[20]; + int mode_fixup; +- ++ int type; ++ u32 ep_count; + u32 fb_addr; + u32 fb_end; + }; + +-#define to_baikal_vdu_drm_connector(x) \ +- container_of(x, struct baikal_vdu_drm_connector, connector) +- +-extern const struct drm_encoder_funcs baikal_vdu_encoder_funcs; +- + /* CRTC Functions */ + int baikal_vdu_crtc_create(struct drm_device *dev); + irqreturn_t baikal_vdu_irq(int irq, void *data); +@@ -64,15 +54,7 @@ irqreturn_t baikal_vdu_irq(int irq, void *data); + int baikal_vdu_primary_plane_init(struct drm_device *dev); + + /* Connector Functions */ +-int baikal_vdu_connector_create(struct drm_device *dev); +- +-/* Encoder Functions */ +-int baikal_vdu_encoder_init(struct drm_device *dev); +- +-/* GEM Functions */ +-int baikal_vdu_dumb_create(struct drm_file *file_priv, +- struct drm_device *dev, +- struct drm_mode_create_dumb *args); ++int baikal_vdu_lvds_connector_create(struct drm_device *dev); + + void baikal_vdu_debugfs_init(struct drm_minor *minor); + +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_drv.c b/drivers/gpu/drm/baikal/baikal_vdu_drv.c +index 5deab510ea57..8eb9dda7fa01 100644 +--- a/drivers/gpu/drm/baikal/baikal_vdu_drv.c ++++ b/drivers/gpu/drm/baikal/baikal_vdu_drv.c +@@ -23,7 +23,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -63,6 +62,10 @@ static struct drm_mode_config_funcs mode_config_funcs = { + .atomic_commit = drm_atomic_helper_commit, + }; + ++static const struct drm_encoder_funcs baikal_vdu_encoder_funcs = { ++ .destroy = drm_encoder_cleanup, ++}; ++ + static int vdu_modeset_init(struct drm_device *dev) + { + struct drm_mode_config *mode_config; +@@ -94,38 +97,35 @@ static int vdu_modeset_init(struct drm_device *dev) + } + + ret = drm_of_find_panel_or_bridge(dev->dev->of_node, -1, -1, +- &priv->connector.panel, ++ &priv->panel, + &priv->bridge); + if (ret == -EPROBE_DEFER) { + dev_info(dev->dev, "Bridge probe deferred\n"); + goto out_config; + } + +- ret = baikal_vdu_encoder_init(dev); +- if (ret) { +- dev_err(dev->dev, "Failed to create DRM encoder\n"); +- goto out_config; +- } +- + if (priv->bridge) { ++ struct drm_encoder *encoder = &priv->encoder; ++ ret = drm_encoder_init(dev, encoder, &baikal_vdu_encoder_funcs, ++ DRM_MODE_ENCODER_NONE, NULL); ++ if (ret) { ++ dev_err(dev->dev, "failed to create DRM encoder\n"); ++ goto out_config; ++ } ++ encoder->crtc = &priv->crtc; ++ encoder->possible_crtcs = drm_crtc_mask(encoder->crtc); + priv->bridge->encoder = &priv->encoder; + ret = drm_bridge_attach(&priv->encoder, priv->bridge, NULL, 0); + if (ret) { + dev_err(dev->dev, "Failed to attach DRM bridge %d\n", ret); + goto out_config; + } +- } else if (priv->connector.panel) { +- ret = baikal_vdu_connector_create(dev); ++ } else if (priv->panel) { ++ ret = baikal_vdu_lvds_connector_create(dev); + if (ret) { + dev_err(dev->dev, "Failed to create DRM connector\n"); + goto out_config; + } +- ret = drm_connector_attach_encoder(&priv->connector.connector, +- &priv->encoder); +- if (ret != 0) { +- dev_err(dev->dev, "Failed to attach encoder\n"); +- goto out_config; +- } + } else + ret = -EINVAL; + +@@ -194,7 +194,7 @@ static struct drm_driver vdu_drm_driver = { + .major = 1, + .minor = 0, + .patchlevel = 0, +- .dumb_create = baikal_vdu_dumb_create, ++ .dumb_create = drm_gem_cma_dumb_create, + .gem_create_object = drm_gem_cma_create_object_default_funcs, + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, +@@ -254,6 +254,14 @@ static int baikal_vdu_drm_probe(struct platform_device *pdev) + return ret; + } + ++ if (pdev->dev.of_node && of_property_read_bool(pdev->dev.of_node, "lvds-out")) { ++ priv->type = VDU_TYPE_LVDS; ++ if (of_property_read_u32(pdev->dev.of_node, "num-lanes", &priv->ep_count)) ++ priv->ep_count = 1; ++ } ++ else ++ priv->type = VDU_TYPE_HDMI; ++ + ret = vdu_modeset_init(drm); + if (ret != 0) { + dev_err(dev, "Failed to init modeset\n"); +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_encoder.c b/drivers/gpu/drm/baikal/baikal_vdu_encoder.c +deleted file mode 100644 +index 9081d196dac3..000000000000 +--- a/drivers/gpu/drm/baikal/baikal_vdu_encoder.c ++++ /dev/null +@@ -1,51 +0,0 @@ +-/* +- * Copyright (C) 2019-2020 Baikal Electronics JSC +- * +- * Author: Pavel Parkhomenko +- * +- * Parts of this file were based on sources as follows: +- * +- * Copyright (c) 2006-2008 Intel Corporation +- * Copyright (c) 2007 Dave Airlie +- * Copyright (C) 2011 Texas Instruments +- * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. +- * +- * This program is free software and is provided to you under the terms of the +- * GNU General Public License version 2 as published by the Free Software +- * Foundation, and any use by you of this program is subject to the terms of +- * such GNU licence. +- * +- */ +- +-/** +- * baikal_vdu_encoder.c +- * Implementation of the encoder functions for Baikal Electronics BE-M1000 VDU driver +- */ +-#include +-#include +-#include +- +-#include +- +-#include "baikal_vdu_drm.h" +- +-const struct drm_encoder_funcs baikal_vdu_encoder_funcs = { +- .destroy = drm_encoder_cleanup, +-}; +- +-int baikal_vdu_encoder_init(struct drm_device *dev) +-{ +- struct baikal_vdu_private *priv = dev->dev_private; +- struct drm_encoder *encoder = &priv->encoder; +- int ret; +- +- ret = drm_encoder_init(dev, encoder, &baikal_vdu_encoder_funcs, +- DRM_MODE_ENCODER_NONE, NULL); +- if (ret) +- return ret; +- +- encoder->crtc = &priv->crtc; +- encoder->possible_crtcs = BIT(drm_crtc_index(encoder->crtc)); +- +- return 0; +-} +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_gem.c b/drivers/gpu/drm/baikal/baikal_vdu_gem.c +deleted file mode 100644 +index b07566caf12c..000000000000 +--- a/drivers/gpu/drm/baikal/baikal_vdu_gem.c ++++ /dev/null +@@ -1,37 +0,0 @@ +-/* +- * Copyright (C) 2019-2020 Baikal Electronics JSC +- * +- * Author: Pavel Parkhomenko +- * +- * Parts of this file were based on sources as follows: +- * +- * Copyright (c) 2006-2008 Intel Corporation +- * Copyright (c) 2007 Dave Airlie +- * Copyright (C) 2011 Texas Instruments +- * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. +- * +- * This program is free software and is provided to you under the terms of the +- * GNU General Public License version 2 as published by the Free Software +- * Foundation, and any use by you of this program is subject to the terms of +- * such GNU licence. +- * +- */ +- +-/** +- * baikal_vdu_gem.c +- * Implementation of the GEM functions for Baikal Electronics BE-M1000 VDU driver +- */ +-#include +-#include +-#include +-#include +-#include +-#include "baikal_vdu_drm.h" +- +-int baikal_vdu_dumb_create(struct drm_file *file_priv, +- struct drm_device *dev, struct drm_mode_create_dumb *args) +-{ +- args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8); +- +- return drm_gem_cma_dumb_create_internal(file_priv, dev, args); +-} +diff --git a/drivers/gpu/drm/baikal/baikal_vdu_regs.h b/drivers/gpu/drm/baikal/baikal_vdu_regs.h +index a0d8e69eb5e6..5553fcac5fec 100644 +--- a/drivers/gpu/drm/baikal/baikal_vdu_regs.h ++++ b/drivers/gpu/drm/baikal/baikal_vdu_regs.h +@@ -1,5 +1,6 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ + /* +- * Copyright (C) 2019-2020 Baikal Electronics JSC ++ * Copyright (C) 2019-2021 Baikal Electronics JSC + * + * Author: Pavel Parkhomenko + * +@@ -7,10 +8,6 @@ + * + * David A Rusling + * Copyright (C) 2001 ARM Limited +- * +- * This file is subject to the terms and conditions of the GNU General Public +- * License. See the file COPYING in the main directory of this archive +- * for more details. + */ + + #ifndef __BAIKAL_VDU_REGS_H__ +@@ -50,6 +47,7 @@ + #define INTR_FER BIT(4) + + #define CR1_FBP BIT(19) ++#define CR1_FDW_MASK GENMASK(17, 16) + #define CR1_FDW_4_WORDS (0 << 16) + #define CR1_FDW_8_WORDS (1 << 16) + #define CR1_FDW_16_WORDS (2 << 16) +@@ -129,15 +127,10 @@ + #define HPPLOR_HPPLO(x) ((x) << 0) + + #define GPIOR_UHD_MASK GENMASK(23, 16) +-#define GPIOR_UHD_FMT_LDI (0 << 20) +-#define GPIOR_UHD_FMT_VESA (1 << 20) +-#define GPIOR_UHD_FMT_JEIDA (2 << 20) + #define GPIOR_UHD_SNGL_PORT (0 << 18) + #define GPIOR_UHD_DUAL_PORT (1 << 18) + #define GPIOR_UHD_QUAD_PORT (2 << 18) + #define GPIOR_UHD_ENB BIT(17) +-#define GPIOR_UHD_PIX_INTLV (0 << 16) +-#define GPIOR_UHD_PIX_SQNTL (1 << 16) + + #define MRR_DEAR_MRR_MASK GENMASK(31, 3) + #define MRR_OUTSTND_RQ_MASK GENMASK(2, 0) +-- +2.31.1 + diff --git a/kernel-arm64.config b/kernel-arm64.config index 9ca30b3..1c9fba7 100644 --- a/kernel-arm64.config +++ b/kernel-arm64.config @@ -1,16 +1,17 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.10.17 Kernel Configuration +# Linux/arm64 5.10.45 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="gcc (GCC) 10.2.0 20200723 (ROSA)" +CONFIG_CC_VERSION_TEXT="gcc (GCC) 11.1.0 20210427 (ROSA)" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=100200 +CONFIG_GCC_VERSION=110100 CONFIG_LD_VERSION=236010000 CONFIG_CLANG_VERSION=0 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y @@ -221,6 +222,7 @@ CONFIG_USERMODE_DRIVER=y # CONFIG_BPF_PRELOAD is not set CONFIG_USERFAULTFD=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_KCMP=y CONFIG_RSEQ=y # CONFIG_DEBUG_RSEQ is not set # CONFIG_EMBEDDED is not set @@ -289,6 +291,7 @@ CONFIG_ARCH_ACTIONS=y CONFIG_ARCH_AGILEX=y CONFIG_ARCH_SUNXI=y CONFIG_ARCH_ALPINE=y +CONFIG_ARCH_BAIKAL=y CONFIG_ARCH_BCM2835=y CONFIG_ARCH_BCM_IPROC=y CONFIG_ARCH_BERLIN=y @@ -2111,7 +2114,6 @@ CONFIG_PCIEASPM_DEFAULT=y CONFIG_PCIE_PME=y CONFIG_PCIE_DPC=y CONFIG_PCIE_PTM=y -# CONFIG_PCIE_BW is not set CONFIG_PCIE_EDR=y CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y @@ -2168,6 +2170,7 @@ CONFIG_PCIE_ROCKCHIP_HOST=m CONFIG_PCIE_ROCKCHIP_EP=y CONFIG_PCIE_MEDIATEK=m CONFIG_PCIE_BRCMSTB=m +CONFIG_PCI_BAIKAL=m CONFIG_PCIE_HISI_ERR=y # @@ -2632,6 +2635,7 @@ CONFIG_XILINX_SDFEC=m CONFIG_MISC_RTSX=m CONFIG_PVPANIC=m CONFIG_HISI_HIKEY_USB=m +CONFIG_TP_BMC=y CONFIG_C2PORT=m # @@ -3478,6 +3482,7 @@ CONFIG_STMMAC_ETH=m CONFIG_STMMAC_PLATFORM=m CONFIG_DWMAC_DWC_QOS_ETH=m CONFIG_DWMAC_GENERIC=m +CONFIG_DWMAC_BAIKAL=m CONFIG_DWMAC_IPQ806X=m CONFIG_DWMAC_MEDIATEK=m CONFIG_DWMAC_MESON=m @@ -4461,7 +4466,7 @@ CONFIG_SERIAL_8250_RSA=y CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_BCM2835AUX=m CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_DW=m +CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_8250_RT288X=y CONFIG_SERIAL_8250_OMAP=m CONFIG_SERIAL_8250_MT6577=m @@ -5094,7 +5099,7 @@ CONFIG_GPIO_BCM_XGS_IPROC=m CONFIG_GPIO_BRCMSTB=m CONFIG_GPIO_CADENCE=m CONFIG_GPIO_DAVINCI=y -CONFIG_GPIO_DWAPB=m +CONFIG_GPIO_DWAPB=y CONFIG_GPIO_EIC_SPRD=m CONFIG_GPIO_EXAR=m CONFIG_GPIO_FTGPIO010=y @@ -5383,6 +5388,8 @@ CONFIG_SENSORS_ARM_SCMI=m CONFIG_SENSORS_ARM_SCPI=m CONFIG_SENSORS_ASPEED=m CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_BT1_PVT=m +CONFIG_SENSORS_BT1_PVT_ALARMS=y CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_DRIVETEMP=m CONFIG_SENSORS_DS620=m @@ -6988,6 +6995,7 @@ CONFIG_DRM_MALI_DISPLAY=m CONFIG_DRM_KOMEDA=m # end of ARM devices +CONFIG_DRM_BAIKAL_VDU=m CONFIG_DRM_RADEON=m # CONFIG_DRM_RADEON_USERPTR is not set CONFIG_DRM_AMDGPU=m @@ -7168,6 +7176,7 @@ CONFIG_DRM_CHRONTEL_CH7033=m CONFIG_DRM_DISPLAY_CONNECTOR=m CONFIG_DRM_LONTIUM_LT9611=m CONFIG_DRM_LVDS_CODEC=m +CONFIG_DRM_BAIKAL_HDMI=m CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m CONFIG_DRM_NWL_MIPI_DSI=m CONFIG_DRM_NXP_PTN3460=m @@ -8347,6 +8356,7 @@ CONFIG_USB_DWC3_KEYSTONE=m CONFIG_USB_DWC3_MESON_G12A=m CONFIG_USB_DWC3_OF_SIMPLE=m CONFIG_USB_DWC3_QCOM=m +CONFIG_USB_DWC3_BAIKAL=m CONFIG_USB_DWC2=y CONFIG_USB_DWC2_HOST=y @@ -9008,7 +9018,7 @@ CONFIG_RTC_I2C_AND_SPI=y # CONFIG_RTC_DRV_DS3232=m CONFIG_RTC_DRV_DS3232_HWMON=y -CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF2127=y CONFIG_RTC_DRV_RV3029C2=m CONFIG_RTC_DRV_RV3029_HWMON=y @@ -10955,7 +10965,6 @@ CONFIG_RESET_TEGRA_BPMP=y CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PHY_MIPI_DPHY=y CONFIG_PHY_XGENE=m -CONFIG_USB_LGM_PHY=m CONFIG_PHY_SUN4I_USB=m CONFIG_PHY_SUN6I_MIPI_DPHY=m CONFIG_PHY_SUN9I_USB=m @@ -12117,7 +12126,7 @@ CONFIG_DMA_CMA=y # # Default contiguous memory area size: # -CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_CMA_SIZE_MBYTES=256 CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set # CONFIG_CMA_SIZE_SEL_MIN is not set @@ -12223,6 +12232,7 @@ CONFIG_KDB_KEYBOARD=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y # CONFIG_UBSAN is not set +CONFIG_HAVE_KCSAN_COMPILER=y # end of Generic Kernel Debugging Instruments CONFIG_DEBUG_KERNEL=y diff --git a/kernel.spec b/kernel.spec index 16bf906..50ca7f1 100644 --- a/kernel.spec +++ b/kernel.spec @@ -342,6 +342,36 @@ Patch306: 0001-ROSA-ima-allow-to-off-modules-signature-check-dynami.patch Patch307: le9pf.diff Patch308: 0001-Revert-kallsyms-unexport-kallsyms_lookup_name-and-ka.patch +# Support SoC with Baikal-M (ARMv8) CPU +# From http://git.altlinux.org/gears/k/kernel-image-std-def.git (many thanks!) +# They are based on sources from official SDK with patched kernel from Baikal Electronics +Patch0601: 0601-Baikal-M-Kconfig-defconfig.patch +Patch0602: 0602-Baikal-M-clock-driver.patch +Patch0603: 0603-efi-rtc-avoid-calling-efi.get_time-on-Baikal-M-board.patch +Patch0604: 0604-efi-arm-runtime-print-EFI-mapping.patch +Patch0605: 0605-ethernet-stmmac-made-dwmac1000_-DMA-functions-availa.patch +Patch0606: 0606-stmmac-Baikal-M-dwmac-driver.patch +Patch0607: 0607-Fixed-secondary-CPUs-boot-on-BE-M1000-SoC.patch +Patch0608: 0608-Baikal-M-USB-driver.patch +# https://bugzilla.altlinux.org/show_bug.cgi?id=40269 +Patch0609: 0609-Baikal-M-video-unit-driver.patch +Patch0610: 0610-Added-Baikal-T1-M-BMC-driver.patch +Patch0611: 0611-dw-hdmi-ahb-audio-support-BE-M1000-SoC.patch +Patch0612: 0612-bt1-pvt.c-access-registers-via-pvt_-readl-writel-hel.patch +Patch0613: 0613-bt1-pvt-define-pvt_readl-pvt_writel-for-BE-M1000-SoC.patch +Patch0614: 0614-bt1-pvt-adjust-probing-for-BE-M1000-SoC.patch +Patch0615: 0615-bt1-pvt-added-compatible-baikal-pvt.patch +Patch0616: 0616-Baikal-M-PCIe-driver-from-SDK-M-4.3.patch +Patch0617: 0617-Baikal-M-PCIe-driver-from-SDK-M-4.4.patch +Patch0618: 0618-baikal_vdu-avoid-using-SMC-calls-for-updating-frameb.patch +Patch0619: 0619-panfrost-compatibility-with-Baikal-M-firmware-from-S.patch +Patch0620: 0620-cpufreq-dt-don-t-load-on-BE-M1000-SoC.patch +Patch0621: 0621-baikal_clk-compatibility-with-SDK-M-5.1-firmware.patch +Patch0622: 0622-stmmac_mdio-implemented-reset-via-MAC-GP-out-pin.patch +Patch0623: 0623-dwmac_baikal-clear-PHY-reset-before-calling-generic-.patch +Patch0624: 0624-BROKEN-dwc-i2s-support-BE-M1000-SoC.patch +Patch0625: 0625-baikal_vdu_drm-LVDS-panel-support.patch + # Disable AutoReq AutoReq: 0 # but keep autoprov for kmod(xxx)