Add patches of panfrost driver for Baikal

Found information about them by vising commits to Mesa.git here: https://github.com/asheplyakov/panfrost-baikalm-howto + viewe git log v5.4.10..45..[alt's tag] of kernel
2025-02-23 18:42:55 +00:00 · 2021-06-23 19:21:23 +03:00 · 2021-06-23 19:21:23 +03:00 · 588bd7cdd3
commit 588bd7cdd3
parent 839b6a86b6
4 changed files with 123 additions and 1 deletions
--- a/0626-Serial-82550_dw-Fix-clock-rate-setting-in-dw8250_set.patch
+++ b/0626-Serial-82550_dw-Fix-clock-rate-setting-in-dw8250_set.patch
@ -0,0 +1,45 @@
+From 7349284a3d505346b1e2913e5b04efbe9b9b32c8 Mon Sep 17 00:00:00 2001
+From: "Vadim V. Vlasov" <vvv19xx@gmail.com>
+Date: Fri, 16 Oct 2020 17:14:00 +0300
+Subject: [PATCH] Serial: 82550_dw: Fix clock rate setting in
+ dw8250_set_termios()
+
+If clk_round_rate() returns rate out of 1/16 precision range from
+the desired rate, then do not change clock rate.
+
+This usually happens if the desired rate is below the minimum
+supported by the clk.
+
+Fixes UART console on BE-M1000 SoC (without this patch the console
+gets garbled after loading the driver)
+---
+ drivers/tty/serial/8250/8250_dw.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
+index 9e204f9b799a..0c29137a6583 100644
+--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
+@@ -329,14 +329,17 @@ dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
+ static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
+ 			       struct ktermios *old)
+ {
+-	unsigned long newrate = tty_termios_baud_rate(termios) * 16;
+	unsigned long baud = tty_termios_baud_rate(termios);
+	unsigned long newrate = baud * 16;
+ 	struct dw8250_data *d = to_dw8250_data(p->private_data);
+ 	long rate;
+ 	int ret;
+ 
+ 	clk_disable_unprepare(d->clk);
+ 	rate = clk_round_rate(d->clk, newrate);
+-	if (rate > 0) {
+	if (rate > baud * 17 || rate < baud * 15) {
+		ret = -EINVAL; /* cannot set rate with acceptable accuracy */
+	} else if (rate > 0) {
+ 		/*
+ 		 * Premilinary set the uartclk to the new clock rate so the
+ 		 * clock update event handler caused by the clk_set_rate()
+-- 
+2.31.1
+
--- a/0627-drm-panfrost-Fix-memory-attributes-for-Mali-T620.patch
+++ b/0627-drm-panfrost-Fix-memory-attributes-for-Mali-T620.patch
@ -0,0 +1,46 @@
+From 6d1046bd245b1167b263f76b400c9426fca02113 Mon Sep 17 00:00:00 2001
+From: "Vadim V. Vlasov" <vvv19xx@gmail.com>
+Date: Thu, 26 Nov 2020 18:45:58 +0300
+Subject: [PATCH] drm/panfrost: Fix memory attributes for Mali T620
+
+Fix #19
+---
+ drivers/gpu/drm/panfrost/panfrost_mmu.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c
+index be8d68fb0e11..9762f3639aff 100644
+--- a/drivers/gpu/drm/panfrost/panfrost_mmu.c
+++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c
+@@ -123,6 +123,10 @@ static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_m
+ 	/* Need to revisit mem attrs.
+ 	 * NC is the default, Mali driver is inner WT.
+ 	 */
+	if (panfrost_model_eq(pfdev, 0x620)) {
+		memattr &= ~0xf0f0f0ULL;
+		memattr |= 0x404040;
+	}
+ 	mmu_write(pfdev, AS_MEMATTR_LO(as_nr), memattr & 0xffffffffUL);
+ 	mmu_write(pfdev, AS_MEMATTR_HI(as_nr), memattr >> 32);
+ 
+@@ -186,7 +190,7 @@ u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
+ 	atomic_set(&mmu->as_count, 1);
+ 	list_add(&mmu->list, &pfdev->as_lru_list);
+ 
+-	dev_dbg(pfdev->dev, "Assigned AS%d to mmu %p, alloc_mask=%lx", as, mmu, pfdev->as_alloc_mask);
+	dev_dbg(pfdev->dev, "Assigned AS%d to mmu %px, alloc_mask=%lx", as, mmu, pfdev->as_alloc_mask);
+ 
+ 	panfrost_mmu_enable(pfdev, mmu);
+ 
+@@ -287,6 +291,8 @@ int panfrost_mmu_map(struct panfrost_gem_mapping *mapping)
+ 
+ 	if (bo->noexec)
+ 		prot |= IOMMU_NOEXEC;
+	if (bo->is_heap)
+		prot |= IOMMU_CACHE;
+ 
+ 	sgt = drm_gem_shmem_get_pages_sgt(obj);
+ 	if (WARN_ON(IS_ERR(sgt)))
+-- 
+2.31.1
+
--- a/0628-drm-panfrost-Trim-affinity-for-Mali-T620.patch
+++ b/0628-drm-panfrost-Trim-affinity-for-Mali-T620.patch
@ -0,0 +1,27 @@
+From 5192df6d13aa5ad12c5ade843a598b428760d9c0 Mon Sep 17 00:00:00 2001
+From: "Vadim V. Vlasov" <vvv19xx@gmail.com>
+Date: Fri, 11 Dec 2020 16:55:06 +0300
+Subject: [PATCH] drm/panfrost: Trim affinity for Mali T620
+
+libmali uses 0xf affinity instead of 0xff for jobs in slot 1.
+Looks like this resolves problem with cache incoherency.
+---
+ drivers/gpu/drm/panfrost/panfrost_job.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c b/drivers/gpu/drm/panfrost/panfrost_job.c
+index 04e6f6f9b742..28a1a8f50fad 100644
+--- a/drivers/gpu/drm/panfrost/panfrost_job.c
+++ b/drivers/gpu/drm/panfrost/panfrost_job.c
+@@ -143,6 +143,8 @@ static void panfrost_job_write_affinity(struct panfrost_device *pfdev,
+ 	 * multiple (2) coherent core groups
+ 	 */
+ 	affinity = pfdev->features.shader_present;
+	if (panfrost_model_eq(pfdev, 0x620) && js == 1)
+		affinity &= 0xf;
+ 
+ 	job_write(pfdev, JS_AFFINITY_NEXT_LO(js), affinity & 0xFFFFFFFF);
+ 	job_write(pfdev, JS_AFFINITY_NEXT_HI(js), affinity >> 32);
+-- 
+2.31.1
+
--- a/kernel.spec
+++ b/kernel.spec
@ -32,7 +32,7 @@
 %define sublevel 45

 # Release number. Increase this before a rebuild.
-%define rpmrel 1
+%define rpmrel 2
 %define fullrpmrel	%{rpmrel}

 %define rpmtag		%{disttag}
@ -371,6 +371,10 @@ Patch0622: 0622-stmmac_mdio-implemented-reset-via-MAC-GP-out-pin.patch
 Patch0623: 0623-dwmac_baikal-clear-PHY-reset-before-calling-generic-.patch
 Patch0624: 0624-BROKEN-dwc-i2s-support-BE-M1000-SoC.patch
 Patch0625: 0625-baikal_vdu_drm-LVDS-panel-support.patch
+Patch0626: 0626-Serial-82550_dw-Fix-clock-rate-setting-in-dw8250_set.patch
+Patch0627: 0627-drm-panfrost-Fix-memory-attributes-for-Mali-T620.patch
+Patch0628: 0628-drm-panfrost-Trim-affinity-for-Mali-T620.patch
+

 # Disable AutoReq
 AutoReq: 	0