kernel-5.15/0626-Serial-82550_dw-Fix-clock-rate-setting-in-dw8250_set.patch

From 7349284a3d505346b1e2913e5b04efbe9b9b32c8 Mon Sep 17 00:00:00 2001
From: "Vadim V. Vlasov" <vvv19xx@gmail.com>
Date: Fri, 16 Oct 2020 17:14:00 +0300
Subject: [PATCH] Serial: 82550_dw: Fix clock rate setting in
 dw8250_set_termios()

If clk_round_rate() returns rate out of 1/16 precision range from
the desired rate, then do not change clock rate.

This usually happens if the desired rate is below the minimum
supported by the clk.

Fixes UART console on BE-M1000 SoC (without this patch the console
gets garbled after loading the driver)
---
 drivers/tty/serial/8250/8250_dw.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 9e204f9b799a..0c29137a6583 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -329,14 +329,17 @@ dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
 			       struct ktermios *old)
 {
-	unsigned long newrate = tty_termios_baud_rate(termios) * 16;
+	unsigned long baud = tty_termios_baud_rate(termios);
+	unsigned long newrate = baud * 16;
 	struct dw8250_data *d = to_dw8250_data(p->private_data);
 	long rate;
 	int ret;
 
 	clk_disable_unprepare(d->clk);
 	rate = clk_round_rate(d->clk, newrate);
-	if (rate > 0) {
+	if (rate > baud * 17 || rate < baud * 15) {
+		ret = -EINVAL; /* cannot set rate with acceptable accuracy */
+	} else if (rate > 0) {
 		/*
 		 * Premilinary set the uartclk to the new clock rate so the
 		 * clock update event handler caused by the clk_set_rate()
-- 
2.31.1