mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 17:44:19 +00:00
fffde230ba
* changes: fix(versal2): modify function to have single return fix(versal-net): modify function to have single return fix(versal): modify function to have single return fix(xilinx): modify function to have single return fix(zynqmp): modify function to have single return fix(versal-net): add unsigned suffix to match data type fix(versal): add unsigned suffix to match data type fix(versal2): add missing curly braces fix(versal-net): add missing curly braces fix(zynqmp): add missing curly braces
415 lines
7.4 KiB
C
415 lines
7.4 KiB
C
/*
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* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <string.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/smccc.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <plat_arm.h>
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#include <services/arm_arch_svc.h>
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#include <plat_ipi.h>
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#include <plat_private.h>
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#include <plat_startup.h>
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#include "zynqmp_pm_api_sys.h"
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/*
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* Table of regions to map using the MMU.
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* This doesn't include TZRAM as the 'mem_layout' argument passed to
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* configure_mmu_elx() will give the available subset of that,
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*/
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const mmap_region_t plat_zynqmp_mmap[] = {
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MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(CRF_APB_BASE, CRF_APB_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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{0}
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};
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const mmap_region_t *plat_get_mmap(void)
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{
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return plat_zynqmp_mmap;
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}
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static uint32_t zynqmp_get_silicon_ver(void)
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{
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static uint32_t ver;
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if (ver == 0U) {
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ver = mmio_read_32(ZYNQMP_CSU_BASEADDR +
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ZYNQMP_CSU_VERSION_OFFSET);
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ver &= ZYNQMP_SILICON_VER_MASK;
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ver >>= ZYNQMP_SILICON_VER_SHIFT;
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}
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return ver;
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}
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uint32_t get_uart_clk(void)
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{
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unsigned int ver = zynqmp_get_silicon_ver();
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uint32_t uart_clk = 0U;
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if (ver == ZYNQMP_CSU_VERSION_QEMU) {
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uart_clk = 133000000U;
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} else {
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uart_clk = 100000000U;
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}
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return uart_clk;
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}
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#if LOG_LEVEL >= LOG_LEVEL_NOTICE
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static const struct {
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uint8_t id;
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bool evexists;
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uint16_t ver;
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char *name;
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} __packed zynqmp_devices[] = {
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{
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.id = 0x10,
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.name = "XCZU3EG",
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},
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{
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.id = 0x10,
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.ver = 0x2c,
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.name = "XCZU3CG",
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},
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{
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.id = 0x11,
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.name = "XCZU2EG",
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},
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{
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.id = 0x11,
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.ver = 0x2c,
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.name = "XCZU2CG",
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},
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{
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.id = 0x20,
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.name = "XCZU5EV",
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.evexists = true,
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},
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{
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.id = 0x20,
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.ver = 0x100,
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.name = "XCZU5EG",
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.evexists = true,
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},
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{
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.id = 0x20,
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.ver = 0x12c,
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.name = "XCZU5CG",
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},
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{
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.id = 0x21,
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.name = "XCZU4EV",
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.evexists = true,
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},
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{
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.id = 0x21,
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.ver = 0x100,
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.name = "XCZU4EG",
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.evexists = true,
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},
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{
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.id = 0x21,
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.ver = 0x12c,
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.name = "XCZU4CG",
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},
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{
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.id = 0x30,
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.name = "XCZU7EV",
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.evexists = true,
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},
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{
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.id = 0x30,
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.ver = 0x100,
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.name = "XCZU7EG",
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.evexists = true,
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},
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{
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.id = 0x30,
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.ver = 0x12c,
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.name = "XCZU7CG",
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},
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{
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.id = 0x38,
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.name = "XCZU9EG",
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},
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{
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.id = 0x38,
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.ver = 0x2c,
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.name = "XCZU9CG",
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},
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{
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.id = 0x39,
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.name = "XCZU6EG",
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},
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{
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.id = 0x39,
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.ver = 0x2c,
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.name = "XCZU6CG",
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},
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{
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.id = 0x40,
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.name = "XCZU11EG",
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},
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{
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.id = 0x50,
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.name = "XCZU15EG",
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},
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{
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.id = 0x58,
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.name = "XCZU19EG",
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},
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{
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.id = 0x59,
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.name = "XCZU17EG",
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},
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{
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.id = 0x60,
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.name = "XCZU28DR",
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},
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{
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.id = 0x61,
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.name = "XCZU21DR",
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},
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{
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.id = 0x62,
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.name = "XCZU29DR",
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},
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{
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.id = 0x63,
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.name = "XCZU23DR",
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},
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{
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.id = 0x64,
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.name = "XCZU27DR",
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},
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{
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.id = 0x65,
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.name = "XCZU25DR",
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},
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{
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.id = 0x66,
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.name = "XCZU39DR",
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},
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{
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.id = 0x7d,
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.name = "XCZU43DR",
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},
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{
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.id = 0x78,
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.name = "XCZU46DR",
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},
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{
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.id = 0x7f,
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.name = "XCZU47DR",
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},
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{
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.id = 0x7b,
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.name = "XCZU48DR",
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},
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{
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.id = 0x7e,
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.name = "XCZU49DR",
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},
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};
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#define ZYNQMP_PL_STATUS_BIT 9
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#define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
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#define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
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#define SILICON_ID_XCK24 0x4712093U
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#define SILICON_ID_XCK26 0x4724093U
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static char *zynqmp_get_silicon_idcode_name(void)
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{
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uint32_t id, ver, chipid[2];
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size_t i, j, len;
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const char *name = "EG/EV";
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if (pm_get_chipid(chipid) != PM_RET_SUCCESS) {
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return "XCZUUNKN";
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}
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id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
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ZYNQMP_CSU_IDCODE_SVD_MASK);
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id >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
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ver = chipid[1] >> ZYNQMP_EFUSE_IPDISABLE_SHIFT;
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for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
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if ((zynqmp_devices[i].id == id) &&
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(zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK))) {
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break;
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}
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}
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if (i >= ARRAY_SIZE(zynqmp_devices)) {
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switch (chipid[0]) {
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case SILICON_ID_XCK24:
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return "XCK24";
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case SILICON_ID_XCK26:
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return "XCK26";
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default:
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return "XCZUUNKN";
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}
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}
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if (!zynqmp_devices[i].evexists) {
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return zynqmp_devices[i].name;
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}
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if ((ver & ZYNQMP_PL_STATUS_MASK) != 0U) {
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return zynqmp_devices[i].name;
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}
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len = strlen(zynqmp_devices[i].name) - 2U;
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for (j = 0; j < strlen(name); j++) {
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zynqmp_devices[i].name[len] = name[j];
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len++;
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}
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zynqmp_devices[i].name[len] = '\0';
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return zynqmp_devices[i].name;
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}
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static unsigned int zynqmp_get_rtl_ver(void)
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{
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uint32_t ver;
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ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);
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ver &= ZYNQMP_RTL_VER_MASK;
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ver >>= ZYNQMP_RTL_VER_SHIFT;
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return ver;
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}
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static char *zynqmp_print_silicon_idcode(void)
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{
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uint32_t id, maskid, tmp;
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id = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
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tmp = id;
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tmp &= ZYNQMP_CSU_IDCODE_XILINX_ID_MASK |
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ZYNQMP_CSU_IDCODE_FAMILY_MASK;
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maskid = (ZYNQMP_CSU_IDCODE_XILINX_ID << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) |
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(ZYNQMP_CSU_IDCODE_FAMILY << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT);
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if (tmp != maskid) {
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ERROR("Incorrect IDCODE 0x%x, maskid 0x%x\n", id, maskid);
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return "UNKN";
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}
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VERBOSE("IDCODE 0x%x\n", id);
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return zynqmp_get_silicon_idcode_name();
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}
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int32_t plat_is_smccc_feature_available(u_register_t fid)
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{
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int32_t ret = SMC_ARCH_CALL_NOT_SUPPORTED;
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switch (fid) {
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case SMCCC_ARCH_SOC_ID:
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ret = SMC_ARCH_CALL_SUCCESS;
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break;
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default:
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break;
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}
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return ret;
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}
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int32_t plat_get_soc_version(void)
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{
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uint32_t chip_id = zynqmp_get_silicon_ver();
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uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_XILINX_BKID, JEDEC_XILINX_MFID);
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uint32_t result = (manfid | (chip_id & 0xFFFFU));
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return (int32_t)result;
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}
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int32_t plat_get_soc_revision(void)
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{
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return (int32_t)mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
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}
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static uint32_t zynqmp_get_ps_ver(void)
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{
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uint32_t ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);
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ver &= ZYNQMP_PS_VER_MASK;
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ver >>= ZYNQMP_PS_VER_SHIFT;
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return ver + 1U;
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}
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static void zynqmp_print_platform_name(void)
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{
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uint32_t ver = zynqmp_get_silicon_ver();
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uint32_t rtl = zynqmp_get_rtl_ver();
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const char *label = "Unknown";
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switch (ver) {
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case ZYNQMP_CSU_VERSION_QEMU:
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label = "QEMU";
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break;
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case ZYNQMP_CSU_VERSION_SILICON:
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label = "silicon";
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break;
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default:
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/* Do nothing in default case */
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break;
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}
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VERBOSE("TF-A running on %s/%s at 0x%x\n",
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zynqmp_print_silicon_idcode(), label, BL31_BASE);
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VERBOSE("TF-A running on v%d/RTL%d.%d\n",
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zynqmp_get_ps_ver(), (rtl & 0xf0U) >> 4U, rtl & 0xfU);
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}
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#else
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static inline void zynqmp_print_platform_name(void) { }
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#endif
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uint32_t zynqmp_get_bootmode(void)
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{
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uint32_t r;
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enum pm_ret_status ret;
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ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r);
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if (ret != PM_RET_SUCCESS) {
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r = mmio_read_32(CRL_APB_BOOT_MODE_USER);
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}
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return r & CRL_APB_BOOT_MODE_MASK;
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}
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void zynqmp_config_setup(void)
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{
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/* Configure IPI data for ZynqMP */
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zynqmp_ipi_config_table_init();
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zynqmp_print_platform_name();
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}
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uint32_t plat_get_syscnt_freq2(void)
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{
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uint32_t ver = zynqmp_get_silicon_ver();
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uint32_t ret = 0U;
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if (ver == ZYNQMP_CSU_VERSION_QEMU) {
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ret = 65000000U;
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} else {
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ret = mmio_read_32((uint64_t)IOU_SCNTRS_BASEFREQ);
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}
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return ret;
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}
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