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9f7bab42a1
We now have code to detect the CPU topology at runtime, and can also populate the CPU nodes in a devicetree accordingly. This is used by the ARM FPGA port, for instance. But also a GICv3 compatible interrupt controller provides MMIO frames per core, so the size of this region needs to be adjusted in the DT, to match the number of cores as well. Provide a generic function to find the GICv3 interrupt controller in the DT, then adjust the "reg" entry to match the number of detected cores. Since the size of the GICR frame per cores differs between GICv4 and GICv3, this size is supplied as a parameter to the function. The caller should determine the applicable value by either hardcoding it or by observing GICR_TYPER.VLPIS. Change-Id: Ic2a6445c2c5381a36bf24263f52fcbefad378c05 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
19 lines
578 B
C
19 lines
578 B
C
/*
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FDT_FIXUP_H
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#define FDT_FIXUP_H
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int dt_add_psci_node(void *fdt);
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int dt_add_psci_cpu_enable_methods(void *fdt);
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int fdt_add_reserved_memory(void *dtb, const char *node_name,
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uintptr_t base, size_t size);
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int fdt_add_cpus_node(void *dtb, unsigned int afflv0,
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unsigned int afflv1, unsigned int afflv2);
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int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores,
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unsigned int gicr_frame_size);
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#endif /* FDT_FIXUP_H */
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