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https://github.com/ARM-software/arm-trusted-firmware.git
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18e279ebe6
This patch does the required changes to enable CSS platforms to build and use the SDS framework. Since SDS is always coupled with SCMI protocol, the preexisting SCMI build flag is now renamed to `CSS_USE_SCMI_SDS_DRIVER` which will enable both SCMI and SDS on CSS platforms. Also some of the workarounds applied for SCMI are now removed with SDS in place. Change-Id: I94e8b93f05e3fe95e475c5501c25bec052588a9c Signed-off-by: Soby Mathew <soby.mathew@arm.com>
101 lines
3 KiB
ArmAsm
101 lines
3 KiB
ArmAsm
/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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#include <css_def.h>
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.weak plat_secondary_cold_boot_setup
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.weak plat_get_my_entrypoint
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.globl css_calc_core_pos_swap_cluster
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.weak plat_is_my_cpu_primary
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/* ---------------------------------------------------------------------
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* void plat_secondary_cold_boot_setup(void);
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* In the normal boot flow, cold-booting secondary
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* CPUs is not yet implemented and they panic.
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* ---------------------------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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/* TODO: Implement secondary CPU cold boot setup on CSS platforms */
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cb_panic:
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b cb_panic
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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* uintptr_t plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and a warm
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* boot. On CSS platforms, this distinction is based on the contents of
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* the Trusted Mailbox. It is initialised to zero by the SCP before the
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* AP cores are released from reset. Therefore, a zero mailbox means
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* it's a cold reset.
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*
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* This functions returns the contents of the mailbox, i.e.:
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* - 0 for a cold boot;
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* - the warm boot entrypoint for a warm boot.
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE
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ldr r0, [r0]
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bx lr
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------------
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* unsigned int css_calc_core_pos_swap_cluster(u_register_t mpidr)
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* Utility function to calculate the core position by
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* swapping the cluster order. This is necessary in order to
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* match the format of the boot information passed by the SCP
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* and read in plat_is_my_cpu_primary below.
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* -----------------------------------------------------------
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*/
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func css_calc_core_pos_swap_cluster
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and r1, r0, #MPIDR_CPU_MASK
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and r0, r0, #MPIDR_CLUSTER_MASK
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eor r0, r0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
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add r0, r1, r0, LSR #6
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bx lr
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endfunc css_calc_core_pos_swap_cluster
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu (applicable ony after a cold boot)
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* -----------------------------------------------------
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*/
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#if CSS_USE_SCMI_SDS_DRIVER
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func plat_is_my_cpu_primary
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mov r10, lr
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bl plat_my_core_pos
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mov r4, r0
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bl sds_get_primary_cpu_id
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/* Check for error */
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mov r1, #0xffffffff
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cmp r0, r1
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beq 1f
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cmp r0, r4
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moveq r0, #1
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movne r0, #0
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bx r10
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1:
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no_ret plat_panic_handler
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endfunc plat_is_my_cpu_primary
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#else
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func plat_is_my_cpu_primary
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mov r10, lr
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bl plat_my_core_pos
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ldr r1, =SCP_BOOT_CFG_ADDR
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ldr r1, [r1]
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ubfx r1, r1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
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#PLAT_CSS_PRIMARY_CPU_BIT_WIDTH
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cmp r0, r1
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moveq r0, #1
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movne r0, #0
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bx r10
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endfunc plat_is_my_cpu_primary
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#endif
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