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86606eb51e
Platform may use specific cache line sizes. Since CACHE_WRITEBACK_GRANULE defines the platform specific cache line size, it is used to define the size of the cpu data structure CPU_DATA_SIZE aligned on cache line size. Introduce assembly macro 'mov_imm' for AArch32 to simplify implementation of function '_cpu_data_by_index'. Change-Id: Ic2d49ffe0c3e51649425fd9c8c99559c582ac5a1 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
42 lines
1.1 KiB
ArmAsm
42 lines
1.1 KiB
ArmAsm
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <cpu_data.h>
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.globl _cpu_data
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.globl _cpu_data_by_index
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/* -----------------------------------------------------------------
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* cpu_data_t *_cpu_data(void)
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*
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* Return the cpu_data structure for the current CPU.
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* -----------------------------------------------------------------
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*/
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func _cpu_data
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/* r12 is pushed to meet the 8 byte stack alignment requirement */
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push {r12, lr}
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bl plat_my_core_pos
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pop {r12, lr}
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b _cpu_data_by_index
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endfunc _cpu_data
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/* -----------------------------------------------------------------
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* cpu_data_t *_cpu_data_by_index(uint32_t cpu_index)
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*
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* Return the cpu_data structure for the CPU with given linear index
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*
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* This can be called without a valid stack.
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* clobbers: r0, r1
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* -----------------------------------------------------------------
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*/
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func _cpu_data_by_index
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mov_imm r1, CPU_DATA_SIZE
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mul r0, r0, r1
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ldr r1, =percpu_data
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add r0, r0, r1
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bx lr
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endfunc _cpu_data_by_index
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