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66b5620c87
Currently, the peripheral node indexes are incorrect
for Versal NET due to which incorrect node error is
generated and permission to set the device as wakeup
source is failed. Correct Versal NET peripheral node
indexes to fix above issue.
Fixes: 662aafd6475e ("feat(xilinx): add device node indexes")
Change-Id: I4a2d76f375645e13512599a0272d9322ff6fafd3
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
243 lines
7 KiB
C
243 lines
7 KiB
C
/*
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* Copyright (c) 2019, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* Versal PM nodes enums and defines */
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#ifndef PM_NODE_H
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#define PM_NODE_H
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/*********************************************************************
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* Macro definitions
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********************************************************************/
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#define NODE_CLASS_SHIFT 26U
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#define NODE_SUBCLASS_SHIFT 20U
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#define NODE_TYPE_SHIFT 14U
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#define NODE_INDEX_SHIFT 0U
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#define NODE_CLASS_MASK_BITS GENMASK_32(5, 0)
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#define NODE_SUBCLASS_MASK_BITS GENMASK_32(5, 0)
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#define NODE_TYPE_MASK_BITS GENMASK_32(5, 0)
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#define NODE_INDEX_MASK_BITS GENMASK_32(13, 0)
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#define NODE_CLASS_MASK (NODE_CLASS_MASK_BITS << NODE_CLASS_SHIFT)
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#define NODE_SUBCLASS_MASK (NODE_SUBCLASS_MASK_BITS << NODE_SUBCLASS_SHIFT)
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#define NODE_TYPE_MASK (NODE_TYPE_MASK_BITS << NODE_TYPE_SHIFT)
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#define NODE_INDEX_MASK (NODE_INDEX_MASK_BITS << NODE_INDEX_SHIFT)
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#define NODEID(CLASS, SUBCLASS, TYPE, INDEX) \
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((((CLASS) & NODE_CLASS_MASK_BITS) << NODE_CLASS_SHIFT) | \
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(((SUBCLASS) & NODE_SUBCLASS_MASK_BITS) << NODE_SUBCLASS_SHIFT) | \
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(((TYPE) & NODE_TYPE_MASK_BITS) << NODE_TYPE_SHIFT) | \
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(((INDEX) & NODE_INDEX_MASK_BITS) << NODE_INDEX_SHIFT))
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#define NODECLASS(ID) (((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT)
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#define NODESUBCLASS(ID) (((ID) & NODE_SUBCLASS_MASK) >> \
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NODE_SUBCLASS_SHIFT)
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#define NODETYPE(ID) (((ID) & NODE_TYPE_MASK) >> NODE_TYPE_SHIFT)
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#define NODEINDEX(ID) (((ID) & NODE_INDEX_MASK) >> NODE_INDEX_SHIFT)
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/*********************************************************************
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* Enum definitions
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********************************************************************/
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/* Node class types */
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enum pm_node_class {
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XPM_NODECLASS_MIN,
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XPM_NODECLASS_POWER,
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XPM_NODECLASS_CLOCK,
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XPM_NODECLASS_RESET,
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XPM_NODECLASS_MEMIC,
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XPM_NODECLASS_STMIC,
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XPM_NODECLASS_DEVICE,
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XPM_NODECLASS_MAX
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};
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enum pm_device_node_subclass {
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/* Device types */
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XPM_NODESUBCL_DEV_CORE = 1,
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XPM_NODESUBCL_DEV_PERIPH,
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XPM_NODESUBCL_DEV_MEM,
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XPM_NODESUBCL_DEV_SOC,
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XPM_NODESUBCL_DEV_MEM_CTRLR,
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XPM_NODESUBCL_DEV_PHY,
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};
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enum pm_device_node_type {
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/* Device types */
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XPM_NODETYPE_DEV_CORE_PMC = 1,
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XPM_NODETYPE_DEV_CORE_PSM,
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XPM_NODETYPE_DEV_CORE_APU,
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XPM_NODETYPE_DEV_CORE_RPU,
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XPM_NODETYPE_DEV_OCM,
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XPM_NODETYPE_DEV_TCM,
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XPM_NODETYPE_DEV_L2CACHE,
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XPM_NODETYPE_DEV_DDR,
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XPM_NODETYPE_DEV_PERIPH,
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XPM_NODETYPE_DEV_SOC,
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XPM_NODETYPE_DEV_GT,
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};
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/* Device node Indexes */
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enum pm_device_node_idx {
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/* Device nodes */
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XPM_NODEIDX_DEV_MIN = 0x0,
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/* Processor devices */
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XPM_NODEIDX_DEV_PMC_PROC = 0x1,
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XPM_NODEIDX_DEV_PSM_PROC = 0x2,
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XPM_NODEIDX_DEV_ACPU_0 = 0x3,
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XPM_NODEIDX_DEV_ACPU_1 = 0x4,
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XPM_NODEIDX_DEV_RPU0_0 = 0x5,
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XPM_NODEIDX_DEV_RPU0_1 = 0x6,
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/* Memory devices */
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XPM_NODEIDX_DEV_OCM_0 = 0x7,
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XPM_NODEIDX_DEV_OCM_1 = 0x8,
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XPM_NODEIDX_DEV_OCM_2 = 0x9,
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XPM_NODEIDX_DEV_OCM_3 = 0xA,
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XPM_NODEIDX_DEV_TCM_0_A = 0xB,
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XPM_NODEIDX_DEV_TCM_0_B = 0xC,
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XPM_NODEIDX_DEV_TCM_1_A = 0xD,
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XPM_NODEIDX_DEV_TCM_1_B = 0xE,
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XPM_NODEIDX_DEV_L2_BANK_0 = 0xF,
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XPM_NODEIDX_DEV_DDR_0 = 0x10,
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XPM_NODEIDX_DEV_DDR_1 = 0x11,
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XPM_NODEIDX_DEV_DDR_2 = 0x12,
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XPM_NODEIDX_DEV_DDR_3 = 0x13,
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XPM_NODEIDX_DEV_DDR_4 = 0x14,
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XPM_NODEIDX_DEV_DDR_5 = 0x15,
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XPM_NODEIDX_DEV_DDR_6 = 0x16,
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XPM_NODEIDX_DEV_DDR_7 = 0x17,
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/* LPD Peripheral devices */
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XPM_NODEIDX_DEV_USB_0 = 0x18,
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XPM_NODEIDX_DEV_GEM_0 = 0x19,
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XPM_NODEIDX_DEV_GEM_1 = 0x1A,
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XPM_NODEIDX_DEV_SPI_0 = 0x1B,
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XPM_NODEIDX_DEV_SPI_1 = 0x1C,
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XPM_NODEIDX_DEV_I2C_0 = 0x1D,
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XPM_NODEIDX_DEV_I2C_1 = 0x1E,
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XPM_NODEIDX_DEV_CAN_FD_0 = 0x1F,
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XPM_NODEIDX_DEV_CAN_FD_1 = 0x20,
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XPM_NODEIDX_DEV_UART_0 = 0x21,
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XPM_NODEIDX_DEV_UART_1 = 0x22,
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XPM_NODEIDX_DEV_GPIO = 0x23,
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XPM_NODEIDX_DEV_TTC_0 = 0x24,
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XPM_NODEIDX_DEV_TTC_1 = 0x25,
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XPM_NODEIDX_DEV_TTC_2 = 0x26,
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XPM_NODEIDX_DEV_TTC_3 = 0x27,
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XPM_NODEIDX_DEV_SWDT_LPD = 0x28,
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/* FPD Peripheral devices */
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XPM_NODEIDX_DEV_SWDT_FPD = 0x29,
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/* PMC Peripheral devices */
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XPM_NODEIDX_DEV_OSPI = 0x2A,
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XPM_NODEIDX_DEV_QSPI = 0x2B,
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XPM_NODEIDX_DEV_GPIO_PMC = 0x2C,
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XPM_NODEIDX_DEV_I2C_PMC = 0x2D,
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XPM_NODEIDX_DEV_SDIO_0 = 0x2E,
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XPM_NODEIDX_DEV_SDIO_1 = 0x2F,
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XPM_NODEIDX_DEV_PL_0 = 0x30,
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XPM_NODEIDX_DEV_PL_1 = 0x31,
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XPM_NODEIDX_DEV_PL_2 = 0x32,
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XPM_NODEIDX_DEV_PL_3 = 0x33,
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XPM_NODEIDX_DEV_RTC = 0x34,
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XPM_NODEIDX_DEV_ADMA_0 = 0x35,
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XPM_NODEIDX_DEV_ADMA_1 = 0x36,
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XPM_NODEIDX_DEV_ADMA_2 = 0x37,
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XPM_NODEIDX_DEV_ADMA_3 = 0x38,
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XPM_NODEIDX_DEV_ADMA_4 = 0x39,
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XPM_NODEIDX_DEV_ADMA_5 = 0x3A,
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XPM_NODEIDX_DEV_ADMA_6 = 0x3B,
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XPM_NODEIDX_DEV_ADMA_7 = 0x3C,
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XPM_NODEIDX_DEV_IPI_0 = 0x3D,
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XPM_NODEIDX_DEV_IPI_1 = 0x3E,
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XPM_NODEIDX_DEV_IPI_2 = 0x3F,
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XPM_NODEIDX_DEV_IPI_3 = 0x40,
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XPM_NODEIDX_DEV_IPI_4 = 0x41,
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XPM_NODEIDX_DEV_IPI_5 = 0x42,
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XPM_NODEIDX_DEV_IPI_6 = 0x43,
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/* Entire SoC */
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XPM_NODEIDX_DEV_SOC = 0x44,
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/* DDR memory controllers */
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XPM_NODEIDX_DEV_DDRMC_0 = 0x45,
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XPM_NODEIDX_DEV_DDRMC_1 = 0x46,
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XPM_NODEIDX_DEV_DDRMC_2 = 0x47,
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XPM_NODEIDX_DEV_DDRMC_3 = 0x48,
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/* GT devices */
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XPM_NODEIDX_DEV_GT_0 = 0x49,
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XPM_NODEIDX_DEV_GT_1 = 0x4A,
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XPM_NODEIDX_DEV_GT_2 = 0x4B,
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XPM_NODEIDX_DEV_GT_3 = 0x4C,
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XPM_NODEIDX_DEV_GT_4 = 0x4D,
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XPM_NODEIDX_DEV_GT_5 = 0x4E,
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XPM_NODEIDX_DEV_GT_6 = 0x4F,
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XPM_NODEIDX_DEV_GT_7 = 0x50,
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XPM_NODEIDX_DEV_GT_8 = 0x51,
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XPM_NODEIDX_DEV_GT_9 = 0x52,
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XPM_NODEIDX_DEV_GT_10 = 0x53,
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#if defined(PLAT_versal_net)
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XPM_NODEIDX_DEV_ACPU_0_0 = 0xAF,
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XPM_NODEIDX_DEV_ACPU_0_1 = 0xB0,
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XPM_NODEIDX_DEV_ACPU_0_2 = 0xB1,
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XPM_NODEIDX_DEV_ACPU_0_3 = 0xB2,
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XPM_NODEIDX_DEV_ACPU_1_0 = 0xB3,
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XPM_NODEIDX_DEV_ACPU_1_1 = 0xB4,
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XPM_NODEIDX_DEV_ACPU_1_2 = 0xB5,
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XPM_NODEIDX_DEV_ACPU_1_3 = 0xB6,
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XPM_NODEIDX_DEV_ACPU_2_0 = 0xB7,
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XPM_NODEIDX_DEV_ACPU_2_1 = 0xB8,
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XPM_NODEIDX_DEV_ACPU_2_2 = 0xB9,
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XPM_NODEIDX_DEV_ACPU_2_3 = 0xBA,
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XPM_NODEIDX_DEV_ACPU_3_0 = 0xBB,
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XPM_NODEIDX_DEV_ACPU_3_1 = 0xBC,
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XPM_NODEIDX_DEV_ACPU_3_2 = 0xBD,
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XPM_NODEIDX_DEV_ACPU_3_3 = 0xBE,
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XPM_NODEIDX_DEV_RPU_A_0 = 0xBF,
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XPM_NODEIDX_DEV_RPU_A_1 = 0xC0,
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XPM_NODEIDX_DEV_RPU_B_0 = 0xC1,
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XPM_NODEIDX_DEV_RPU_B_1 = 0xC2,
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XPM_NODEIDX_DEV_OCM_0_0 = 0xC3,
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XPM_NODEIDX_DEV_OCM_0_1 = 0xC4,
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XPM_NODEIDX_DEV_OCM_0_2 = 0xC5,
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XPM_NODEIDX_DEV_OCM_0_3 = 0xC6,
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XPM_NODEIDX_DEV_OCM_1_0 = 0xC7,
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XPM_NODEIDX_DEV_OCM_1_1 = 0xC8,
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XPM_NODEIDX_DEV_OCM_1_2 = 0xC9,
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XPM_NODEIDX_DEV_OCM_1_3 = 0xCA,
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XPM_NODEIDX_DEV_TCM_A_0A = 0xCB,
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XPM_NODEIDX_DEV_TCM_A_0B = 0xCC,
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XPM_NODEIDX_DEV_TCM_A_0C = 0xCD,
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XPM_NODEIDX_DEV_TCM_A_1A = 0xCE,
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XPM_NODEIDX_DEV_TCM_A_1B = 0xCF,
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XPM_NODEIDX_DEV_TCM_A_1C = 0xD0,
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XPM_NODEIDX_DEV_TCM_B_0A = 0xD1,
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XPM_NODEIDX_DEV_TCM_B_0B = 0xD2,
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XPM_NODEIDX_DEV_TCM_B_0C = 0xD3,
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XPM_NODEIDX_DEV_TCM_B_1A = 0xD4,
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XPM_NODEIDX_DEV_TCM_B_1B = 0xD5,
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XPM_NODEIDX_DEV_TCM_B_1C = 0xD6,
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XPM_NODEIDX_DEV_USB_1 = 0xD7,
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XPM_NODEIDX_DEV_PMC_WWDT = 0xD8,
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XPM_NODEIDX_DEV_LPD_SWDT_0 = 0xD9,
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XPM_NODEIDX_DEV_LPD_SWDT_1 = 0xDA,
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XPM_NODEIDX_DEV_FPD_SWDT_0 = 0xDB,
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XPM_NODEIDX_DEV_FPD_SWDT_1 = 0xDC,
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XPM_NODEIDX_DEV_FPD_SWDT_2 = 0xDD,
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XPM_NODEIDX_DEV_FPD_SWDT_3 = 0xDE,
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#endif
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XPM_NODEIDX_DEV_MAX,
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};
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#endif /* PM_NODE_H */
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