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https://github.com/ARM-software/arm-trusted-firmware.git
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7931d3322d
This patch is used to enable platform enablement for Agilex5 SoC FPGA. New feature: 1. Added ATF->Zephyr boot option 2. Added xlat_v2 for MMU 3. Added ATF->Linux boot option 4. Added SMP support 5. Added HPS bridges support 6. Added EMULATOR support 7. Added DDR support 8. Added GICv3 Redistirbution init 9. Added SDMMC/NAND/Combo Phy support 10. Updated GIC as secure access 11. Added CCU driver support 12. Updated product name -> Agilex5 13. Updated register address based on y22ww52.2 RTL 14. Updated system counter freq to 400MHz Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009
99 lines
3.9 KiB
C
99 lines
3.9 KiB
C
/*
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* Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_NOC_H
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#define SOCFPGA_NOC_H
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/* Macros */
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#define SCR_AXI_AP_MASK BIT(24)
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#define SCR_FPGA2SOC_MASK BIT(16)
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#define SCR_MPU_MASK BIT(0)
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#define DISABLE_L4_FIREWALL (SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \
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| SCR_MPU_MASK)
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#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
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#define SOCFPGA_CCU_NOC(_ctrl, _dev) (SOCFPGA_CCU_NOC_REG_BASE \
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+ (SOCFPGA_CCU_NOC_##_ctrl##_##_dev))
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#define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \
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+ (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg))
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#define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \
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+ (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg))
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/* L3 Interconnect Register Map */
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#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000
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#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004
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#define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028
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#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030
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#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040
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#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044
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#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068
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#define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG4 0x007c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_PWRMGR 0x0080
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_RXECC 0x0084
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_TXECC 0x0088
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094
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/* CCU NOC Register Map */
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#define SOCFPGA_CCU_NOC_CPU0_RAM0 0x04688
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#define SOCFPGA_CCU_NOC_IOM_RAM0 0x18628
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#define SOCFPGA_CCU_NOC_ADMASK_P_MASK BIT(0)
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#define SOCFPGA_CCU_NOC_ADMASK_NS_MASK BIT(1)
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/* Function Definitions */
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void enable_ns_peripheral_access(void);
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void enable_ns_bridge_access(void);
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void enable_ns_ocram_access(void);
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void enable_ocram_firewall(void);
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#endif
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