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https://github.com/ARM-software/arm-trusted-firmware.git
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fcd41e8692
Add the basic support for i.MX8ULP. The i.MX 8ULP family of processors features NXP’s advanced implementation of the dual Arm Cortex-A35 cores alongside an Arm Cortex-M33. This combined architecture enables the device to run a rich operating system (such as Linux) on the Cortex-A35 core and an RTOS (such as FreeRTOS) on the Cortex-M33 core. It also includes a Cadence Tensilica Fusion DSP for low-power audio and a HiFi4 DSP for advanced audio and machine learning applications. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I12df622b95960bcdf7da52e4c66470a700690e36
104 lines
3.3 KiB
C
104 lines
3.3 KiB
C
/*
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* Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __IMX_SIP_SVC_H__
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#define __IMX_SIP_SVC_H__
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/* SMC function IDs for SiP Service queries */
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#define IMX_SIP_GPC 0xC2000000
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#define IMX_SIP_CPUFREQ 0xC2000001
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#define IMX_SIP_SET_CPUFREQ 0x00
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#define IMX_SIP_SRTC 0xC2000002
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#define IMX_SIP_SRTC_SET_TIME 0x00
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#define IMX_SIP_BUILDINFO 0xC2000003
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#define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00
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#define IMX_SIP_DDR_DVFS 0xc2000004
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#define IMX_SIP_SRC 0xC2000005
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#define IMX_SIP_SRC_SET_SECONDARY_BOOT 0x10
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#define IMX_SIP_SRC_IS_SECONDARY_BOOT 0x11
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#define IMX_SIP_GET_SOC_INFO 0xC2000006
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#define IMX_SIP_HAB 0xC2000007
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#define IMX_SIP_HAB_AUTH_IMG 0x00
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#define IMX_SIP_HAB_ENTRY 0x01
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#define IMX_SIP_HAB_EXIT 0x02
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#define IMX_SIP_HAB_REPORT_EVENT 0x03
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#define IMX_SIP_HAB_REPORT_STATUS 0x04
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#define IMX_SIP_HAB_FAILSAFE 0x05
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#define IMX_SIP_HAB_CHECK_TARGET 0x06
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#define IMX_SIP_HAB_GET_VERSION 0x07
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#define IMX_SIP_HAB_AUTH_IMG_NO_DCD 0x08
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#define IMX_SIP_WAKEUP_SRC 0xC2000009
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#define IMX_SIP_WAKEUP_SRC_SCU 0x1
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#define IMX_SIP_WAKEUP_SRC_IRQSTEER 0x2
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#define IMX_SIP_OTP_READ 0xC200000A
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#define IMX_SIP_OTP_WRITE 0xC200000B
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#define IMX_SIP_MISC_SET_TEMP 0xC200000C
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#define IMX_SIP_AARCH32 0xC20000FD
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int imx_kernel_entry_handler(uint32_t smc_fid, u_register_t x1,
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u_register_t x2, u_register_t x3,
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u_register_t x4);
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#define IMX_SIP_SCMI 0xC20000FE
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#if defined(PLAT_imx8mq)
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int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1,
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u_register_t x2, u_register_t x3);
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int imx_gpc_handler(uint32_t smc_fid, u_register_t x1,
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u_register_t x2, u_register_t x3);
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int dram_dvfs_handler(uint32_t smc_fid, void *handle,
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u_register_t x1, u_register_t x2, u_register_t x3);
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#endif
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#if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
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int dram_dvfs_handler(uint32_t smc_fid, void *handle,
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u_register_t x1, u_register_t x2, u_register_t x3);
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int imx_gpc_handler(uint32_t smc_fid, u_register_t x1,
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u_register_t x2, u_register_t x3);
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#endif
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#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq) || defined(PLAT_imx8mn) || \
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defined(PLAT_imx8mp)
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int imx_src_handler(uint32_t smc_fid, u_register_t x1,
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u_register_t x2, u_register_t x3, void *handle);
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#endif
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#if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
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int imx_hab_handler(uint32_t smc_fid, u_register_t x1,
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u_register_t x2, u_register_t x3, u_register_t x4);
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#endif
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#if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx))
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int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1,
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u_register_t x2, u_register_t x3);
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int imx_srtc_handler(uint32_t smc_fid, void *handle, u_register_t x1,
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u_register_t x2, u_register_t x3, u_register_t x4);
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int imx_wakeup_src_handler(uint32_t smc_fid, u_register_t x1,
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u_register_t x2, u_register_t x3);
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int imx_otp_handler(uint32_t smc_fid, void *handle,
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u_register_t x1, u_register_t x2);
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int imx_misc_set_temp_handler(uint32_t smc_fid, u_register_t x1,
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u_register_t x2, u_register_t x3,
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u_register_t x4);
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#endif
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uint64_t imx_buildinfo_handler(uint32_t smc_fid, u_register_t x1,
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u_register_t x2, u_register_t x3,
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u_register_t x4);
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int scmi_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3);
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#endif /* __IMX_SIP_SVC_H__ */
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