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https://github.com/ARM-software/arm-trusted-firmware.git
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fcd41e8692
Add the basic support for i.MX8ULP. The i.MX 8ULP family of processors features NXP’s advanced implementation of the dual Arm Cortex-A35 cores alongside an Arm Cortex-M33. This combined architecture enables the device to run a rich operating system (such as Linux) on the Cortex-A35 core and an RTOS (such as FreeRTOS) on the Cortex-M33 core. It also includes a Cadence Tensilica Fusion DSP for low-power audio and a HiFi4 DSP for advanced audio and machine learning applications. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I12df622b95960bcdf7da52e4c66470a700690e36
100 lines
2.6 KiB
C
100 lines
2.6 KiB
C
/*
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* Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <drivers/scmi-msg.h>
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#include <lib/pmf/pmf.h>
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#include <tools_share/uuid.h>
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#include <imx_sip_svc.h>
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static int32_t imx_sip_setup(void)
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{
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return 0;
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}
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static uintptr_t imx_sip_handler(unsigned int smc_fid,
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u_register_t x1,
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u_register_t x2,
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u_register_t x3,
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u_register_t x4,
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void *cookie,
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void *handle,
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u_register_t flags)
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{
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switch (smc_fid) {
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case IMX_SIP_AARCH32:
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SMC_RET1(handle, imx_kernel_entry_handler(smc_fid, x1, x2, x3, x4));
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break;
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#if defined(PLAT_imx8ulp)
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case IMX_SIP_SCMI:
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scmi_smt_fastcall_smc_entry(0);
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SMC_RET1(handle, 0);
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break;
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#endif
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#if defined(PLAT_imx8mq)
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case IMX_SIP_GET_SOC_INFO:
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SMC_RET1(handle, imx_soc_info_handler(smc_fid, x1, x2, x3));
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break;
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case IMX_SIP_GPC:
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SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3));
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break;
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case IMX_SIP_DDR_DVFS:
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return dram_dvfs_handler(smc_fid, handle, x1, x2, x3);
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#endif
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#if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
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case IMX_SIP_DDR_DVFS:
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return dram_dvfs_handler(smc_fid, handle, x1, x2, x3);
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case IMX_SIP_GPC:
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SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3));
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break;
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#endif
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#if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx))
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case IMX_SIP_SRTC:
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return imx_srtc_handler(smc_fid, handle, x1, x2, x3, x4);
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case IMX_SIP_CPUFREQ:
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SMC_RET1(handle, imx_cpufreq_handler(smc_fid, x1, x2, x3));
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break;
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case IMX_SIP_WAKEUP_SRC:
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SMC_RET1(handle, imx_wakeup_src_handler(smc_fid, x1, x2, x3));
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case IMX_SIP_OTP_READ:
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case IMX_SIP_OTP_WRITE:
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return imx_otp_handler(smc_fid, handle, x1, x2);
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case IMX_SIP_MISC_SET_TEMP:
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SMC_RET1(handle, imx_misc_set_temp_handler(smc_fid, x1, x2, x3, x4));
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#endif
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#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq) || defined(PLAT_imx8mn) || \
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defined(PLAT_imx8mp)
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case IMX_SIP_SRC:
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SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3, handle));
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break;
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#endif
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#if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
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case IMX_SIP_HAB:
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SMC_RET1(handle, imx_hab_handler(smc_fid, x1, x2, x3, x4));
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break;
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#endif
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case IMX_SIP_BUILDINFO:
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SMC_RET1(handle, imx_buildinfo_handler(smc_fid, x1, x2, x3, x4));
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default:
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WARN("Unimplemented i.MX SiP Service Call: 0x%x\n", smc_fid);
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SMC_RET1(handle, SMC_UNK);
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break;
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}
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}
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/* Define a runtime service descriptor for fast SMC calls */
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DECLARE_RT_SVC(
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imx_sip_svc,
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OEN_SIP_START,
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OEN_SIP_END,
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SMC_TYPE_FAST,
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imx_sip_setup,
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imx_sip_handler
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);
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