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https://github.com/ARM-software/arm-trusted-firmware.git
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fcd41e8692
Add the basic support for i.MX8ULP. The i.MX 8ULP family of processors features NXP’s advanced implementation of the dual Arm Cortex-A35 cores alongside an Arm Cortex-M33. This combined architecture enables the device to run a rich operating system (such as Linux) on the Cortex-A35 core and an RTOS (such as FreeRTOS) on the Cortex-M33 core. It also includes a Cadence Tensilica Fusion DSP for low-power audio and a HiFi4 DSP for advanced audio and machine learning applications. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I12df622b95960bcdf7da52e4c66470a700690e36
150 lines
3.7 KiB
ArmAsm
150 lines
3.7 KiB
ArmAsm
/*
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* Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <platform_def.h>
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#include <cortex_a35.h>
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_calc_core_pos
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.globl plat_reset_handler
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.globl plat_get_my_entrypoint
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.globl plat_secondary_cold_boot_setup
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl platform_mem_init
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.globl imx_mailbox_init
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/* --------------------------------------------------------------------
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* Helper macro that reads the part number of the current CPU and jumps
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* to the given label if it matches the CPU MIDR provided.
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*
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* Clobbers x0.
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* --------------------------------------------------------------------
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*/
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.macro jump_if_cpu_midr _cpu_midr, _label
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mrs x0, midr_el1
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ubfx x0, x0, MIDR_PN_SHIFT, #12
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cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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b.eq \_label
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.endm
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/* ----------------------------------------------
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* The mailbox_base is used to distinguish warm/cold
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* reset. The mailbox_base is in the data section, not
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* in .bss, this allows function to start using this
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* variable before the runtime memory is initialized.
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* ----------------------------------------------
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*/
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.section .data.mailbox_base
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.align 3
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mailbox_base: .quad 0x0
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/* ----------------------------------------------
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* unsigned int plat_is_my_cpu_primary(void);
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* This function checks if this is the primary CPU
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* ----------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CPU_MASK)
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cmp x0, #PLAT_PRIMARY_CPU
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cset x0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* ----------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This Function uses the plat_calc_core_pos()
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* to get the index of the calling CPU.
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* ----------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc plat_my_core_pos
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/*
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* unsigned int plat_calc_core_pos(uint64_t mpidr)
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* helper function to calculate the core position.
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* With this function.
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*/
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func plat_calc_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc plat_calc_core_pos
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/* ----------------------------------------------
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* function to handle platform specific reset.
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* ----------------------------------------------
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*/
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func plat_reset_handler
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#if defined(PLAT_imx8ulp)
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mrs x0, CORTEX_A35_CPUECTLR_EL1
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orr x0, x0, #(0x1 << 0)
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orr x0, x0, #(0x1 << 3)
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msr CORTEX_A35_CPUECTLR_EL1, x0
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mrs x0, CORTEX_A35_L2ECTLR_EL1
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orr x0, x0, #(0x1 << 0)
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msr CORTEX_A35_L2ECTLR_EL1, x0
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isb
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#endif
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/* enable EL2 cpuectlr RW access */
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mov x0, #0x73
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msr actlr_el3, x0
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msr actlr_el2, x0
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isb
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ret
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endfunc plat_reset_handler
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/* ---------------------------------------------
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* function to get the entrypoint.
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* ---------------------------------------------
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*/
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func plat_get_my_entrypoint
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adrp x1, mailbox_base
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ldr x0, [x1, :lo12:mailbox_base]
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ret
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endfunc plat_get_my_entrypoint
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func imx_mailbox_init
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adrp x1, mailbox_base
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str x0, [x1, :lo12:mailbox_base]
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ret
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endfunc imx_mailbox_init
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func plat_secondary_cold_boot_setup
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b .
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endfunc plat_secondary_cold_boot_setup
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func plat_crash_console_init
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mov x0, #1
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ret
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endfunc plat_crash_console_init
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func plat_crash_console_putc
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ret
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endfunc plat_crash_console_putc
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func plat_crash_console_flush
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mov x0, #0
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ret
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endfunc plat_crash_console_flush
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func platform_mem_init
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ret
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endfunc platform_mem_init
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