mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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b57e16a4f9
The AMU extension code was using its own feature detection routines. Replace them with the generic CPU feature handlers (defined in arch_features.h), which get updated to cover the v1p1 variant as well. Change-Id: I8540f1e745d7b02a25a6c6cdf2a39d6f5e21f2aa Signed-off-by: Andre Przywara <andre.przywara@arm.com>
395 lines
9 KiB
C
395 lines
9 KiB
C
/*
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* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <cdefs.h>
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#include <stdbool.h>
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#include "../amu_private.h"
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/el3_runtime/pubsub_events.h>
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#include <lib/extensions/amu.h>
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#include <plat/common/platform.h>
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struct amu_ctx {
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uint64_t group0_cnts[AMU_GROUP0_MAX_COUNTERS];
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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uint64_t group1_cnts[AMU_GROUP1_MAX_COUNTERS];
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#endif
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uint16_t group0_enable;
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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uint16_t group1_enable;
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#endif
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};
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static struct amu_ctx amu_ctxs_[PLATFORM_CORE_COUNT];
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CASSERT((sizeof(amu_ctxs_[0].group0_enable) * CHAR_BIT) <= AMU_GROUP0_MAX_COUNTERS,
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amu_ctx_group0_enable_cannot_represent_all_group0_counters);
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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CASSERT((sizeof(amu_ctxs_[0].group1_enable) * CHAR_BIT) <= AMU_GROUP1_MAX_COUNTERS,
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amu_ctx_group1_enable_cannot_represent_all_group1_counters);
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#endif
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static inline __unused void write_hcptr_tam(uint32_t value)
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{
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write_hcptr((read_hcptr() & ~TAM_BIT) |
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((value << TAM_SHIFT) & TAM_BIT));
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}
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static inline __unused void write_amcr_cg1rz(uint32_t value)
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{
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write_amcr((read_amcr() & ~AMCR_CG1RZ_BIT) |
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((value << AMCR_CG1RZ_SHIFT) & AMCR_CG1RZ_BIT));
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}
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static inline __unused uint32_t read_amcfgr_ncg(void)
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{
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return (read_amcfgr() >> AMCFGR_NCG_SHIFT) &
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AMCFGR_NCG_MASK;
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}
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static inline __unused uint32_t read_amcgcr_cg0nc(void)
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{
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return (read_amcgcr() >> AMCGCR_CG0NC_SHIFT) &
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AMCGCR_CG0NC_MASK;
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}
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static inline __unused uint32_t read_amcgcr_cg1nc(void)
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{
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return (read_amcgcr() >> AMCGCR_CG1NC_SHIFT) &
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AMCGCR_CG1NC_MASK;
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}
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static inline __unused uint32_t read_amcntenset0_px(void)
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{
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return (read_amcntenset0() >> AMCNTENSET0_Pn_SHIFT) &
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AMCNTENSET0_Pn_MASK;
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}
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static inline __unused uint32_t read_amcntenset1_px(void)
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{
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return (read_amcntenset1() >> AMCNTENSET1_Pn_SHIFT) &
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AMCNTENSET1_Pn_MASK;
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}
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static inline __unused void write_amcntenset0_px(uint32_t px)
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{
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uint32_t value = read_amcntenset0();
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value &= ~AMCNTENSET0_Pn_MASK;
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value |= (px << AMCNTENSET0_Pn_SHIFT) &
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AMCNTENSET0_Pn_MASK;
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write_amcntenset0(value);
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}
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static inline __unused void write_amcntenset1_px(uint32_t px)
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{
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uint32_t value = read_amcntenset1();
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value &= ~AMCNTENSET1_Pn_MASK;
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value |= (px << AMCNTENSET1_Pn_SHIFT) &
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AMCNTENSET1_Pn_MASK;
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write_amcntenset1(value);
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}
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static inline __unused void write_amcntenclr0_px(uint32_t px)
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{
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uint32_t value = read_amcntenclr0();
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value &= ~AMCNTENCLR0_Pn_MASK;
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value |= (px << AMCNTENCLR0_Pn_SHIFT) & AMCNTENCLR0_Pn_MASK;
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write_amcntenclr0(value);
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}
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static inline __unused void write_amcntenclr1_px(uint32_t px)
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{
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uint32_t value = read_amcntenclr1();
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value &= ~AMCNTENCLR1_Pn_MASK;
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value |= (px << AMCNTENCLR1_Pn_SHIFT) & AMCNTENCLR1_Pn_MASK;
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write_amcntenclr1(value);
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}
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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static __unused bool amu_group1_supported(void)
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{
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return read_amcfgr_ncg() > 0U;
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}
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#endif
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/*
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* Enable counters. This function is meant to be invoked by the context
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* management library before exiting from EL3.
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*/
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void amu_enable(bool el2_unused)
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{
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uint32_t amcfgr_ncg; /* Number of counter groups */
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uint32_t amcgcr_cg0nc; /* Number of group 0 counters */
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uint32_t amcntenset0_px = 0x0; /* Group 0 enable mask */
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uint32_t amcntenset1_px = 0x0; /* Group 1 enable mask */
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if (el2_unused) {
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/*
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* HCPTR.TAM: Set to zero so any accesses to the Activity
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* Monitor registers do not trap to EL2.
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*/
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write_hcptr_tam(0U);
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}
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/*
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* Retrieve the number of architected counters. All of these counters
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* are enabled by default.
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*/
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amcgcr_cg0nc = read_amcgcr_cg0nc();
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amcntenset0_px = (UINT32_C(1) << (amcgcr_cg0nc)) - 1U;
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assert(amcgcr_cg0nc <= AMU_AMCGCR_CG0NC_MAX);
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/*
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* The platform may opt to enable specific auxiliary counters. This can
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* be done via the common FCONF getter, or via the platform-implemented
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* function.
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*/
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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const struct amu_topology *topology;
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#if ENABLE_AMU_FCONF
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topology = FCONF_GET_PROPERTY(amu, config, topology);
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#else
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topology = plat_amu_topology();
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#endif /* ENABLE_AMU_FCONF */
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if (topology != NULL) {
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unsigned int core_pos = plat_my_core_pos();
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amcntenset1_el0_px = topology->cores[core_pos].enable;
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} else {
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ERROR("AMU: failed to generate AMU topology\n");
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}
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#endif /* ENABLE_AMU_AUXILIARY_COUNTERS */
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/*
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* Enable the requested counters.
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*/
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write_amcntenset0_px(amcntenset0_px);
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amcfgr_ncg = read_amcfgr_ncg();
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if (amcfgr_ncg > 0U) {
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write_amcntenset1_px(amcntenset1_px);
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#if !ENABLE_AMU_AUXILIARY_COUNTERS
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VERBOSE("AMU: auxiliary counters detected but support is disabled\n");
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#endif
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}
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/* Bail out if FEAT_AMUv1p1 features are not present. */
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if (!is_feat_amuv1p1_supported()) {
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return;
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}
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#if AMU_RESTRICT_COUNTERS
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/*
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* FEAT_AMUv1p1 adds a register field to restrict access to group 1
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* counters at all but the highest implemented EL. This is controlled
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* with the AMU_RESTRICT_COUNTERS compile time flag, when set, system
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* register reads at lower ELs return zero. Reads from the memory
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* mapped view are unaffected.
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*/
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VERBOSE("AMU group 1 counter access restricted.\n");
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write_amcr_cg1rz(1U);
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#else
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write_amcr_cg1rz(0U);
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#endif
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}
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/* Read the group 0 counter identified by the given `idx`. */
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static uint64_t amu_group0_cnt_read(unsigned int idx)
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{
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assert(is_feat_amu_supported());
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assert(idx < read_amcgcr_cg0nc());
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return amu_group0_cnt_read_internal(idx);
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}
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/* Write the group 0 counter identified by the given `idx` with `val` */
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static void amu_group0_cnt_write(unsigned int idx, uint64_t val)
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{
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assert(is_feat_amu_supported());
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assert(idx < read_amcgcr_cg0nc());
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amu_group0_cnt_write_internal(idx, val);
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isb();
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}
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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/* Read the group 1 counter identified by the given `idx` */
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static uint64_t amu_group1_cnt_read(unsigned int idx)
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{
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assert(is_feat_amu_supported());
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assert(amu_group1_supported());
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assert(idx < read_amcgcr_cg1nc());
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return amu_group1_cnt_read_internal(idx);
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}
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/* Write the group 1 counter identified by the given `idx` with `val` */
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static void amu_group1_cnt_write(unsigned int idx, uint64_t val)
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{
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assert(is_feat_amu_supported());
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assert(amu_group1_supported());
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assert(idx < read_amcgcr_cg1nc());
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amu_group1_cnt_write_internal(idx, val);
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isb();
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}
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#endif
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static void *amu_context_save(const void *arg)
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{
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uint32_t i;
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unsigned int core_pos;
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struct amu_ctx *ctx;
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uint32_t amcgcr_cg0nc; /* Number of group 0 counters */
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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uint32_t amcfgr_ncg; /* Number of counter groups */
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uint32_t amcgcr_cg1nc; /* Number of group 1 counters */
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#endif
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if (!is_feat_amu_supported()) {
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return (void *)0;
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}
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core_pos = plat_my_core_pos();
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ctx = &amu_ctxs_[core_pos];
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amcgcr_cg0nc = read_amcgcr_cg0nc();
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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amcfgr_ncg = read_amcfgr_ncg();
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amcgcr_cg1nc = (amcfgr_ncg > 0U) ? read_amcgcr_cg1nc() : 0U;
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#endif
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/*
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* Disable all AMU counters.
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*/
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ctx->group0_enable = read_amcntenset0_px();
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write_amcntenclr0_px(ctx->group0_enable);
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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if (amcfgr_ncg > 0U) {
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ctx->group1_enable = read_amcntenset1_px();
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write_amcntenclr1_px(ctx->group1_enable);
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}
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#endif
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/*
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* Save the counters to the local context.
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*/
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isb(); /* Ensure counters have been stopped */
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for (i = 0U; i < amcgcr_cg0nc; i++) {
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ctx->group0_cnts[i] = amu_group0_cnt_read(i);
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}
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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for (i = 0U; i < amcgcr_cg1nc; i++) {
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ctx->group1_cnts[i] = amu_group1_cnt_read(i);
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}
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#endif
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return (void *)0;
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}
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static void *amu_context_restore(const void *arg)
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{
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uint32_t i;
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unsigned int core_pos;
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struct amu_ctx *ctx;
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uint32_t amcfgr_ncg; /* Number of counter groups */
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uint32_t amcgcr_cg0nc; /* Number of group 0 counters */
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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uint32_t amcgcr_cg1nc; /* Number of group 1 counters */
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#endif
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if (!is_feat_amu_supported()) {
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return (void *)0;
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}
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core_pos = plat_my_core_pos();
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ctx = &amu_ctxs_[core_pos];
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amcfgr_ncg = read_amcfgr_ncg();
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amcgcr_cg0nc = read_amcgcr_cg0nc();
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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amcgcr_cg1nc = (amcfgr_ncg > 0U) ? read_amcgcr_cg1nc() : 0U;
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#endif
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/*
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* Sanity check that all counters were disabled when the context was
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* previously saved.
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*/
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assert(read_amcntenset0_px() == 0U);
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if (amcfgr_ncg > 0U) {
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assert(read_amcntenset1_px() == 0U);
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}
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/*
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* Restore the counter values from the local context.
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*/
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for (i = 0U; i < amcgcr_cg0nc; i++) {
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amu_group0_cnt_write(i, ctx->group0_cnts[i]);
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}
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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for (i = 0U; i < amcgcr_cg1nc; i++) {
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amu_group1_cnt_write(i, ctx->group1_cnts[i]);
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}
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#endif
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/*
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* Re-enable counters that were disabled during context save.
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*/
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write_amcntenset0_px(ctx->group0_enable);
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#if ENABLE_AMU_AUXILIARY_COUNTERS
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if (amcfgr_ncg > 0U) {
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write_amcntenset1_px(ctx->group1_enable);
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}
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#endif
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return (void *)0;
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}
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SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, amu_context_save);
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SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, amu_context_restore);
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