Sona Mathew ab062f0510 fix(cpus): workaround platforms non-arm interconnect ... The workarounds for these below mentioned errata are not implemented in EL3, but the flags can be enabled/disabled at a platform level based on arm/non-arm interconnect IP. The ABI helps assist the Kernel in the process of mitigation for the following errata: Cortex-A715: erratum 2701951 Neoverse V2: erratum 2719103 Cortex-A710: erratum 2701952 Cortex-X2: erratum 2701952 Neoverse N2: erratum 2728475 Neoverse V1: erratum 2701953 Cortex-A78: erratum 2712571 Cortex-A78AE: erratum 2712574 Cortex-A78C: erratum 2712575 EL3 provides an appropriate return value via errata ABI when the kernel makes an SMC call using the EM_CPU_ERRATUM_FEATURES FID with the appropriate erratum ID. Change-Id: I35bd69d812dba37410dd8bc2bbde20d4955b0850 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>		2023-05-05 13:23:10 -05:00
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aarch32	refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3	2023-03-15 11:43:14 +00:00
aarch64	build(psci): move runtime_errata.S to PSCI	2023-05-03 15:36:08 +02:00
cpu-ops.mk	fix(cpus): workaround platforms non-arm interconnect	2023-05-05 13:23:10 -05:00
errata_report.c	refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3	2023-03-15 11:43:14 +00:00