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fcb72e16ce
Add symbols for mapping the physical memory layout of BL32. There are symbols that partially satisfy this requirement, however, the naming of these is inconsistent. Signed-off-by: Harrison Mutai <harrison.mutai@arm.com> Change-Id: I106187f93b227d604bda650892f9e919047b3fc7
155 lines
3.7 KiB
ArmAsm
155 lines
3.7 KiB
ArmAsm
/*
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* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/bl_common.ld.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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OUTPUT_FORMAT(elf32-littlearm)
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OUTPUT_ARCH(arm)
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ENTRY(sp_min_vector_table)
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MEMORY {
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RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE
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}
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#ifdef PLAT_SP_MIN_EXTRA_LD_SCRIPT
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# include <plat_sp_min.ld.S>
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#endif /* PLAT_SP_MIN_EXTRA_LD_SCRIPT */
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SECTIONS {
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RAM_REGION_START = ORIGIN(RAM);
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RAM_REGION_LENGTH = LENGTH(RAM);
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. = BL32_BASE;
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ASSERT(. == ALIGN(PAGE_SIZE),
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"BL32_BASE address is not aligned on a page boundary.")
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#if SEPARATE_CODE_AND_RODATA
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.text . : {
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__TEXT_START__ = .;
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*entrypoint.o(.text*)
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*(SORT_BY_ALIGNMENT(.text*))
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*(.vectors)
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. = ALIGN(PAGE_SIZE);
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__TEXT_END__ = .;
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} >RAM
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/* .ARM.extab and .ARM.exidx are only added because Clang needs them */
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.ARM.extab . : {
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} >RAM
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.ARM.exidx . : {
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} >RAM
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.rodata . : {
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__RODATA_START__ = .;
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*(SORT_BY_ALIGNMENT(.rodata*))
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RODATA_COMMON
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. = ALIGN(8);
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# include <lib/el3_runtime/pubsub_events.h>
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. = ALIGN(PAGE_SIZE);
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__RODATA_END__ = .;
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} >RAM
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#else /* SEPARATE_CODE_AND_RODATA */
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.ro . : {
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__RO_START__ = .;
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*entrypoint.o(.text*)
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*(SORT_BY_ALIGNMENT(.text*))
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*(SORT_BY_ALIGNMENT(.rodata*))
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RODATA_COMMON
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. = ALIGN(8);
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# include <lib/el3_runtime/pubsub_events.h>
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*(.vectors)
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__RO_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked as device
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* memory. No other unexpected data must creep in. Ensure that the rest
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* of the current memory page is unused.
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*/
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. = ALIGN(PAGE_SIZE);
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__RO_END__ = .;
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} >RAM
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#endif /* SEPARATE_CODE_AND_RODATA */
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ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
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"cpu_ops not defined for this platform.")
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__RW_START__ = .;
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DATA_SECTION >RAM
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RELA_SECTION >RAM
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#ifdef BL32_PROGBITS_LIMIT
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ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.")
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#endif /* BL32_PROGBITS_LIMIT */
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STACK_SECTION >RAM
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BSS_SECTION >RAM
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XLAT_TABLE_SECTION >RAM
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__BSS_SIZE__ = SIZEOF(.bss);
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#if USE_COHERENT_MEM
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/*
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* The base address of the coherent memory section must be page-aligned to
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* guarantee that the coherent data are stored on their own pages and are
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* not mixed with normal data. This is required to set up the correct
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* memory attributes for the coherent data page tables.
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*/
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.coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
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__COHERENT_RAM_START__ = .;
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/*
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* Bakery locks are stored in coherent memory. Each lock's data is
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* contiguous and fully allocated by the compiler.
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*/
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*(.bakery_lock)
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*(.tzfw_coherent_mem)
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__COHERENT_RAM_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked as device
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* memory. No other unexpected data must creep in. Ensure that the rest
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* of the current memory page is unused.
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*/
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. = ALIGN(PAGE_SIZE);
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__COHERENT_RAM_END__ = .;
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} >RAM
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__COHERENT_RAM_UNALIGNED_SIZE__ =
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__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
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#endif /* USE_COHERENT_MEM */
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__RW_END__ = .;
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__BL32_END__ = .;
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/DISCARD/ : {
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*(.dynsym .dynstr .hash .gnu.hash)
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}
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ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
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RAM_REGION_END = .;
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}
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