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https://github.com/ARM-software/arm-trusted-firmware.git
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fc7dca72ba
SPE and TRBE don't have an outright EL3 disable, there are only constraints on what's allowed. Since we only enable them for NS at the moment, we want NS to own the buffers even when the feature should be "disabled" for a world. This means that when we're running in NS everything is as normal but when running in S/RL then tracing is prohibited (since the buffers are owned by NS). This allows us to fiddle with context a bit more without having to context switch registers. Change-Id: Ie1dc7c00e4cf9bcc746f02ae43633acca32d3758 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
57 lines
1.6 KiB
C
57 lines
1.6 KiB
C
/*
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* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <lib/extensions/trbe.h>
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void trbe_enable(cpu_context_t *ctx)
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{
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el3_state_t *state = get_el3state_ctx(ctx);
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u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
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/*
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* MDCR_EL3.NSTBE = 0b0
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* Trace Buffer owning Security state is Non-secure state. If FEAT_RME
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* is not implemented, this field is RES0.
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*
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* MDCR_EL3.NSTB = 0b11
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* Allow access of trace buffer control registers from NS-EL1 and
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* NS-EL2, tracing is prohibited in Secure and Realm state (if
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* implemented).
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*/
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mdcr_el3_val |= MDCR_NSTB(MDCR_NSTB_EL1);
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mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
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write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
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}
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void trbe_disable(cpu_context_t *ctx)
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{
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el3_state_t *state = get_el3state_ctx(ctx);
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u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
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/*
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* MDCR_EL3.{NSTBE,NSTB} = 0b0, 0b10
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* Disable access of trace buffer control registers from lower ELs in
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* any security state. Non-secure owns the buffer.
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*/
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mdcr_el3_val &= ~(MDCR_NSTB(MDCR_NSTB_EL1));
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mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
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mdcr_el3_val |= MDCR_NSTB(MDCR_NSTB_EL3);
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write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
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}
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void trbe_init_el2_unused(void)
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{
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/*
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* MDCR_EL2.E2TB: Set to zero so that the trace Buffer
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* owning exception level is NS-EL1 and, tracing is
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* prohibited at NS-EL2. These bits are RES0 when
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* FEAT_TRBE is not implemented.
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*/
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write_mdcr_el2(read_mdcr_el2() & ~MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1));
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}
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