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https://github.com/ARM-software/arm-trusted-firmware.git
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fc7dca72ba
SPE and TRBE don't have an outright EL3 disable, there are only constraints on what's allowed. Since we only enable them for NS at the moment, we want NS to own the buffers even when the feature should be "disabled" for a world. This means that when we're running in NS everything is as normal but when running in S/RL then tracing is prohibited (since the buffers are owned by NS). This allows us to fiddle with context a bit more without having to context switch registers. Change-Id: Ie1dc7c00e4cf9bcc746f02ae43633acca32d3758 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
77 lines
2.3 KiB
C
77 lines
2.3 KiB
C
/*
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* Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <lib/extensions/spe.h>
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#include <plat/common/platform.h>
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void spe_enable(cpu_context_t *ctx)
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{
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el3_state_t *state = get_el3state_ctx(ctx);
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u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
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/*
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* MDCR_EL3.NSPB (ARM v8.2): SPE enabled in Non-secure state
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* and disabled in secure state. Accesses to SPE registers at
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* S-EL1 generate trap exceptions to EL3.
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*
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* MDCR_EL3.NSPBE: Profiling Buffer uses Non-secure Virtual Addresses.
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* When FEAT_RME is not implemented, this field is RES0.
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*
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* MDCR_EL3.EnPMSN (ARM v8.7): Do not trap access to PMSNEVFR_EL1
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* register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2 is implemented.
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* Setting this bit to 1 doesn't have any effect on it when
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* FEAT_SPEv1p2 not implemented.
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*/
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mdcr_el3_val |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT;
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mdcr_el3_val &= ~(MDCR_NSPBE_BIT);
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write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
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}
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void spe_disable(cpu_context_t *ctx)
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{
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el3_state_t *state = get_el3state_ctx(ctx);
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u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
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/*
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* MDCR_EL3.NSPB: set to 0x2. After, Non-Secure state owns
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* the Profiling Buffer and accesses to Statistical Profiling and Profiling
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* Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3.
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* Profiling is disabled in Secure and Realm states.
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*
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* MDCR_EL3.NSPBE: Don't care as it was cleared during spe_enable and setting
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* this to 1 does not make sense as NSPBE{1} and NSPB{0b0x} is RESERVED.
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*
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* MDCR_EL3.EnPMSN (ARM v8.7): Clear the bit to trap access of PMSNEVFR_EL1
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* from EL2/EL1 to EL3.
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*/
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mdcr_el3_val &= ~(MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT);
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mdcr_el3_val |= MDCR_NSPB(MDCR_NSPB_EL3);
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write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
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}
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void spe_init_el2_unused(void)
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{
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uint64_t v;
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/*
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* MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical
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* profiling controls to EL2.
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*
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* MDCR_EL2.E2PB (ARM v8.2): SPE enabled in Non-secure
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* state. Accesses to profiling buffer controls at
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* Non-secure EL1 are not trapped to EL2.
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*/
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v = read_mdcr_el2();
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v &= ~MDCR_EL2_TPMS;
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v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1);
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write_mdcr_el2(v);
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}
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