Bipin Ravi c1aa3fa555 fix(cpus): workaround for Cortex X3 erratum 2641945 ... Cortex X3 erratum 2641945 is a Cat B erratum that applies to all revisions <= r1p0 and is fixed in r1p1. The workaround is to disable the affected L1 data cache prefetcher by setting CPUACTLR6_EL1[41] to 1. Doing so will incur a performance penalty of ~1%. Contact Arm for an alternate workaround that impacts power. SDEN documentation: https://developer.arm.com/documentation/2055130/latest Change-Id: Ia6d6ac8a66936c63b8aa8d7698b937f42ba8f044 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>		2024-01-25 17:14:54 -06:00
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alt-boot-flows.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
auth-framework.rst	fix(docs): revise the description of REGISTER_CRYPTO_LIB	2023-11-29 14:39:31 +08:00
cpu-specific-build-macros.rst	fix(cpus): workaround for Cortex X3 erratum 2641945	2024-01-25 17:14:54 -06:00
firmware-design.rst	refactor(mte): deprecate CTX_INCLUDE_MTE_REGS	2024-01-23 11:58:55 -06:00
index.rst	docs: add top level section numbering	2022-11-16 14:06:48 +00:00
interrupt-framework-design.rst	Fix broken links to various sections across docs	2020-08-03 09:55:04 -05:00
psci-pd-tree.rst	doc: Set correct syntax highlighting style	2019-05-22 11:28:17 +01:00
reset-design.rst	docs: update RESET_TO_BL31 documentation	2023-03-09 14:42:49 +00:00
trusted-board-boot-build.rst	docs(arm): add ARM_ROTPK_LOCATION variant full key	2022-12-09 14:55:39 -06:00
trusted-board-boot.rst	feat(cert-create): add pkcs11 engine support	2023-09-21 13:27:25 +02:00