mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 17:44:19 +00:00
fb037bfb7c
Add tag names to all unnamed structs in header files. This allows forward declaration of structs, which is necessary to reduce header file nesting (to be implemented in a subsequent commit). Also change the typedef names across the codebase to use the _t suffix to be more conformant with the Linux coding style. The coding style actually prefers us not to use typedefs at all but this is considered a step too far for Trusted Firmware. Also change the IO framework structs defintions to use typedef'd structs to be consistent with the rest of the codebase. Change-Id: I722b2c86fc0d92e4da3b15e5cab20373dd26786f
488 lines
15 KiB
C
488 lines
15 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <assert.h>
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#include <bl31.h>
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#include <debug.h>
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#include <arch_helpers.h>
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#include <console.h>
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#include <platform.h>
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#include <psci.h>
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#include <context_mgmt.h>
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#include <runtime_svc.h>
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#include "psci_private.h"
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typedef int (*afflvl_on_handler_t)(unsigned long,
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aff_map_node_t *,
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unsigned long,
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unsigned long);
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/*******************************************************************************
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* This function checks whether a cpu which has been requested to be turned on
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* is OFF to begin with.
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******************************************************************************/
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static int cpu_on_validate_state(aff_map_node_t *node)
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{
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unsigned int psci_state;
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/* Get the raw psci state */
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psci_state = psci_get_state(node);
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if (psci_state == PSCI_STATE_ON || psci_state == PSCI_STATE_SUSPEND)
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return PSCI_E_ALREADY_ON;
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if (psci_state == PSCI_STATE_ON_PENDING)
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return PSCI_E_ON_PENDING;
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assert(psci_state == PSCI_STATE_OFF);
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Handler routine to turn a cpu on. It takes care of any generic, architectural
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* or platform specific setup required.
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* TODO: Split this code across separate handlers for each type of setup?
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******************************************************************************/
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static int psci_afflvl0_on(unsigned long target_cpu,
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aff_map_node_t *cpu_node,
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unsigned long ns_entrypoint,
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unsigned long context_id)
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{
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unsigned int index, plat_state;
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unsigned long psci_entrypoint;
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int rc;
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/* Sanity check to safeguard against data corruption */
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assert(cpu_node->level == MPIDR_AFFLVL0);
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/*
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* Generic management: Ensure that the cpu is off to be
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* turned on
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*/
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rc = cpu_on_validate_state(cpu_node);
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if (rc != PSCI_E_SUCCESS)
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return rc;
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/*
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* Call the cpu on handler registered by the Secure Payload Dispatcher
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* to let it do any bookeeping. If the handler encounters an error, it's
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* expected to assert within
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*/
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if (psci_spd_pm && psci_spd_pm->svc_on)
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psci_spd_pm->svc_on(target_cpu);
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/*
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* Arch. management: Derive the re-entry information for
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* the non-secure world from the non-secure state from
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* where this call originated.
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*/
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index = cpu_node->data;
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rc = psci_set_ns_entry_info(index, ns_entrypoint, context_id);
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if (rc != PSCI_E_SUCCESS)
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return rc;
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/* Set the secure world (EL3) re-entry point after BL1 */
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psci_entrypoint = (unsigned long) psci_aff_on_finish_entry;
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/* State management: Set this cpu's state as ON PENDING */
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psci_set_state(cpu_node, PSCI_STATE_ON_PENDING);
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/*
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* Plat. management: Give the platform the current state
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* of the target cpu to allow it to perform the necessary
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* steps to power on.
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*/
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if (psci_plat_pm_ops->affinst_on) {
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/* Get the current physical state of this cpu */
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plat_state = psci_get_phys_state(cpu_node);
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rc = psci_plat_pm_ops->affinst_on(target_cpu,
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psci_entrypoint,
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ns_entrypoint,
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cpu_node->level,
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plat_state);
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}
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return rc;
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}
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/*******************************************************************************
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* Handler routine to turn a cluster on. It takes care or any generic, arch.
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* or platform specific setup required.
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* TODO: Split this code across separate handlers for each type of setup?
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******************************************************************************/
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static int psci_afflvl1_on(unsigned long target_cpu,
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aff_map_node_t *cluster_node,
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unsigned long ns_entrypoint,
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unsigned long context_id)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned int plat_state;
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unsigned long psci_entrypoint;
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assert(cluster_node->level == MPIDR_AFFLVL1);
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/*
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* There is no generic and arch. specific cluster
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* management required
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*/
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/* State management: Is not required while turning a cluster on */
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/*
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* Plat. management: Give the platform the current state
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* of the target cpu to allow it to perform the necessary
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* steps to power on.
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*/
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if (psci_plat_pm_ops->affinst_on) {
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plat_state = psci_get_phys_state(cluster_node);
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psci_entrypoint = (unsigned long) psci_aff_on_finish_entry;
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rc = psci_plat_pm_ops->affinst_on(target_cpu,
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psci_entrypoint,
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ns_entrypoint,
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cluster_node->level,
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plat_state);
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}
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return rc;
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}
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/*******************************************************************************
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* Handler routine to turn a cluster of clusters on. It takes care or any
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* generic, arch. or platform specific setup required.
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* TODO: Split this code across separate handlers for each type of setup?
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******************************************************************************/
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static int psci_afflvl2_on(unsigned long target_cpu,
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aff_map_node_t *system_node,
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unsigned long ns_entrypoint,
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unsigned long context_id)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned int plat_state;
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unsigned long psci_entrypoint;
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/* Cannot go beyond affinity level 2 in this psci imp. */
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assert(system_node->level == MPIDR_AFFLVL2);
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/*
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* There is no generic and arch. specific system management
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* required
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*/
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/* State management: Is not required while turning a system on */
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/*
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* Plat. management: Give the platform the current state
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* of the target cpu to allow it to perform the necessary
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* steps to power on.
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*/
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if (psci_plat_pm_ops->affinst_on) {
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plat_state = psci_get_phys_state(system_node);
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psci_entrypoint = (unsigned long) psci_aff_on_finish_entry;
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rc = psci_plat_pm_ops->affinst_on(target_cpu,
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psci_entrypoint,
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ns_entrypoint,
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system_node->level,
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plat_state);
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}
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return rc;
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}
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/* Private data structure to make this handlers accessible through indexing */
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static const afflvl_on_handler_t psci_afflvl_on_handlers[] = {
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psci_afflvl0_on,
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psci_afflvl1_on,
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psci_afflvl2_on,
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};
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/*******************************************************************************
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* This function takes an array of pointers to affinity instance nodes in the
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* topology tree and calls the on handler for the corresponding affinity
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* levels
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******************************************************************************/
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static int psci_call_on_handlers(mpidr_aff_map_nodes_t target_cpu_nodes,
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int start_afflvl,
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int end_afflvl,
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unsigned long target_cpu,
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unsigned long entrypoint,
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unsigned long context_id)
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{
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int rc = PSCI_E_INVALID_PARAMS, level;
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aff_map_node_t *node;
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for (level = end_afflvl; level >= start_afflvl; level--) {
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node = target_cpu_nodes[level];
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if (node == NULL)
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continue;
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/*
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* TODO: In case of an error should there be a way
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* of undoing what we might have setup at higher
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* affinity levels.
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*/
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rc = psci_afflvl_on_handlers[level](target_cpu,
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node,
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entrypoint,
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context_id);
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if (rc != PSCI_E_SUCCESS)
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break;
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}
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return rc;
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}
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/*******************************************************************************
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* Generic handler which is called to physically power on a cpu identified by
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* its mpidr. It traverses through all the affinity levels performing generic,
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* architectural, platform setup and state management e.g. for a cpu that is
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* to be powered on, it will ensure that enough information is stashed for it
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* to resume execution in the non-secure security state.
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*
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* The state of all the relevant affinity levels is changed after calling the
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* affinity level specific handlers as their actions would depend upon the state
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* the affinity level is currently in.
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*
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* The affinity level specific handlers are called in descending order i.e. from
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* the highest to the lowest affinity level implemented by the platform because
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* to turn on affinity level X it is neccesary to turn on affinity level X + 1
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* first.
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******************************************************************************/
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int psci_afflvl_on(unsigned long target_cpu,
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unsigned long entrypoint,
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unsigned long context_id,
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int start_afflvl,
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int end_afflvl)
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{
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int rc = PSCI_E_SUCCESS;
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mpidr_aff_map_nodes_t target_cpu_nodes;
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unsigned long mpidr = read_mpidr() & MPIDR_AFFINITY_MASK;
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/*
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* Collect the pointers to the nodes in the topology tree for
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* each affinity instance in the mpidr. If this function does
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* not return successfully then either the mpidr or the affinity
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* levels are incorrect.
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*/
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rc = psci_get_aff_map_nodes(target_cpu,
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start_afflvl,
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end_afflvl,
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target_cpu_nodes);
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if (rc != PSCI_E_SUCCESS)
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return rc;
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/*
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* This function acquires the lock corresponding to each affinity
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* level so that by the time all locks are taken, the system topology
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* is snapshot and state management can be done safely.
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*/
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psci_acquire_afflvl_locks(mpidr,
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start_afflvl,
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end_afflvl,
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target_cpu_nodes);
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/* Perform generic, architecture and platform specific handling. */
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rc = psci_call_on_handlers(target_cpu_nodes,
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start_afflvl,
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end_afflvl,
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target_cpu,
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entrypoint,
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context_id);
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/*
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* This loop releases the lock corresponding to each affinity level
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* in the reverse order to which they were acquired.
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*/
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psci_release_afflvl_locks(mpidr,
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start_afflvl,
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end_afflvl,
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target_cpu_nodes);
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return rc;
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}
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/*******************************************************************************
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* The following functions finish an earlier affinity power on request. They
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* are called by the common finisher routine in psci_common.c.
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******************************************************************************/
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static unsigned int psci_afflvl0_on_finish(unsigned long mpidr,
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aff_map_node_t *cpu_node)
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{
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unsigned int index, plat_state, state, rc = PSCI_E_SUCCESS;
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assert(cpu_node->level == MPIDR_AFFLVL0);
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/* Ensure we have been explicitly woken up by another cpu */
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state = psci_get_state(cpu_node);
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assert(state == PSCI_STATE_ON_PENDING);
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/*
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* Plat. management: Perform the platform specific actions
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* for this cpu e.g. enabling the gic or zeroing the mailbox
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* register. The actual state of this cpu has already been
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* changed.
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*/
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if (psci_plat_pm_ops->affinst_on_finish) {
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/* Get the physical state of this cpu */
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plat_state = get_phys_state(state);
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rc = psci_plat_pm_ops->affinst_on_finish(mpidr,
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cpu_node->level,
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plat_state);
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assert(rc == PSCI_E_SUCCESS);
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}
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/*
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* Arch. management: Turn on mmu & restore architectural state
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*/
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enable_mmu();
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/*
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* All the platform specific actions for turning this cpu
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* on have completed. Perform enough arch.initialization
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* to run in the non-secure address space.
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*/
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bl31_arch_setup();
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/*
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* Use the more complex exception vectors to enable SPD
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* initialisation. SP_EL3 should point to a 'cpu_context'
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* structure which has an exception stack allocated. The
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* calling cpu should have set the context already
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*/
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assert(cm_get_context(mpidr, NON_SECURE));
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cm_set_next_eret_context(NON_SECURE);
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write_vbar_el3((uint64_t) runtime_exceptions);
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/*
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* Call the cpu on finish handler registered by the Secure Payload
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* Dispatcher to let it do any bookeeping. If the handler encounters an
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* error, it's expected to assert within
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*/
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if (psci_spd_pm && psci_spd_pm->svc_on_finish)
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psci_spd_pm->svc_on_finish(0);
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/*
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* Generic management: Now we just need to retrieve the
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* information that we had stashed away during the cpu_on
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* call to set this cpu on its way. First get the index
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* for restoring the re-entry info
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*/
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index = cpu_node->data;
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psci_get_ns_entry_info(index);
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/* State management: mark this cpu as on */
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psci_set_state(cpu_node, PSCI_STATE_ON);
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/* Clean caches before re-entering normal world */
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dcsw_op_louis(DCCSW);
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return rc;
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}
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static unsigned int psci_afflvl1_on_finish(unsigned long mpidr,
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aff_map_node_t *cluster_node)
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{
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unsigned int plat_state, rc = PSCI_E_SUCCESS;
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assert(cluster_node->level == MPIDR_AFFLVL1);
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/*
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* Plat. management: Perform the platform specific actions
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* as per the old state of the cluster e.g. enabling
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* coherency at the interconnect depends upon the state with
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* which this cluster was powered up. If anything goes wrong
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* then assert as there is no way to recover from this
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* situation.
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*/
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if (psci_plat_pm_ops->affinst_on_finish) {
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/* Get the physical state of this cluster */
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plat_state = psci_get_phys_state(cluster_node);
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rc = psci_plat_pm_ops->affinst_on_finish(mpidr,
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cluster_node->level,
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plat_state);
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assert(rc == PSCI_E_SUCCESS);
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}
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/* State management: Increment the cluster reference count */
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psci_set_state(cluster_node, PSCI_STATE_ON);
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return rc;
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}
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static unsigned int psci_afflvl2_on_finish(unsigned long mpidr,
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aff_map_node_t *system_node)
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{
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unsigned int plat_state, rc = PSCI_E_SUCCESS;
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/* Cannot go beyond this affinity level */
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assert(system_node->level == MPIDR_AFFLVL2);
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/*
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* Currently, there are no architectural actions to perform
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* at the system level.
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*/
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/*
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* Plat. management: Perform the platform specific actions
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* as per the old state of the cluster e.g. enabling
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* coherency at the interconnect depends upon the state with
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* which this cluster was powered up. If anything goes wrong
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* then assert as there is no way to recover from this
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* situation.
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*/
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if (psci_plat_pm_ops->affinst_on_finish) {
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/* Get the physical state of the system */
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plat_state = psci_get_phys_state(system_node);
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rc = psci_plat_pm_ops->affinst_on_finish(mpidr,
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system_node->level,
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plat_state);
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assert(rc == PSCI_E_SUCCESS);
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}
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/* State management: Increment the system reference count */
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psci_set_state(system_node, PSCI_STATE_ON);
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return rc;
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}
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const afflvl_power_on_finisher_t psci_afflvl_on_finishers[] = {
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psci_afflvl0_on_finish,
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psci_afflvl1_on_finish,
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psci_afflvl2_on_finish,
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};
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