mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 01:24:27 +00:00

Add a support of USB as serial boot devices for STM32MP15x platform: the FIP file is provide by STM32CubeProgrammer with the DFU protocol, loaded in DDR at DWL_BUFFER_BASE address and then the io memmap is used. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Change-Id: I272c17c458ff1e9d0780f8fa22330c8a35533d19
440 lines
10 KiB
C
440 lines
10 KiB
C
/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <drivers/io/io_block.h>
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#include <drivers/io/io_driver.h>
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#include <drivers/io/io_fip.h>
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#include <drivers/io/io_memmap.h>
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#include <drivers/io/io_mtd.h>
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#include <drivers/io/io_storage.h>
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#include <drivers/mmc.h>
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#include <drivers/partition/partition.h>
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#include <drivers/raw_nand.h>
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#include <drivers/spi_nand.h>
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#include <drivers/spi_nor.h>
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#include <drivers/st/io_mmc.h>
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#include <drivers/st/stm32_fmc2_nand.h>
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#include <drivers/st/stm32_qspi.h>
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#include <drivers/st/stm32_sdmmc2.h>
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#include <drivers/usb_device.h>
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#include <lib/fconf/fconf.h>
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#include <lib/mmio.h>
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#include <lib/utils.h>
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#include <plat/common/platform.h>
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#include <tools_share/firmware_image_package.h>
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#include <platform_def.h>
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#include <stm32cubeprogrammer.h>
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#include <stm32mp_fconf_getter.h>
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#include <usb_dfu.h>
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/* IO devices */
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uintptr_t fip_dev_handle;
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uintptr_t storage_dev_handle;
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static const io_dev_connector_t *fip_dev_con;
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#if STM32MP_SDMMC || STM32MP_EMMC
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static struct mmc_device_info mmc_info;
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static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE);
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static io_block_dev_spec_t mmc_block_dev_spec = {
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/* It's used as temp buffer in block driver */
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.buffer = {
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.offset = (size_t)&block_buffer,
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.length = MMC_BLOCK_SIZE,
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},
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.ops = {
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.read = mmc_read_blocks,
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.write = NULL,
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},
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.block_size = MMC_BLOCK_SIZE,
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};
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static const io_dev_connector_t *mmc_dev_con;
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#endif /* STM32MP_SDMMC || STM32MP_EMMC */
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#if STM32MP_SPI_NOR
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static io_mtd_dev_spec_t spi_nor_dev_spec = {
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.ops = {
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.init = spi_nor_init,
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.read = spi_nor_read,
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},
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};
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#endif
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#if STM32MP_RAW_NAND
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static io_mtd_dev_spec_t nand_dev_spec = {
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.ops = {
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.init = nand_raw_init,
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.read = nand_read,
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.seek = nand_seek_bb
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},
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};
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static const io_dev_connector_t *nand_dev_con;
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#endif
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#if STM32MP_SPI_NAND
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static io_mtd_dev_spec_t spi_nand_dev_spec = {
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.ops = {
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.init = spi_nand_init,
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.read = nand_read,
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.seek = nand_seek_bb
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},
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};
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#endif
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#if STM32MP_SPI_NAND || STM32MP_SPI_NOR
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static const io_dev_connector_t *spi_dev_con;
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#endif
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#if STM32MP_USB_PROGRAMMER
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static const io_dev_connector_t *memmap_dev_con;
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#endif
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io_block_spec_t image_block_spec = {
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.offset = 0U,
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.length = 0U,
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};
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int open_fip(const uintptr_t spec)
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{
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return io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
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}
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int open_storage(const uintptr_t spec)
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{
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return io_dev_init(storage_dev_handle, 0);
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}
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static void print_boot_device(boot_api_context_t *boot_context)
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{
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switch (boot_context->boot_interface_selected) {
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
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INFO("Using SDMMC\n");
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break;
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
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INFO("Using EMMC\n");
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break;
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
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INFO("Using QSPI NOR\n");
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break;
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
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INFO("Using FMC NAND\n");
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break;
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
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INFO("Using SPI NAND\n");
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break;
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
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INFO("Using USB\n");
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break;
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default:
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ERROR("Boot interface %u not found\n",
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boot_context->boot_interface_selected);
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panic();
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break;
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}
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if (boot_context->boot_interface_instance != 0U) {
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INFO(" Instance %d\n", boot_context->boot_interface_instance);
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}
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}
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#if STM32MP_SDMMC || STM32MP_EMMC
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static void boot_mmc(enum mmc_device_type mmc_dev_type,
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uint16_t boot_interface_instance)
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{
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int io_result __unused;
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struct stm32_sdmmc2_params params;
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zeromem(¶ms, sizeof(struct stm32_sdmmc2_params));
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mmc_info.mmc_dev_type = mmc_dev_type;
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switch (boot_interface_instance) {
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case 1:
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params.reg_base = STM32MP_SDMMC1_BASE;
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break;
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case 2:
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params.reg_base = STM32MP_SDMMC2_BASE;
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break;
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case 3:
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params.reg_base = STM32MP_SDMMC3_BASE;
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break;
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default:
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WARN("SDMMC instance not found, using default\n");
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if (mmc_dev_type == MMC_IS_SD) {
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params.reg_base = STM32MP_SDMMC1_BASE;
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} else {
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params.reg_base = STM32MP_SDMMC2_BASE;
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}
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break;
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}
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params.device_info = &mmc_info;
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if (stm32_sdmmc2_mmc_init(¶ms) != 0) {
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ERROR("SDMMC%u init failed\n", boot_interface_instance);
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panic();
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}
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/* Open MMC as a block device to read GPT table */
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io_result = register_io_dev_block(&mmc_dev_con);
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if (io_result != 0) {
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panic();
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}
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io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec,
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&storage_dev_handle);
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assert(io_result == 0);
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}
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#endif /* STM32MP_SDMMC || STM32MP_EMMC */
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#if STM32MP_SPI_NOR
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static void boot_spi_nor(boot_api_context_t *boot_context)
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{
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int io_result __unused;
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io_result = stm32_qspi_init();
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assert(io_result == 0);
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io_result = register_io_dev_mtd(&spi_dev_con);
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assert(io_result == 0);
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/* Open connections to device */
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io_result = io_dev_open(spi_dev_con,
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(uintptr_t)&spi_nor_dev_spec,
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&storage_dev_handle);
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assert(io_result == 0);
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}
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#endif /* STM32MP_SPI_NOR */
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#if STM32MP_RAW_NAND
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static void boot_fmc2_nand(boot_api_context_t *boot_context)
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{
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int io_result __unused;
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io_result = stm32_fmc2_init();
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assert(io_result == 0);
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/* Register the IO device on this platform */
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io_result = register_io_dev_mtd(&nand_dev_con);
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assert(io_result == 0);
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/* Open connections to device */
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io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec,
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&storage_dev_handle);
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assert(io_result == 0);
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}
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#endif /* STM32MP_RAW_NAND */
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#if STM32MP_SPI_NAND
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static void boot_spi_nand(boot_api_context_t *boot_context)
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{
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int io_result __unused;
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io_result = stm32_qspi_init();
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assert(io_result == 0);
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io_result = register_io_dev_mtd(&spi_dev_con);
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assert(io_result == 0);
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/* Open connections to device */
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io_result = io_dev_open(spi_dev_con,
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(uintptr_t)&spi_nand_dev_spec,
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&storage_dev_handle);
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assert(io_result == 0);
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}
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#endif /* STM32MP_SPI_NAND */
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#if STM32MP_USB_PROGRAMMER
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static void mmap_io_setup(void)
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{
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int io_result __unused;
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io_result = register_io_dev_memmap(&memmap_dev_con);
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assert(io_result == 0);
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io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
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&storage_dev_handle);
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assert(io_result == 0);
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}
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static void stm32cubeprogrammer_usb(void)
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{
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int ret __unused;
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struct usb_handle *pdev;
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/* Init USB on platform */
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pdev = usb_dfu_plat_init();
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ret = stm32cubeprog_usb_load(pdev, DWL_BUFFER_BASE, DWL_BUFFER_SIZE);
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assert(ret == 0);
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}
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#endif
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void stm32mp_io_setup(void)
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{
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int io_result __unused;
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boot_api_context_t *boot_context =
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(boot_api_context_t *)stm32mp_get_boot_ctx_address();
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print_boot_device(boot_context);
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if ((boot_context->boot_partition_used_toboot == 1U) ||
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(boot_context->boot_partition_used_toboot == 2U)) {
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INFO("Boot used partition fsbl%u\n",
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boot_context->boot_partition_used_toboot);
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}
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io_result = register_io_dev_fip(&fip_dev_con);
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assert(io_result == 0);
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io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
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&fip_dev_handle);
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switch (boot_context->boot_interface_selected) {
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#if STM32MP_SDMMC
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
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dmbsy();
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boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance);
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break;
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#endif
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#if STM32MP_EMMC
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
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dmbsy();
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boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance);
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break;
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#endif
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#if STM32MP_SPI_NOR
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
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dmbsy();
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boot_spi_nor(boot_context);
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break;
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#endif
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#if STM32MP_RAW_NAND
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
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dmbsy();
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boot_fmc2_nand(boot_context);
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break;
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#endif
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#if STM32MP_SPI_NAND
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
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dmbsy();
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boot_spi_nand(boot_context);
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break;
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#endif
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#if STM32MP_USB_PROGRAMMER
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
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dmbsy();
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mmap_io_setup();
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break;
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#endif
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default:
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ERROR("Boot interface %d not supported\n",
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boot_context->boot_interface_selected);
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panic();
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break;
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}
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}
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int bl2_plat_handle_pre_image_load(unsigned int image_id)
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{
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static bool gpt_init_done __unused;
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uint16_t boot_itf = stm32mp_get_boot_itf_selected();
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switch (boot_itf) {
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#if STM32MP_SDMMC || STM32MP_EMMC
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
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if (!gpt_init_done) {
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const partition_entry_t *entry;
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partition_init(GPT_IMAGE_ID);
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entry = get_partition_entry(FIP_IMAGE_NAME);
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if (entry == NULL) {
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ERROR("Could NOT find the %s partition!\n",
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FIP_IMAGE_NAME);
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return -ENOENT;
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}
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image_block_spec.offset = entry->start;
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image_block_spec.length = entry->length;
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gpt_init_done = true;
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} else {
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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mmc_block_dev_spec.buffer.offset = bl_mem_params->image_info.image_base;
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mmc_block_dev_spec.buffer.length = bl_mem_params->image_info.image_max_size;
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}
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break;
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#endif
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#if STM32MP_RAW_NAND || STM32MP_SPI_NAND
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#if STM32MP_RAW_NAND
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
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#endif
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#if STM32MP_SPI_NAND
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
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#endif
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image_block_spec.offset = STM32MP_NAND_FIP_OFFSET;
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break;
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#endif
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#if STM32MP_SPI_NOR
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
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image_block_spec.offset = STM32MP_NOR_FIP_OFFSET;
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break;
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#endif
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#if STM32MP_USB_PROGRAMMER
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
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if (image_id == FW_CONFIG_ID) {
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stm32cubeprogrammer_usb();
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/* FIP loaded at DWL address */
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image_block_spec.offset = DWL_BUFFER_BASE;
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image_block_spec.length = DWL_BUFFER_SIZE;
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}
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break;
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#endif
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default:
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ERROR("FIP Not found\n");
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panic();
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}
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return 0;
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}
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/*
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* Return an IO device handle and specification which can be used to access
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* an image. Use this to enforce platform load policy.
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*/
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int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
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uintptr_t *image_spec)
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{
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int rc;
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const struct plat_io_policy *policy;
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policy = FCONF_GET_PROPERTY(stm32mp, io_policies, image_id);
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rc = policy->check(policy->image_spec);
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if (rc == 0) {
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*image_spec = policy->image_spec;
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*dev_handle = *(policy->dev_handle);
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}
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return rc;
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}
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