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https://github.com/ARM-software/arm-trusted-firmware.git
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f9e858b1f7
This patch implements the platform power managment handler to verify non secure entrypoint for ARM platforms. The handler ensures that the entry point specified by the normal world during CPU_SUSPEND, CPU_ON or SYSTEM_SUSPEND PSCI API is a valid address within the non secure DRAM. Change-Id: I4795452df99f67a24682b22f0e0967175c1de429
285 lines
10 KiB
C
285 lines
10 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <arm_gic.h>
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#include <cci.h>
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#include <css_def.h>
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#include <debug.h>
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#include <errno.h>
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#include <plat_arm.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <psci.h>
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#include "css_scpi.h"
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#if ARM_RECOM_STATE_ID_ENC
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/*
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* The table storing the valid idle power states. Ensure that the
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* array entries are populated in ascending order of state-id to
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* enable us to use binary search during power state validation.
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* The table must be terminated by a NULL entry.
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*/
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const unsigned int arm_pm_idle_states[] = {
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/* State-id - 0x01 */
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arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET,
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ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
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/* State-id - 0x02 */
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arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
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ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
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/* State-id - 0x22 */
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arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
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ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
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0,
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};
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#endif
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/*******************************************************************************
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* Private function to program the mailbox for a cpu before it is released
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* from reset.
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******************************************************************************/
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static void css_program_mailbox(uintptr_t address)
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{
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uintptr_t *mailbox = (void *) TRUSTED_MAILBOX_BASE;
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*mailbox = address;
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flush_dcache_range((uintptr_t) mailbox, sizeof(*mailbox));
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}
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/*******************************************************************************
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* Handler called when a power domain is about to be turned on. The
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* level and mpidr determine the affinity instance.
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******************************************************************************/
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int css_pwr_domain_on(u_register_t mpidr)
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{
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/*
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* SCP takes care of powering up parent power domains so we
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* only need to care about level 0
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*/
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scpi_set_css_power_state(mpidr, scpi_power_on, scpi_power_on,
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scpi_power_on);
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Handler called when a power level has just been powered on after
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* being turned off earlier. The target_state encodes the low power state that
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* each level has woken up from.
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******************************************************************************/
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void css_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
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ARM_LOCAL_STATE_OFF);
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/*
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* Perform the common cluster specific operations i.e enable coherency
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* if this cluster was off.
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*/
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if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
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ARM_LOCAL_STATE_OFF)
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
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/* Enable the gic cpu interface */
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arm_gic_cpuif_setup();
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/* todo: Is this setup only needed after a cold boot? */
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arm_gic_pcpu_distif_setup();
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}
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/*******************************************************************************
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* Common function called while turning a cpu off or suspending it. It is called
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* from css_off() or css_suspend() when these functions in turn are called for
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* power domain at the highest power level which will be powered down. It
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* performs the actions common to the OFF and SUSPEND calls.
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******************************************************************************/
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static void css_power_down_common(const psci_power_state_t *target_state)
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{
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uint32_t cluster_state = scpi_power_on;
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/* Prevent interrupts from spuriously waking up this cpu */
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arm_gic_cpuif_deactivate();
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/* Cluster is to be turned off, so disable coherency */
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if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
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ARM_LOCAL_STATE_OFF) {
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cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
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cluster_state = scpi_power_off;
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}
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/*
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* Ask the SCP to power down the appropriate components depending upon
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* their state.
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*/
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scpi_set_css_power_state(read_mpidr_el1(),
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scpi_power_off,
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cluster_state,
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scpi_power_on);
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}
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/*******************************************************************************
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* Handler called when a power domain is about to be turned off. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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static void css_pwr_domain_off(const psci_power_state_t *target_state)
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{
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assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
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ARM_LOCAL_STATE_OFF);
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css_power_down_common(target_state);
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}
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/*******************************************************************************
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* Handler called when a power domain is about to be suspended. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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static void css_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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/*
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* Juno has retention only at cpu level. Just return
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* as nothing is to be done for retention.
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*/
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if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
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ARM_LOCAL_STATE_RET)
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return;
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assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
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ARM_LOCAL_STATE_OFF);
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css_power_down_common(target_state);
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}
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/*******************************************************************************
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* Handler called when a power domain has just been powered on after
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* having been suspended earlier. The target_state encodes the low power state
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* that each level has woken up from.
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* TODO: At the moment we reuse the on finisher and reinitialize the secure
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* context. Need to implement a separate suspend finisher.
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******************************************************************************/
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static void css_pwr_domain_suspend_finish(
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const psci_power_state_t *target_state)
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{
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/*
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* Return as nothing is to be done on waking up from retention.
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*/
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if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
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ARM_LOCAL_STATE_RET)
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return;
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css_pwr_domain_on_finish(target_state);
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}
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/*******************************************************************************
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* Handlers to shutdown/reboot the system
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******************************************************************************/
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static void __dead2 css_system_off(void)
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{
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uint32_t response;
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/* Send the power down request to the SCP */
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response = scpi_sys_power_state(scpi_system_shutdown);
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if (response != SCP_OK) {
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ERROR("CSS System Off: SCP error %u.\n", response);
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panic();
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}
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wfi();
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ERROR("CSS System Off: operation not handled.\n");
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panic();
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}
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static void __dead2 css_system_reset(void)
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{
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uint32_t response;
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/* Send the system reset request to the SCP */
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response = scpi_sys_power_state(scpi_system_reboot);
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if (response != SCP_OK) {
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ERROR("CSS System Reset: SCP error %u.\n", response);
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panic();
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}
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wfi();
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ERROR("CSS System Reset: operation not handled.\n");
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panic();
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}
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/*******************************************************************************
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* Handler called when the CPU power domain is about to enter standby.
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******************************************************************************/
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void css_cpu_standby(plat_local_state_t cpu_state)
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{
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unsigned int scr;
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assert(cpu_state == ARM_LOCAL_STATE_RET);
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scr = read_scr_el3();
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/* Enable PhysicalIRQ bit for NS world to wake the CPU */
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write_scr_el3(scr | SCR_IRQ_BIT);
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isb();
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dsb();
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wfi();
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/*
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* Restore SCR to the original value, synchronisation of scr_el3 is
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* done by eret while el3_exit to save some execution cycles.
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*/
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write_scr_el3(scr);
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}
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/*******************************************************************************
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* Export the platform handlers to enable psci to invoke them
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******************************************************************************/
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static const plat_psci_ops_t css_ops = {
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.pwr_domain_on = css_pwr_domain_on,
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.pwr_domain_on_finish = css_pwr_domain_on_finish,
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.pwr_domain_off = css_pwr_domain_off,
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.cpu_standby = css_cpu_standby,
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.pwr_domain_suspend = css_pwr_domain_suspend,
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.pwr_domain_suspend_finish = css_pwr_domain_suspend_finish,
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.system_off = css_system_off,
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.system_reset = css_system_reset,
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.validate_power_state = arm_validate_power_state,
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.validate_ns_entrypoint = arm_validate_ns_entrypoint
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};
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/*******************************************************************************
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* Export the platform specific psci ops.
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******************************************************************************/
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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*psci_ops = &css_ops;
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/* Setup mailbox with entry point. */
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css_program_mailbox(sec_entrypoint);
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return 0;
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}
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