mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 01:54:22 +00:00
f893160690
In order to allow the MHUv2 driver to be usable with multiple MHUv2 controllers, use the base address of the controller from the platform information instead of the MHUV2_BASE_ADDR macro. Change-Id: I4dbab87b929fb0568935e6c8b339ce67937f8cd1 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
40 lines
983 B
C
40 lines
983 B
C
/*
|
|
* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#ifndef PLATFORM_DEF_H
|
|
#define PLATFORM_DEF_H
|
|
|
|
#include <lib/utils_def.h>
|
|
|
|
#include <sgi_base_platform_def.h>
|
|
|
|
#define PLAT_ARM_CLUSTER_COUNT U(2)
|
|
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
|
|
#define CSS_SGI_MAX_PE_PER_CPU U(1)
|
|
|
|
#define PLAT_CSS_MHU_BASE UL(0x45000000)
|
|
|
|
/* Base address of DMC-620 instances */
|
|
#define SGI575_DMC620_BASE0 UL(0x4e000000)
|
|
#define SGI575_DMC620_BASE1 UL(0x4e100000)
|
|
|
|
/* System power domain level */
|
|
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
|
|
|
|
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
|
|
|
|
/*
|
|
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
|
|
*/
|
|
#ifdef __aarch64__
|
|
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
|
|
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
|
|
#else
|
|
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
|
|
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
|
|
#endif
|
|
|
|
#endif /* PLATFORM_DEF_H */
|