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f893160690
In order to allow the MHUv2 driver to be usable with multiple MHUv2 controllers, use the base address of the controller from the platform information instead of the MHUV2_BASE_ADDR macro. Change-Id: I4dbab87b929fb0568935e6c8b339ce67937f8cd1 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
40 lines
987 B
C
40 lines
987 B
C
/*
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <lib/utils_def.h>
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#include <sgi_base_platform_def.h>
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#define PLAT_ARM_CLUSTER_COUNT U(2)
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
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#define CSS_SGI_MAX_PE_PER_CPU U(1)
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#define PLAT_CSS_MHU_BASE UL(0x45400000)
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/* Base address of DMC-620 instances */
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#define RDN1EDGE_DMC620_BASE0 UL(0x4e000000)
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#define RDN1EDGE_DMC620_BASE1 UL(0x4e100000)
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/* System power domain level */
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
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/*
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* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
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*/
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#ifdef __aarch64__
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
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#else
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#endif
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#endif /* PLATFORM_DEF_H */
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