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https://github.com/ARM-software/arm-trusted-firmware.git
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f86098a62c
For N1, this involves replacing:
- The reset_func with the standard cpu_reset_func_{start,end}
to apply errata automatically
- The <cpu>_errata_report with the errata_report_shim to
report errata automatically
And for each erratum:
- The prologue with the workaround_<type>_start to do the checks and
framework registration automatically at reset or runtime
- The epilogue with the workaround_<type>_end
- The checker function with the check_erratum_<type> to check whether
the erratum applies on the revision of the CPU.
Testing was conducted by:
- Manual comparison of disassembly of converted functions with non-
converted functions:
aarch64-none-elf-objdump -D
<trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D
<trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf
- Build for debug with all errata enabled and step through ArmDS
to ensure all functions are entered and the path remains the same
as before conversion to the new framework.
Change-Id: I2ea612d4c197dd73835fadda81f59732c19534f8
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
341 lines
10 KiB
ArmAsm
341 lines
10 KiB
ArmAsm
/*
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* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpuamu.h>
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#include <cpu_macros.S>
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#include <neoverse_n1.h>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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.global neoverse_n1_errata_ic_trap_handler
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1
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#endif /* WORKAROUND_CVE_2022_23960 */
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/*
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* ERRATA_DSU_936184:
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* The errata is defined in dsu_helpers.S and applies to Neoverse N1.
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* Henceforth creating symbolic names to the already existing errata
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* workaround functions to get them registered under the Errata Framework.
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*/
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.equ check_erratum_neoverse_n1_936184, check_errata_dsu_936184
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.equ erratum_neoverse_n1_936184_wa, errata_dsu_936184_wa
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add_erratum_entry neoverse_n1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
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workaround_reset_start neoverse_n1, ERRATUM(1043202), ERRATA_N1_1043202
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/* Apply instruction patching sequence */
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ldr x0, =0x0
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msr CPUPSELR_EL3, x0
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ldr x0, =0xF3BF8F2F
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msr CPUPOR_EL3, x0
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ldr x0, =0xFFFFFFFF
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msr CPUPMR_EL3, x0
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ldr x0, =0x800200071
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msr CPUPCR_EL3, x0
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workaround_reset_end neoverse_n1, ERRATUM(1043202)
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check_erratum_ls neoverse_n1, ERRATUM(1043202), CPU_REV(1, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1073348), ERRATA_N1_1073348
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mrs x1, NEOVERSE_N1_CPUACTLR_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
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msr NEOVERSE_N1_CPUACTLR_EL1, x1
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workaround_reset_end neoverse_n1, ERRATUM(1073348)
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check_erratum_ls neoverse_n1, ERRATUM(1073348), CPU_REV(1, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1130799), ERRATA_N1_1130799
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mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
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msr NEOVERSE_N1_CPUACTLR2_EL1, x1
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workaround_reset_end neoverse_n1, ERRATUM(1130799)
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check_erratum_ls neoverse_n1, ERRATUM(1130799), CPU_REV(2, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1165347), ERRATA_N1_1165347
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mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
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orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
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msr NEOVERSE_N1_CPUACTLR2_EL1, x1
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workaround_reset_end neoverse_n1, ERRATUM(1165347)
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check_erratum_ls neoverse_n1, ERRATUM(1165347), CPU_REV(2, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1207823), ERRATA_N1_1207823
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mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
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msr NEOVERSE_N1_CPUACTLR2_EL1, x1
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workaround_reset_end neoverse_n1, ERRATUM(1207823)
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check_erratum_ls neoverse_n1, ERRATUM(1207823), CPU_REV(2, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1220197), ERRATA_N1_1220197
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mrs x1, NEOVERSE_N1_CPUECTLR_EL1
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orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK
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msr NEOVERSE_N1_CPUECTLR_EL1, x1
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workaround_reset_end neoverse_n1, ERRATUM(1220197)
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check_erratum_ls neoverse_n1, ERRATUM(1220197), CPU_REV(2, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1257314), ERRATA_N1_1257314
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mrs x1, NEOVERSE_N1_CPUACTLR3_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
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msr NEOVERSE_N1_CPUACTLR3_EL1, x1
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workaround_reset_end neoverse_n1, ERRATUM(1257314)
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check_erratum_ls neoverse_n1, ERRATUM(1257314), CPU_REV(3, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1262606), ERRATA_N1_1262606
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mrs x1, NEOVERSE_N1_CPUACTLR_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
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msr NEOVERSE_N1_CPUACTLR_EL1, x1
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workaround_reset_end neoverse_n1, ERRATUM(1262606)
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check_erratum_ls neoverse_n1, ERRATUM(1262606), CPU_REV(3, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1262888), ERRATA_N1_1262888
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mrs x1, NEOVERSE_N1_CPUECTLR_EL1
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orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
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msr NEOVERSE_N1_CPUECTLR_EL1, x1
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workaround_reset_end neoverse_n1, ERRATUM(1262888)
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check_erratum_ls neoverse_n1, ERRATUM(1262888), CPU_REV(3, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1275112), ERRATA_N1_1275112
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mrs x1, NEOVERSE_N1_CPUACTLR_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
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msr NEOVERSE_N1_CPUACTLR_EL1, x1
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workaround_reset_end neoverse_n1, ERRATUM(1275112)
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check_erratum_ls neoverse_n1, ERRATUM(1275112), CPU_REV(3, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1315703), ERRATA_N1_1315703
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mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
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orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
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msr NEOVERSE_N1_CPUACTLR2_EL1, x0
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workaround_reset_end neoverse_n1, ERRATUM(1315703)
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check_erratum_ls neoverse_n1, ERRATUM(1315703), CPU_REV(3, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1542419), ERRATA_N1_1542419
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/* Apply instruction patching sequence */
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ldr x0, =0x0
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msr CPUPSELR_EL3, x0
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ldr x0, =0xEE670D35
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msr CPUPOR_EL3, x0
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ldr x0, =0xFFFF0FFF
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msr CPUPMR_EL3, x0
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ldr x0, =0x08000020007D
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msr CPUPCR_EL3, x0
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isb
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workaround_reset_end neoverse_n1, ERRATUM(1542419)
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check_erratum_range neoverse_n1, ERRATUM(1542419), CPU_REV(3, 0), CPU_REV(4, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1868343), ERRATA_N1_1868343
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mrs x1, NEOVERSE_N1_CPUACTLR_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
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msr NEOVERSE_N1_CPUACTLR_EL1, x1
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workaround_reset_end neoverse_n1, ERRATUM(1868343)
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check_erratum_ls neoverse_n1, ERRATUM(1868343), CPU_REV(4, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1946160), ERRATA_N1_1946160
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mov x0, #3
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msr S3_6_C15_C8_0, x0
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ldr x0, =0x10E3900002
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msr S3_6_C15_C8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_C15_C8_1, x0
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mov x0, #4
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msr S3_6_C15_C8_0, x0
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ldr x0, =0x10E3800082
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msr S3_6_C15_C8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_C15_C8_1, x0
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mov x0, #5
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msr S3_6_C15_C8_0, x0
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ldr x0, =0x10E3800200
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msr S3_6_C15_C8_2, x0
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ldr x0, =0x10FFF003E0
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_C15_C8_1, x0
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isb
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workaround_reset_end neoverse_n1, ERRATUM(1946160)
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check_erratum_range neoverse_n1, ERRATUM(1946160), CPU_REV(3, 0), CPU_REV(4, 1)
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workaround_runtime_start neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end neoverse_n1, ERRATUM(2743102)
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check_erratum_ls neoverse_n1, ERRATUM(2743102), CPU_REV(4, 1)
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workaround_reset_start neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Neoverse-N1 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_neoverse_n1
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 */
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workaround_reset_end neoverse_n1, CVE(2022, 23960)
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check_erratum_chosen neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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/* --------------------------------------------------
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* Disable speculative loads if Neoverse N1 supports
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* SSBS.
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*
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* Shall clobber: x0.
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* --------------------------------------------------
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*/
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func neoverse_n1_disable_speculative_loads
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/* Check if the PE implements SSBS */
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mrs x0, id_aa64pfr1_el1
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tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
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b.eq 1f
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/* Disable speculative loads */
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msr SSBS, xzr
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1:
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ret
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endfunc neoverse_n1_disable_speculative_loads
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cpu_reset_func_start neoverse_n1
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bl neoverse_n1_disable_speculative_loads
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/* Forces all cacheable atomic instructions to be near */
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mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
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orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
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msr NEOVERSE_N1_CPUACTLR2_EL1, x0
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isb
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#if ENABLE_FEAT_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
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msr actlr_el3, x0
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
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msr actlr_el2, x0
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/* Enable group0 counters */
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mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK
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msr CPUAMCNTENSET_EL0, x0
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#endif
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#if NEOVERSE_Nx_EXTERNAL_LLC
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/* Some system may have External LLC, core needs to be made aware */
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mrs x0, NEOVERSE_N1_CPUECTLR_EL1
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orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
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msr NEOVERSE_N1_CPUECTLR_EL1, x0
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#endif
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cpu_reset_func_end neoverse_n1
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func neoverse_n1_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
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orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
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msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
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#if ERRATA_N1_2743102
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mov x15, x30
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bl cpu_get_rev_var
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bl erratum_neoverse_n1_2743102_wa
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mov x30, x15
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#endif /* ERRATA_N1_2743102 */
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isb
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ret
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endfunc neoverse_n1_core_pwr_dwn
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errata_report_shim neoverse_n1
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/*
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* Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB
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* inner-shareable invalidation to an arbitrary address followed by a DSB.
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*
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* x1: Exception Syndrome
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*/
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func neoverse_n1_errata_ic_trap_handler
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cmp x1, #NEOVERSE_N1_EC_IC_TRAP
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b.ne 1f
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tlbi vae3is, xzr
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dsb sy
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# Skip the IC instruction itself
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mrs x3, elr_el3
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add x3, x3, #4
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msr elr_el3, x3
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ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
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ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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/*
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* Issue Error Synchronization Barrier to synchronize SErrors before
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* exiting EL3. We're running with EAs unmasked, so any synchronized
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* errors would be taken immediately; therefore no need to inspect
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* DISR_EL1 register.
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*/
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esb
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exception_return
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1:
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ret
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endfunc neoverse_n1_errata_ic_trap_handler
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/* ---------------------------------------------
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* This function provides neoverse_n1 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_n1_regs, "aS"
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neoverse_n1_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_n1_cpu_reg_dump
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adr x6, neoverse_n1_regs
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mrs x8, NEOVERSE_N1_CPUECTLR_EL1
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ret
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endfunc neoverse_n1_cpu_reg_dump
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declare_cpu_ops_eh neoverse_n1, NEOVERSE_N1_MIDR, \
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neoverse_n1_reset_func, \
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neoverse_n1_errata_ic_trap_handler, \
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neoverse_n1_core_pwr_dwn
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