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f62ad32269
Invalidate the Branch Target Buffer (BTB) on entry to EL3 by disabling and enabling the MMU. To achieve this without performing any branch instruction, a per-cpu vbar is installed which executes the workaround and then branches off to the corresponding vector entry in the main vector table. A side effect of this change is that the main vbar is configured before any reset handling. This is to allow the per-cpu reset function to override the vbar setting. This workaround is enabled by default on the affected CPUs. Change-Id: I97788d38463a5840a410e3cea85ed297a1678265 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
114 lines
3.2 KiB
ArmAsm
114 lines
3.2 KiB
ArmAsm
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <context.h>
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.globl workaround_mmu_runtime_exceptions
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vector_base workaround_mmu_runtime_exceptions
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.macro apply_workaround
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stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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mrs x0, sctlr_el3
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/* Disable MMU */
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bic x1, x0, #SCTLR_M_BIT
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msr sctlr_el3, x1
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isb
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/* Restore MMU config */
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msr sctlr_el3, x0
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isb
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ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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.endm
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/* ---------------------------------------------------------------------
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* Current EL with SP_EL0 : 0x0 - 0x200
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* ---------------------------------------------------------------------
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*/
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vector_entry workaround_mmu_sync_exception_sp_el0
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b sync_exception_sp_el0
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check_vector_size workaround_mmu_sync_exception_sp_el0
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vector_entry workaround_mmu_irq_sp_el0
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b irq_sp_el0
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check_vector_size workaround_mmu_irq_sp_el0
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vector_entry workaround_mmu_fiq_sp_el0
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b fiq_sp_el0
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check_vector_size workaround_mmu_fiq_sp_el0
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vector_entry workaround_mmu_serror_sp_el0
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b serror_sp_el0
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check_vector_size workaround_mmu_serror_sp_el0
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/* ---------------------------------------------------------------------
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* Current EL with SP_ELx: 0x200 - 0x400
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* ---------------------------------------------------------------------
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*/
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vector_entry workaround_mmu_sync_exception_sp_elx
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b sync_exception_sp_elx
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check_vector_size workaround_mmu_sync_exception_sp_elx
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vector_entry workaround_mmu_irq_sp_elx
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b irq_sp_elx
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check_vector_size workaround_mmu_irq_sp_elx
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vector_entry workaround_mmu_fiq_sp_elx
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b fiq_sp_elx
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check_vector_size workaround_mmu_fiq_sp_elx
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vector_entry workaround_mmu_serror_sp_elx
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b serror_sp_elx
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check_vector_size workaround_mmu_serror_sp_elx
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/* ---------------------------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600
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* ---------------------------------------------------------------------
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*/
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vector_entry workaround_mmu_sync_exception_aarch64
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apply_workaround
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b sync_exception_aarch64
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check_vector_size workaround_mmu_sync_exception_aarch64
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vector_entry workaround_mmu_irq_aarch64
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apply_workaround
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b irq_aarch64
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check_vector_size workaround_mmu_irq_aarch64
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vector_entry workaround_mmu_fiq_aarch64
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apply_workaround
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b fiq_aarch64
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check_vector_size workaround_mmu_fiq_aarch64
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vector_entry workaround_mmu_serror_aarch64
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apply_workaround
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b serror_aarch64
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check_vector_size workaround_mmu_serror_aarch64
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/* ---------------------------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* ---------------------------------------------------------------------
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*/
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vector_entry workaround_mmu_sync_exception_aarch32
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apply_workaround
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b sync_exception_aarch32
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check_vector_size workaround_mmu_sync_exception_aarch32
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vector_entry workaround_mmu_irq_aarch32
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apply_workaround
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b irq_aarch32
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check_vector_size workaround_mmu_irq_aarch32
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vector_entry workaround_mmu_fiq_aarch32
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apply_workaround
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b fiq_aarch32
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check_vector_size workaround_mmu_fiq_aarch32
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vector_entry workaround_mmu_serror_aarch32
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apply_workaround
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b serror_aarch32
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check_vector_size workaround_mmu_serror_aarch32
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