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f62ad32269
Invalidate the Branch Target Buffer (BTB) on entry to EL3 by disabling and enabling the MMU. To achieve this without performing any branch instruction, a per-cpu vbar is installed which executes the workaround and then branches off to the corresponding vector entry in the main vector table. A side effect of this change is that the main vbar is configured before any reset handling. This is to allow the per-cpu reset function to override the vbar setting. This workaround is enabled by default on the affected CPUs. Change-Id: I97788d38463a5840a410e3cea85ed297a1678265 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
283 lines
7.4 KiB
ArmAsm
283 lines
7.4 KiB
ArmAsm
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a72.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* ---------------------------------------------
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* Disable L1 data cache and unified L2 cache
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* ---------------------------------------------
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*/
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func cortex_a72_disable_dcache
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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ret
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endfunc cortex_a72_disable_dcache
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/* ---------------------------------------------
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* Disable all types of L2 prefetches.
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* ---------------------------------------------
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*/
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func cortex_a72_disable_l2_prefetch
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mrs x0, CORTEX_A72_ECTLR_EL1
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orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT
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mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK
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orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK
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bic x0, x0, x1
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msr CORTEX_A72_ECTLR_EL1, x0
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isb
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ret
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endfunc cortex_a72_disable_l2_prefetch
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/* ---------------------------------------------
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* Disable the load-store hardware prefetcher.
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* ---------------------------------------------
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*/
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func cortex_a72_disable_hw_prefetcher
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mrs x0, CORTEX_A72_CPUACTLR_EL1
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orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
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msr CORTEX_A72_CPUACTLR_EL1, x0
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isb
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dsb ish
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ret
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endfunc cortex_a72_disable_hw_prefetcher
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* ---------------------------------------------
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*/
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func cortex_a72_disable_smp
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mrs x0, CORTEX_A72_ECTLR_EL1
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bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
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msr CORTEX_A72_ECTLR_EL1, x0
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ret
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endfunc cortex_a72_disable_smp
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/* ---------------------------------------------
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* Disable debug interfaces
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* ---------------------------------------------
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*/
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func cortex_a72_disable_ext_debug
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mov x0, #1
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msr osdlr_el1, x0
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isb
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dsb sy
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ret
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endfunc cortex_a72_disable_ext_debug
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/* --------------------------------------------------
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* Errata Workaround for Cortex A72 Errata #859971.
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* This applies only to revision <= r0p3 of Cortex A72.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber:
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* --------------------------------------------------
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*/
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func errata_a72_859971_wa
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mov x17,x30
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bl check_errata_859971
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cbz x0, 1f
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mrs x1, CORTEX_A72_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH
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msr CORTEX_A72_CPUACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_a72_859971_wa
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func check_errata_859971
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mov x1, #0x03
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b cpu_rev_var_ls
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endfunc check_errata_859971
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A72.
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* -------------------------------------------------
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*/
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func cortex_a72_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A72_859971
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mov x0, x18
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bl errata_a72_859971_wa
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
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adr x0, workaround_mmu_runtime_exceptions
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msr vbar_el3, x0
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#endif
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A72_ECTLR_EL1
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orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
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msr CORTEX_A72_ECTLR_EL1, x0
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isb
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ret x19
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endfunc cortex_a72_reset_func
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/* ----------------------------------------------------
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* The CPU Ops core power down function for Cortex-A72.
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* ----------------------------------------------------
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*/
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func cortex_a72_core_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_dcache
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/* ---------------------------------------------
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* Disable the L2 prefetches.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_l2_prefetch
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/* ---------------------------------------------
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* Disable the load-store hardware prefetcher.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_hw_prefetcher
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_smp
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/* ---------------------------------------------
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* Force the debug interfaces to be quiescent
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a72_disable_ext_debug
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endfunc cortex_a72_core_pwr_dwn
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/* -------------------------------------------------------
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* The CPU Ops cluster power down function for Cortex-A72.
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* -------------------------------------------------------
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*/
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func cortex_a72_cluster_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_dcache
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/* ---------------------------------------------
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* Disable the L2 prefetches.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_l2_prefetch
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/* ---------------------------------------------
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* Disable the load-store hardware prefetcher.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_hw_prefetcher
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#if !SKIP_A72_L1_FLUSH_PWR_DWN
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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#endif
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* -------------------------------------------------
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* Flush the L2 caches.
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* -------------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level2
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_smp
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/* ---------------------------------------------
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* Force the debug interfaces to be quiescent
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a72_disable_ext_debug
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endfunc cortex_a72_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A72. Must follow AAPCS.
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*/
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func cortex_a72_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A72_859971, cortex_a72, 859971
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a72_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cortex_a72 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a72_regs, "aS"
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cortex_a72_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", ""
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func cortex_a72_cpu_reg_dump
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adr x6, cortex_a72_regs
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mrs x8, CORTEX_A72_ECTLR_EL1
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mrs x9, CORTEX_A72_MERRSR_EL1
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mrs x10, CORTEX_A72_L2MERRSR_EL1
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ret
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endfunc cortex_a72_cpu_reg_dump
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declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \
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cortex_a72_reset_func, \
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cortex_a72_core_pwr_dwn, \
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cortex_a72_cluster_pwr_dwn
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