Dimitris Papastamos f62ad32269 Workaround for CVE-2017-5715 on Cortex A57 and A72 ... Invalidate the Branch Target Buffer (BTB) on entry to EL3 by disabling and enabling the MMU. To achieve this without performing any branch instruction, a per-cpu vbar is installed which executes the workaround and then branches off to the corresponding vector entry in the main vector table. A side effect of this change is that the main vbar is configured before any reset handling. This is to allow the per-cpu reset function to override the vbar setting. This workaround is enabled by default on the affected CPUs. Change-Id: I97788d38463a5840a410e3cea85ed297a1678265 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>		2018-01-11 10:26:15 +00:00
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bl1	FWU: Introduce FWU_SMC_IMAGE_RESET	2017-06-01 14:52:12 +01:00
bl31	BL31: Program Priority Mask for SMC handling	2017-11-13 07:49:30 +00:00
bl32	bl32: add secure interrupt handling in AArch32 sp_min	2017-08-09 15:48:53 +02:00
common	Workaround for CVE-2017-5715 on Cortex A57 and A72	2018-01-11 10:26:15 +00:00
drivers	Merge pull request #1145 from etienne-lms/rfc-armv7-2	2017-11-23 23:41:24 +00:00
lib	Merge pull request #1178 from davidcunado-arm/dc/enable_sve	2017-12-11 12:29:47 +00:00
plat	Move TSP to TZC secured DRAM	2018-01-03 10:21:26 +00:00
services	SPM: Rename SP_COMMUNICATE macros	2017-12-05 10:31:21 +00:00
tools_share	Support Trusted OS firmware extra images in TF tools	2017-08-09 18:06:05 +08:00