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https://github.com/ARM-software/arm-trusted-firmware.git
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f5cb15b0c8
The Raspberry Pi 4 is a single board computer with four Cortex-A72 cores. From a TF-A perspective it is quite similar to the Raspberry Pi 3, although it comes with more memory (up to 4GB) and has a GIC. This initial port though differs quite a lot from the existing rpi3 platform port, mainly due to taking a much simpler and more robust approach to loading the non-secure payload: The GPU firmware of the SoC, which is responsible for initial platform setup (including DRAM initialisation), already loads the kernel, device tree and the "armstub" into DRAM. We take advantage of this, by placing just a BL31 component into the armstub8.bin component, which will be executed first, in AArch64 EL3. The non-secure payload can be a kernel or a boot loader (U-Boot or EDK-2), disguised as the "kernel" image and loaded by the GPU firmware. So this is just a BL31-only port, which directly drops into EL2 and executes whatever has been loaded as the "kernel" image, handing over the DTB address in x0. Change-Id: I636f4d1f661821566ad9e341d69ba36f6bbfb546 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
162 lines
5 KiB
C
162 lines
5 KiB
C
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#include <common/bl_common.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#include <plat/common/platform.h>
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#include <drivers/arm/gicv2.h>
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#include <rpi_shared.h>
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static const gicv2_driver_data_t rpi4_gic_data = {
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.gicd_base = RPI4_GIC_GICD_BASE,
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.gicc_base = RPI4_GIC_GICC_BASE,
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};
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/*
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* To be filled by the code below. At the moment BL32 is not supported.
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* In the future these might be passed down from BL2.
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*/
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* the security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type. A NULL pointer is returned
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* if the image does not exist.
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******************************************************************************/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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assert(sec_state_is_valid(type) != 0);
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next_image_info = (type == NON_SECURE)
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? &bl33_image_ep_info : &bl32_image_ep_info;
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/* None of the images can have 0x0 as the entrypoint. */
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if (next_image_info->pc) {
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return next_image_info;
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} else {
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return NULL;
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}
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}
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static void ldelay(register_t delay)
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{
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__asm__ volatile (
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"1:\tcbz %0, 2f\n\t"
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"sub %0, %0, #1\n\t"
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"b 1b\n"
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"2:"
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: "=&r" (delay) : "0" (delay)
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);
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}
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/*******************************************************************************
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* Perform any BL31 early platform setup. Here is an opportunity to copy
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* parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before
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* they are lost (potentially). This needs to be done before the MMU is
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* initialized so that the memory layout can be used while creating page
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* tables. BL2 has flushed this information to memory, so we are guaranteed
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* to pick up good data.
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******************************************************************************/
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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uint32_t div_reg;
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/*
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* LOCAL_CONTROL:
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* Bit 9 clear: Increment by 1 (vs. 2).
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* Bit 8 clear: Timer source is 19.2MHz crystal (vs. APB).
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*/
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mmio_write_32(RPI4_LOCAL_CONTROL_BASE_ADDRESS, 0);
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/* LOCAL_PRESCALER; divide-by (0x80000000 / register_val) == 1 */
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mmio_write_32(RPI4_LOCAL_CONTROL_PRESCALER, 0x80000000);
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/* Early GPU firmware revisions need a little break here. */
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ldelay(100000);
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/*
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* Initialize the console to provide early debug support.
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* Different GPU firmware revisions set up the VPU divider differently,
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* so read the actual divider register to learn the UART base clock
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* rate. The divider is encoded as a 12.12 fixed point number, but we
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* just care about the integer part of it.
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*/
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div_reg = mmio_read_32(RPI4_CLOCK_BASE + RPI4_VPU_CLOCK_DIVIDER);
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div_reg = (div_reg >> 12) & 0xfff;
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if (div_reg == 0)
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div_reg = 1;
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rpi3_console_init(PLAT_RPI4_VPU_CLK_RATE / div_reg);
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#if RPI3_DIRECT_LINUX_BOOT
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bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
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bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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# if RPI3_BL33_IN_AARCH32
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/*
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* According to the file ``Documentation/arm/Booting`` of the Linux
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* kernel tree, Linux expects:
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* r0 = 0
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* r1 = machine type number, optional in DT-only platforms (~0 if so)
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* r2 = Physical address of the device tree blob
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*/
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VERBOSE("rpi4: Preparing to boot 32-bit Linux kernel\n");
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bl33_image_ep_info.args.arg0 = 0U;
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bl33_image_ep_info.args.arg1 = ~0U;
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bl33_image_ep_info.args.arg2 = (u_register_t) RPI3_PRELOADED_DTB_BASE;
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# else
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/*
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* According to the file ``Documentation/arm64/booting.txt`` of the
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* Linux kernel tree, Linux expects the physical address of the device
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* tree blob (DTB) in x0, while x1-x3 are reserved for future use and
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* must be 0.
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*/
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VERBOSE("rpi4: Preparing to boot 64-bit Linux kernel\n");
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bl33_image_ep_info.args.arg0 = (u_register_t) RPI3_PRELOADED_DTB_BASE;
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bl33_image_ep_info.args.arg1 = 0ULL;
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bl33_image_ep_info.args.arg2 = 0ULL;
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bl33_image_ep_info.args.arg3 = 0ULL;
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# endif /* RPI3_BL33_IN_AARCH32 */
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#endif /* RPI3_DIRECT_LINUX_BOOT */
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}
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void bl31_plat_arch_setup(void)
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{
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rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE,
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BL_CODE_BASE, BL_CODE_END,
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BL_RO_DATA_BASE, BL_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
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#endif
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);
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enable_mmu_el3(0);
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}
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void bl31_platform_setup(void)
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{
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/* Configure the interrupt controller */
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gicv2_driver_init(&rpi4_gic_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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