mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-26 14:55:16 +00:00
7c0a1877e7
At the moment the UART input clock rate is hard coded at compile time. This works as long as the GPU firmware always sets up the same rate, which does not seem to be true for the Raspberry Pi 4. In preparation for being able to change this at runtime, add a base clock parameter to the console setup function. This is still hardcoded for the Raspberry Pi 3. Change-Id: I398bc2f1e9b46f7af9a84cb0b33cbe8e78f2d900 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#include <rpi_shared.h>
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/* Data structure which holds the extents of the trusted SRAM for BL1 */
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static meminfo_t bl1_tzram_layout;
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meminfo_t *bl1_plat_sec_mem_layout(void)
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{
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return &bl1_tzram_layout;
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}
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/*******************************************************************************
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* Perform any BL1 specific platform actions.
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******************************************************************************/
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void bl1_early_platform_setup(void)
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{
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/* use the 19.2 MHz clock for the architected timer */
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mmio_write_32(RPI3_INTC_BASE_ADDRESS + RPI3_INTC_CONTROL_OFFSET, 0);
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mmio_write_32(RPI3_INTC_BASE_ADDRESS + RPI3_INTC_PRESCALER_OFFSET,
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0x80000000);
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/* Initialize the console to provide early debug support */
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rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ);
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/* Allow BL1 to see the whole Trusted RAM */
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bl1_tzram_layout.total_base = BL_RAM_BASE;
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bl1_tzram_layout.total_size = BL_RAM_SIZE;
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}
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/******************************************************************************
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* Perform the very early platform specific architecture setup. This only
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* does basic initialization. Later architectural setup (bl1_arch_setup())
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* does not do anything platform specific.
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*****************************************************************************/
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void bl1_plat_arch_setup(void)
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{
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rpi3_setup_page_tables(bl1_tzram_layout.total_base,
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bl1_tzram_layout.total_size,
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BL_CODE_BASE, BL1_CODE_END,
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BL1_RO_DATA_BASE, BL1_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
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#endif
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);
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enable_mmu_el3(0);
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}
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void bl1_platform_setup(void)
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{
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uint32_t __unused rev;
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int __unused rc;
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rc = rpi3_vc_hardware_get_board_revision(&rev);
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if (rc == 0) {
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const char __unused *model, __unused *info;
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switch (rev) {
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case 0xA02082:
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model = "Raspberry Pi 3 Model B";
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info = "(1GB, Sony, UK)";
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break;
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case 0xA22082:
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model = "Raspberry Pi 3 Model B";
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info = "(1GB, Embest, China)";
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break;
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case 0xA020D3:
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model = "Raspberry Pi 3 Model B+";
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info = "(1GB, Sony, UK)";
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break;
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default:
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model = "Unknown";
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info = "(Unknown)";
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ERROR("rpi3: Unknown board revision 0x%08x\n", rev);
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break;
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}
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NOTICE("rpi3: Detected: %s %s [0x%08x]\n", model, info, rev);
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} else {
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ERROR("rpi3: Unable to detect board revision\n");
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}
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/* Initialise the IO layer and register platform IO devices */
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plat_rpi3_io_setup();
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}
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