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0b64c19485
Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
27 lines
1,017 B
C
27 lines
1,017 B
C
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A17_H
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#define CORTEX_A17_H
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#include <lib/utils_def.h>
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/*******************************************************************************
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* Cortex-A17 midr with version/revision set to 0
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******************************************************************************/
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#define CORTEX_A17_MIDR U(0x410FC0E0)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A17_ACTLR_SMP_BIT (U(1) << 6)
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/*******************************************************************************
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* Implementation defined register specific definitions.
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******************************************************************************/
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#define CORTEX_A17_IMP_DEF_REG1 p15, 0, c15, c0, 1
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#endif /* CORTEX_A17_H */
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