mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-15 00:54:22 +00:00
96d07af402
This patch implements the pwr_domain_off_early handler for Tegra platforms. Powering off the boot core on some Tegra platforms is not allowed and the SOC specific helper functions for Tegra194, Tegra210 and Tegra186 implement this restriction. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I9d06e0eee12314764adb0422e023a5bec6ed9c1e
446 lines
12 KiB
ArmAsm
446 lines
12 KiB
ArmAsm
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a57.h>
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#include <cpu_macros.S>
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#include <platform_def.h>
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#include <tegra_def.h>
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#include <tegra_platform.h>
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#define MIDR_PN_CORTEX_A57 0xD07
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/*******************************************************************************
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* Implementation defined ACTLR_EL3 bit definitions
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******************************************************************************/
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#define ACTLR_ELx_L2ACTLR_BIT (U(1) << 6)
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#define ACTLR_ELx_L2ECTLR_BIT (U(1) << 5)
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#define ACTLR_ELx_L2CTLR_BIT (U(1) << 4)
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#define ACTLR_ELx_CPUECTLR_BIT (U(1) << 1)
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#define ACTLR_ELx_CPUACTLR_BIT (U(1) << 0)
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#define ACTLR_ELx_ENABLE_ALL_ACCESS (ACTLR_ELx_L2ACTLR_BIT | \
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ACTLR_ELx_L2ECTLR_BIT | \
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ACTLR_ELx_L2CTLR_BIT | \
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ACTLR_ELx_CPUECTLR_BIT | \
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ACTLR_ELx_CPUACTLR_BIT)
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/* Global functions */
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_get_my_entrypoint
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.globl plat_secondary_cold_boot_setup
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.globl platform_mem_init
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.weak plat_core_pos_by_mpidr
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.globl tegra_secure_entrypoint
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.globl plat_reset_handler
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/* Global variables */
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.globl tegra_sec_entry_point
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.globl ns_image_entrypoint
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.globl tegra_bl31_phys_base
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.globl tegra_console_base
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/* ---------------------
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* Common CPU init code
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* ---------------------
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*/
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.macro cpu_init_common
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/* ------------------------------------------------
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* We enable procesor retention, L2/CPUECTLR NS
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* access and ECC/Parity protection for A57 CPUs
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* ------------------------------------------------
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*/
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mrs x0, midr_el1
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mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT)
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and x0, x0, x1
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lsr x0, x0, #MIDR_PN_SHIFT
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cmp x0, #MIDR_PN_CORTEX_A57
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b.ne 1f
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/* ---------------------------
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* Enable processor retention
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* ---------------------------
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*/
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mrs x0, CORTEX_A57_L2ECTLR_EL1
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mov x1, #RETENTION_ENTRY_TICKS_512
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bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK
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orr x0, x0, x1
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msr CORTEX_A57_L2ECTLR_EL1, x0
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isb
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mrs x0, CORTEX_A57_ECTLR_EL1
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mov x1, #RETENTION_ENTRY_TICKS_512
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bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK
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orr x0, x0, x1
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msr CORTEX_A57_ECTLR_EL1, x0
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isb
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/* -------------------------------------------------------
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* Enable L2 and CPU ECTLR RW access from non-secure world
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* -------------------------------------------------------
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*/
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mrs x0, actlr_el3
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mov x1, #ACTLR_ELx_ENABLE_ALL_ACCESS
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orr x0, x0, x1
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msr actlr_el3, x0
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mrs x0, actlr_el2
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mov x1, #ACTLR_ELx_ENABLE_ALL_ACCESS
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orr x0, x0, x1
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msr actlr_el2, x0
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isb
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/* --------------------------------
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* Enable the cycle count register
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* --------------------------------
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*/
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1: mrs x0, pmcr_el0
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ubfx x0, x0, #11, #5 // read PMCR.N field
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mov x1, #1
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lsl x0, x1, x0
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sub x0, x0, #1 // mask of event counters
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orr x0, x0, #0x80000000 // disable overflow intrs
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msr pmintenclr_el1, x0
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msr pmuserenr_el0, x1 // enable user mode access
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/* ----------------------------------------------------------------
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* Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count
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* register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ
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* registers from EL0.
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* ----------------------------------------------------------------
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*/
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mrs x0, cntkctl_el1
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orr x0, x0, #EL0VCTEN_BIT
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msr cntkctl_el1, x0
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.endm
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/* -----------------------------------------------------
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* bool plat_is_my_cpu_primary(void);
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*
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* This function checks if this is the Primary CPU
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*
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* Registers clobbered: x0, x1
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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adr x1, tegra_primary_cpu_mpid
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ldr x1, [x1]
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cmp x0, x1
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cset x0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* ----------------------------------------------------------
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* unsigned int plat_my_core_pos(void);
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*
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* result: CorePos = CoreId + (ClusterId * cpus per cluster)
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* Registers clobbered: x0, x8
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* ----------------------------------------------------------
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*/
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func plat_my_core_pos
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mov x8, x30
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mrs x0, mpidr_el1
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bl plat_core_pos_by_mpidr
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ret x8
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned long plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between
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* a cold and warm boot. If the tegra_sec_entry_point for
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* this CPU is present, then it's a warm boot.
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*
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* -----------------------------------------------------
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*/
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func plat_get_my_entrypoint
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adr x1, tegra_sec_entry_point
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ldr x0, [x1]
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ret
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset. Right
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* now this is a stub function.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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mov x0, #0
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ret
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endfunc plat_secondary_cold_boot_setup
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/* --------------------------------------------------------
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* void platform_mem_init (void);
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*
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* Any memory init, relocation to be done before the
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* platform boots. Called very early in the boot process.
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* --------------------------------------------------------
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*/
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func platform_mem_init
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mov x0, #0
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ret
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endfunc platform_mem_init
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/* ---------------------------------------------------
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* Function to handle a platform reset and store
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* input parameters passed by BL2.
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* ---------------------------------------------------
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*/
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func plat_reset_handler
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/* ----------------------------------------------------
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* Verify if we are running from BL31_BASE address
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* ----------------------------------------------------
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*/
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adr x18, bl31_entrypoint
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mov x17, #BL31_BASE
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cmp x18, x17
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b.eq 1f
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/* ----------------------------------------------------
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* Copy the entire BL31 code to BL31_BASE if we are not
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* running from it already
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* ----------------------------------------------------
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*/
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mov x0, x17
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mov x1, x18
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adr x2, __RELA_END__
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sub x2, x2, x18
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_loop16:
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cmp x2, #16
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b.lo _loop1
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ldp x3, x4, [x1], #16
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stp x3, x4, [x0], #16
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sub x2, x2, #16
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b _loop16
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/* copy byte per byte */
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_loop1:
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cbz x2, _end
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ldrb w3, [x1], #1
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strb w3, [x0], #1
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subs x2, x2, #1
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b.ne _loop1
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/* ----------------------------------------------------
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* Jump to BL31_BASE and start execution again
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* ----------------------------------------------------
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*/
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_end: mov x0, x20
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mov x1, x21
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br x17
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1:
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/* -----------------------------------
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* derive and save the phys_base addr
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* -----------------------------------
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*/
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adr x17, tegra_bl31_phys_base
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ldr x18, [x17]
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cbnz x18, 1f
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adr x18, bl31_entrypoint
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str x18, [x17]
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/* -----------------------------------
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* save the boot CPU MPID value
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* -----------------------------------
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*/
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mrs x0, mpidr_el1
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adr x1, tegra_primary_cpu_mpid
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str x0, [x1]
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1: cpu_init_common
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ret
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endfunc plat_reset_handler
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/* ------------------------------------------------------
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* int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
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*
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* This function implements a part of the critical
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* interface between the psci generic layer and the
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* platform that allows the former to query the platform
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* to convert an MPIDR to a unique linear index. An error
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* code (-1) is returned in case the MPIDR is invalid.
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*
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* Clobbers: x0-x3
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* ------------------------------------------------------
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*/
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func plat_core_pos_by_mpidr
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lsr x1, x0, #MPIDR_AFF0_SHIFT
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and x1, x1, #MPIDR_AFFLVL_MASK /* core id */
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lsr x2, x0, #MPIDR_AFF1_SHIFT
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and x2, x2, #MPIDR_AFFLVL_MASK /* cluster id */
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/* core_id >= PLATFORM_MAX_CPUS_PER_CLUSTER */
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mov x0, #-1
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cmp x1, #(PLATFORM_MAX_CPUS_PER_CLUSTER - 1)
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b.gt 1f
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/* cluster_id >= PLATFORM_CLUSTER_COUNT */
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cmp x2, #(PLATFORM_CLUSTER_COUNT - 1)
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b.gt 1f
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/* CorePos = CoreId + (ClusterId * cpus per cluster) */
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mov x3, #PLATFORM_MAX_CPUS_PER_CLUSTER
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mul x3, x3, x2
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add x0, x1, x3
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1:
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ret
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endfunc plat_core_pos_by_mpidr
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/* ----------------------------------------
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* Secure entrypoint function for CPU boot
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* ----------------------------------------
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*/
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func tegra_secure_entrypoint _align=6
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#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT
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/* --------------------------------------------------------
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* Skip the invalidate BTB workaround for Tegra210B01 SKUs.
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* --------------------------------------------------------
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*/
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mov x0, #TEGRA_MISC_BASE
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add x0, x0, #HARDWARE_REVISION_OFFSET
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ldr w1, [x0]
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lsr w1, w1, #CHIP_ID_SHIFT
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and w1, w1, #CHIP_ID_MASK
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cmp w1, #TEGRA_CHIPID_TEGRA21 /* T210? */
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b.ne 2f
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ldr w1, [x0]
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lsr w1, w1, #MAJOR_VERSION_SHIFT
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and w1, w1, #MAJOR_VERSION_MASK
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cmp w1, #0x02 /* T210 B01? */
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b.eq 2f
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/* -------------------------------------------------------
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* Invalidate BTB along with I$ to remove any stale
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* entries from the branch predictor array.
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* -------------------------------------------------------
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*/
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mrs x0, CORTEX_A57_CPUACTLR_EL1
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orr x0, x0, #1
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msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */
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dsb sy
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isb
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ic iallu /* actual invalidate */
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dsb sy
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isb
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mrs x0, CORTEX_A57_CPUACTLR_EL1
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bic x0, x0, #1
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msr CORTEX_A57_CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */
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dsb sy
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isb
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.rept 7
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nop /* wait */
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.endr
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/* -----------------------------------------------
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* Extract OSLK bit and check if it is '1'. This
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* bit remains '0' for A53 on warm-resets. If '1',
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* turn off regional clock gating and request warm
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* reset.
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* -----------------------------------------------
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*/
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mrs x0, oslsr_el1
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and x0, x0, #2
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mrs x1, mpidr_el1
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bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */
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b.eq restore_oslock
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mov x0, xzr
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msr oslar_el1, x0 /* os lock stays 0 across warm reset */
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mov x3, #3
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movz x4, #0x8000, lsl #48
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msr CORTEX_A57_CPUACTLR_EL1, x4 /* turn off RCG */
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isb
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msr rmr_el3, x3 /* request warm reset */
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isb
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dsb sy
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1: wfi
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b 1b
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/* --------------------------------------------------
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* These nops are here so that speculative execution
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* won't harm us before we are done with warm reset.
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* --------------------------------------------------
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*/
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.rept 65
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nop
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.endr
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2:
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/* --------------------------------------------------
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* Do not insert instructions here
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* --------------------------------------------------
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*/
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#endif
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/* --------------------------------------------------
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* Restore OS Lock bit
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* --------------------------------------------------
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*/
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restore_oslock:
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mov x0, #1
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msr oslar_el1, x0
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/* --------------------------------------------------
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* Get secure world's entry point and jump to it
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* --------------------------------------------------
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*/
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bl plat_get_my_entrypoint
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br x0
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endfunc tegra_secure_entrypoint
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.data
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.align 3
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/* --------------------------------------------------
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* CPU Secure entry point - resume from suspend
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* --------------------------------------------------
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*/
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tegra_sec_entry_point:
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.quad 0
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/* --------------------------------------------------
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* NS world's cold boot entry point
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* --------------------------------------------------
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*/
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ns_image_entrypoint:
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.quad 0
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/* --------------------------------------------------
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* BL31's physical base address
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* --------------------------------------------------
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*/
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tegra_bl31_phys_base:
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.quad 0
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/* --------------------------------------------------
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* UART controller base for console init
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* --------------------------------------------------
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*/
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tegra_console_base:
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.quad 0
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/* --------------------------------------------------
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* MPID value for the boot CPU
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* --------------------------------------------------
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*/
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tegra_primary_cpu_mpid:
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.quad 0
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