Soby Mathew f4f1ae777b Demonstrate model for routing IRQs to EL3 ... This patch provides an option to specify a interrupt routing model where non-secure interrupts (IRQs) are routed to EL3 instead of S-EL1. When such an interrupt occurs, the TSPD arranges a return to the normal world after saving any necessary context. The interrupt routing model to route IRQs to EL3 is enabled only during STD SMC processing. Thus the pre-emption of S-EL1 is disabled during Fast SMC and Secure Interrupt processing. A new build option TSPD_ROUTE_NS_INT_EL3 is introduced to change the non secure interrupt target execution level to EL3. Fixes ARM-software/tf-issues#225 Change-Id: Ia1e779fbbb6d627091e665c73fa6315637cfdd32		2015-01-26 15:29:32 +00:00
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diagrams	Document design of the Interrupt Mangement Framework	2014-06-03 18:42:14 +01:00
change-log.md	Documentation for version 1.0	2014-08-28 14:24:54 +01:00
cpu-specific-build-macros.md	Create Table of Content links in markdown files	2015-01-07 15:01:07 +01:00
firmware-design.md	Increment the PSCI VERSION to 1.0	2015-01-26 12:49:32 +00:00
interrupt-framework-design.md	Create Table of Content links in markdown files	2015-01-07 15:01:07 +01:00
optee-dispatcher.md	Add opteed based on tspd	2014-09-16 11:51:54 -07:00
porting-guide.md	Validate power_state and entrypoint when executing PSCI calls	2015-01-23 18:36:15 +00:00
rt-svc-writers-guide.md	Create Table of Content links in markdown files	2015-01-07 15:01:07 +01:00
user-guide.md	Demonstrate model for routing IRQs to EL3	2015-01-26 15:29:32 +00:00