arm-trusted-firmware/plat/intel/soc
Sieu Mun Tang f4aaa9fd6e fix(intel): update DDR range checking for Agilex5
Update DDR range checking for Agilex when total max size of
DRAM_BASE and DRAM_SIZE overflow unsigned 64bit.

Change-Id: Iaecfa5daae48da0af46cc1831d10c0e6a79613c2
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
2023-12-15 11:15:10 +08:00
..
agilex chore: remove MULTI_CONSOLE_API references 2023-09-12 15:28:36 +02:00
agilex5 chore: remove MULTI_CONSOLE_API references 2023-09-12 15:28:36 +02:00
common fix(intel): update DDR range checking for Agilex5 2023-12-15 11:15:10 +08:00
n5x chore: remove MULTI_CONSOLE_API references 2023-09-12 15:28:36 +02:00
stratix10 feat(intel): platform enablement for Agilex5 SoC FPGA 2023-07-05 10:11:22 +08:00