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f363deb6d4
Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
26 lines
886 B
C
26 lines
886 B
C
/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A77_H
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#define CORTEX_A77_H
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#include <lib/utils_def.h>
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/* Cortex-A77 MIDR */
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#define CORTEX_A77_MIDR U(0x410FD0D0)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
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#endif /* CORTEX_A77_H */
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