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f33b2433f5
The system configuration controller is mainly used to manage the compensation cell and other IOs and system related settings. The SYSCFG driver is in charge of configuring masters on the interconnect, IO compensation, low voltage boards, or pull-ups for boot pins. All other configurations should be handled in Linux drivers requiring it. Device tree files are also updated to manage vdd-supply regulator. Change-Id: I10fb513761a7d1f2b7afedca9c723ad9d1bccf42 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
315 lines
7.3 KiB
Text
315 lines
7.3 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved
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* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/reset/stm32mp1-resets.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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intc: interrupt-controller@a0021000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xa0021000 0x1000>,
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<0xa0022000 0x2000>;
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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clk_csi: clk-csi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <4000000>;
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};
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clk_i2s_ckin: i2s_ckin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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clk_dsi_phy: ck_dsi_phy {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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usart2: serial@4000e000 {
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compatible = "st,stm32h7-uart";
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reg = <0x4000e000 0x400>;
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clocks = <&rcc USART2_K>;
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resets = <&rcc USART2_R>;
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status = "disabled";
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};
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usart3: serial@4000f000 {
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compatible = "st,stm32h7-uart";
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reg = <0x4000f000 0x400>;
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clocks = <&rcc USART3_K>;
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resets = <&rcc USART3_R>;
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status = "disabled";
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};
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uart4: serial@40010000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40010000 0x400>;
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clocks = <&rcc UART4_K>;
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resets = <&rcc UART4_R>;
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status = "disabled";
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};
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uart5: serial@40011000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40011000 0x400>;
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clocks = <&rcc UART5_K>;
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resets = <&rcc UART5_R>;
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status = "disabled";
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};
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uart7: serial@40018000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40018000 0x400>;
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clocks = <&rcc UART7_K>;
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resets = <&rcc UART7_R>;
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status = "disabled";
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};
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uart8: serial@40019000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40019000 0x400>;
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clocks = <&rcc UART8_K>;
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resets = <&rcc UART8_R>;
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status = "disabled";
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};
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usart6: serial@44003000 {
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compatible = "st,stm32h7-uart";
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reg = <0x44003000 0x400>;
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clocks = <&rcc USART6_K>;
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resets = <&rcc USART6_R>;
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status = "disabled";
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};
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sdmmc3: sdmmc@48004000 {
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compatible = "st,stm32-sdmmc2";
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reg = <0x48004000 0x400>, <0x48005000 0x400>;
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clocks = <&rcc SDMMC3_K>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC3_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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status = "disabled";
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};
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rcc: rcc@50000000 {
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compatible = "st,stm32mp1-rcc", "syscon";
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reg = <0x50000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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pwr: pwr@50001000 {
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compatible = "st,stm32mp1-pwr", "syscon", "simple-mfd";
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reg = <0x50001000 0x400>;
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};
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exti: interrupt-controller@5000d000 {
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compatible = "st,stm32mp1-exti", "syscon";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000d000 0x400>;
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/* exti_pwr is an extra interrupt controller used for
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* EXTI 55 to 60. It's mapped on pwr interrupt
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* controller.
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*/
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exti_pwr: exti-pwr {
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&pwr>;
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st,irq-number = <6>;
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};
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};
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syscfg: syscon@50020000 {
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compatible = "st,stm32mp157-syscfg", "syscon";
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reg = <0x50020000 0x400>;
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clocks = <&rcc SYSCFG>;
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};
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rng1: rng@54003000 {
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compatible = "st,stm32-rng";
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reg = <0x54003000 0x400>;
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clocks = <&rcc RNG1_K>;
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resets = <&rcc RNG1_R>;
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status = "disabled";
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};
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fmc: nand-controller@58002000 {
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compatible = "st,stm32mp15-fmc2";
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reg = <0x58002000 0x1000>,
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<0x80000000 0x1000>,
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<0x88010000 0x1000>,
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<0x88020000 0x1000>,
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<0x81000000 0x1000>,
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<0x89010000 0x1000>,
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<0x89020000 0x1000>;
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clocks = <&rcc FMC_K>;
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resets = <&rcc FMC_R>;
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status = "disabled";
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};
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qspi: qspi@58003000 {
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compatible = "st,stm32f469-qspi";
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reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
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reg-names = "qspi", "qspi_mm";
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clocks = <&rcc QSPI_K>;
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resets = <&rcc QSPI_R>;
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status = "disabled";
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};
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sdmmc1: sdmmc@58005000 {
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compatible = "st,stm32-sdmmc2";
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reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
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clocks = <&rcc SDMMC1_K>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC1_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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status = "disabled";
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};
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sdmmc2: sdmmc@58007000 {
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compatible = "st,stm32-sdmmc2";
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reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
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clocks = <&rcc SDMMC2_K>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC2_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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status = "disabled";
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};
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iwdg2: watchdog@5a002000 {
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compatible = "st,stm32mp1-iwdg";
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reg = <0x5a002000 0x400>;
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clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
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clock-names = "pclk", "lsi";
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status = "disabled";
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};
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usart1: serial@5c000000 {
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compatible = "st,stm32h7-uart";
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reg = <0x5c000000 0x400>;
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interrupt-names = "event", "wakeup";
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interrupts-extended = <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<&exti 26 1>;
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clocks = <&rcc USART1_K>;
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resets = <&rcc USART1_R>;
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status = "disabled";
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};
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spi6: spi@5c001000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32h7-spi";
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reg = <0x5c001000 0x400>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc SPI6_K>;
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resets = <&rcc SPI6_R>;
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status = "disabled";
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};
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i2c4: i2c@5c002000 {
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compatible = "st,stm32f7-i2c";
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reg = <0x5c002000 0x400>;
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interrupt-names = "event", "error", "wakeup";
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interrupts-extended = <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<&exti 24 1>;
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clocks = <&rcc I2C4_K>;
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resets = <&rcc I2C4_R>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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rtc: rtc@5c004000 {
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compatible = "st,stm32mp1-rtc";
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reg = <0x5c004000 0x400>;
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clocks = <&rcc RTCAPB>, <&rcc RTC>;
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clock-names = "pclk", "rtc_ck";
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interrupts-extended = <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<&exti 19 1>;
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status = "disabled";
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};
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bsec: nvmem@5c005000 {
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compatible = "st,stm32mp15-bsec";
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reg = <0x5c005000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ts_cal1: calib@5c {
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reg = <0x5c 0x2>;
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};
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ts_cal2: calib@5e {
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reg = <0x5e 0x2>;
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};
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};
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i2c6: i2c@5c009000 {
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compatible = "st,stm32f7-i2c";
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reg = <0x5c009000 0x400>;
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interrupt-names = "event", "error", "wakeup";
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interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<&exti 54 1>;
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clocks = <&rcc I2C6_K>;
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resets = <&rcc I2C6_R>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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};
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