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f1722b693d
This patch fixes up the AArch64 assembly code to use adrp/adr instructions instead of ldr instruction for reference to symbols. This allows these assembly sequences to be Position Independant. Note that the the reference to sizes have been replaced with calculation of size at runtime. This is because size is a constant value and does not depend on execution address and using PC relative instructions for loading them makes them relative to execution address. Also we cannot use `ldr` instruction to load size as it generates a dynamic relocation entry which must *not* be fixed up and it is difficult for a dynamic loader to differentiate which entries need to be skipped. Change-Id: I8bf4ed5c58a9703629e5498a27624500ef40a836 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
96 lines
2 KiB
ArmAsm
96 lines
2 KiB
ArmAsm
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <xlat_tables_v2.h>
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.global enable_mmu_direct_el1
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.global enable_mmu_direct_el2
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.global enable_mmu_direct_el3
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/* Macros to read and write to system register for a given EL. */
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.macro _msr reg_name, el, gp_reg
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msr \reg_name\()_el\()\el, \gp_reg
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.endm
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.macro _mrs gp_reg, reg_name, el
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mrs \gp_reg, \reg_name\()_el\()\el
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.endm
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.macro tlbi_invalidate_all el
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.if \el == 1
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TLB_INVALIDATE(vmalle1)
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.elseif \el == 2
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TLB_INVALIDATE(alle2)
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.elseif \el == 3
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TLB_INVALIDATE(alle3)
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.else
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.error "EL must be 1, 2 or 3"
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.endif
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.endm
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/* void enable_mmu_direct_el<x>(unsigned int flags) */
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.macro define_mmu_enable_func el
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func enable_mmu_direct_\()el\el
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#if ENABLE_ASSERTIONS
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_mrs x1, sctlr, \el
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tst x1, #SCTLR_M_BIT
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ASM_ASSERT(eq)
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#endif
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/* Invalidate all TLB entries */
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tlbi_invalidate_all \el
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mov x7, x0
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adrp x0, mmu_cfg_params
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add x0, x0, :lo12:mmu_cfg_params
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/* MAIR */
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ldr x1, [x0, #(MMU_CFG_MAIR << 3)]
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_msr mair, \el, x1
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/* TCR */
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ldr x2, [x0, #(MMU_CFG_TCR << 3)]
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_msr tcr, \el, x2
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/* TTBR */
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ldr x3, [x0, #(MMU_CFG_TTBR0 << 3)]
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_msr ttbr0, \el, x3
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/*
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* Ensure all translation table writes have drained into memory, the TLB
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* invalidation is complete, and translation register writes are
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* committed before enabling the MMU
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*/
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dsb ish
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isb
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/* Set and clear required fields of SCTLR */
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_mrs x4, sctlr, \el
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mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT
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orr x4, x4, x5
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/* Additionally, amend SCTLR fields based on flags */
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bic x5, x4, #SCTLR_C_BIT
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tst x7, #DISABLE_DCACHE
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csel x4, x5, x4, ne
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_msr sctlr, \el, x4
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isb
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ret
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endfunc enable_mmu_direct_\()el\el
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.endm
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/*
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* Define MMU-enabling functions for EL1 and EL3:
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*
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* enable_mmu_direct_el1
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* enable_mmu_direct_el3
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*/
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define_mmu_enable_func 1
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define_mmu_enable_func 2
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define_mmu_enable_func 3
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