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765ed9fc55
Define Qemu AArch32 implementation for some platform functions (core position, secondary boot cores, crash console). These are derived from the AArch64 implementation. BL31 on Qemu is needed only for ARMv8 and later. On ARMv7, BL32 is the first executable image after BL2. Support SP_MIN and OP-TEE as BL32: create a sp_min make script target in Qemu, define mapping for IMAGE_BL32 Minor fix Qemu return value type for plat_get_ns_image_entrypoint(). Qemu model for the Cortex-A15 does not support the virtualization extension although the core expects it. To overcome the issue, Qemu ARMv7 configuration set ARCH_SUPPORTS_VIRTUALIZATION to 0. Add missing AArch32 assembly macro arm_print_gic_regs from ARM platform used by the Qemu platform. Qemu Cortex-A15 model integrates a single cluster with up to 4 cores. Change-Id: I65b44399071d6f5aa40d5183be11422b9ee9ca15 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
150 lines
4.7 KiB
C
150 lines
4.7 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <desc_image_load.h>
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#include <platform.h>
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#include <platform_def.h>
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/*******************************************************************************
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* Following descriptor provides BL image/ep information that gets used
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* by BL2 to load the images and also subset of this information is
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* passed to next BL image. The image loading sequence is managed by
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* populating the images in required loading order. The image execution
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* sequence is managed by populating the `next_handoff_image_id` with
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* the next executable image id.
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******************************************************************************/
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static bl_mem_params_node_t bl2_mem_params_descs[] = {
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#ifdef EL3_PAYLOAD_BASE
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/* Fill EL3 payload related information (BL31 is EL3 payload) */
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{ .image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = EL3_PAYLOAD_BASE,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
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IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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#else /* EL3_PAYLOAD_BASE */
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#ifdef AARCH64
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/* Fill BL31 related information */
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{ .image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = BL31_BASE,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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# if DEBUG
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.ep_info.args.arg1 = QEMU_BL31_PLAT_PARAM_VAL,
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# endif
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
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IMAGE_ATTRIB_PLAT_SETUP),
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.image_info.image_base = BL31_BASE,
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.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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# ifdef QEMU_LOAD_BL32
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.next_handoff_image_id = BL32_IMAGE_ID,
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# else
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.next_handoff_image_id = BL33_IMAGE_ID,
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# endif
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},
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#endif /* AARCH64 */
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# ifdef QEMU_LOAD_BL32
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#ifdef AARCH64
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#define BL32_EP_ATTRIBS (SECURE | EXECUTABLE)
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#define BL32_IMG_ATTRIBS 0
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#else
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#define BL32_EP_ATTRIBS (SECURE | EXECUTABLE | EP_FIRST_EXE)
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#define BL32_IMG_ATTRIBS IMAGE_ATTRIB_PLAT_SETUP
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#endif
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/* Fill BL32 related information */
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{ .image_id = BL32_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t, BL32_EP_ATTRIBS),
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.ep_info.pc = BL32_BASE,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
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image_info_t, BL32_IMG_ATTRIBS),
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.image_info.image_base = BL32_BASE,
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.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
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.next_handoff_image_id = BL33_IMAGE_ID,
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},
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/*
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* Fill BL32 external 1 related information.
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* A typical use for extra1 image is with OP-TEE where it is the
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* pager image.
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*/
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{ .image_id = BL32_EXTRA1_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t, SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
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image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
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.image_info.image_base = BL32_BASE,
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.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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/*
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* Fill BL32 external 2 related information.
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* A typical use for extra2 image is with OP-TEE where it is the
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* paged image.
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*/
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{ .image_id = BL32_EXTRA2_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t, SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
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image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
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#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE)
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.image_info.image_base = QEMU_OPTEE_PAGEABLE_LOAD_BASE,
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.image_info.image_max_size = QEMU_OPTEE_PAGEABLE_LOAD_SIZE,
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#endif
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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# endif /* QEMU_LOAD_BL32 */
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/* Fill BL33 related information */
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{ .image_id = BL33_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t, NON_SECURE | EXECUTABLE),
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# ifdef PRELOADED_BL33_BASE
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.ep_info.pc = PRELOADED_BL33_BASE,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
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IMAGE_ATTRIB_SKIP_LOADING),
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# else /* PRELOADED_BL33_BASE */
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.ep_info.pc = NS_IMAGE_OFFSET,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
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0),
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.image_info.image_base = NS_IMAGE_OFFSET,
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.image_info.image_max_size = NS_DRAM0_BASE + NS_DRAM0_SIZE -
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NS_IMAGE_OFFSET,
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# endif /* !PRELOADED_BL33_BASE */
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.next_handoff_image_id = INVALID_IMAGE_ID,
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}
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#endif /* !EL3_PAYLOAD_BASE */
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};
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REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
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