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eff2f44430
The CSS_SYSTEM_PWR_DMN_LVL macro that defines the system power domain level is fixed at ARM_PWR_LVL2 for all CSS platforms. However, the system power domain level can be different for CSS platforms that use multi-threaded CPUs. So, in preparation towards adding support for platforms that use multi-threaded CPUs, refactor the definition of CSS_SYSTEM_PWR_DMN_LVL such that CSS_SYSTEM_PWR_DMN_LVL is uniquely defined for each of the CSS platform. Change-Id: Ia837b13f6865e71da01780993c048b45b7f36d85 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
45 lines
1.4 KiB
C
45 lines
1.4 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CSS_PM_H
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#define CSS_PM_H
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#include <cdefs.h>
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#include <psci.h>
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#include <stdint.h>
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/* Macros to read the CSS power domain state */
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#define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0]
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#define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1]
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static inline unsigned int css_system_pwr_state(const psci_power_state_t *state)
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{
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#if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL)
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return state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL];
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#else
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return 0;
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#endif
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}
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int css_pwr_domain_on(u_register_t mpidr);
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void css_pwr_domain_on_finish(const psci_power_state_t *target_state);
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void css_pwr_domain_off(const psci_power_state_t *target_state);
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void css_pwr_domain_suspend(const psci_power_state_t *target_state);
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void css_pwr_domain_suspend_finish(
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const psci_power_state_t *target_state);
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void __dead2 css_system_off(void);
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void __dead2 css_system_reset(void);
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void css_cpu_standby(plat_local_state_t cpu_state);
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void css_get_sys_suspend_power_state(psci_power_state_t *req_state);
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int css_node_hw_state(u_register_t mpidr, unsigned int power_level);
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/*
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* This mapping array has to be exported by the platform. Each element at
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* a given index maps that core to an SCMI power domain.
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*/
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extern const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[];
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#endif /* CSS_PM_H */
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