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https://github.com/ARM-software/arm-trusted-firmware.git
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564e073cd5
Revise the AST2700 boot flow to the RESET_TO_BL31 scheme. The execution of BL1/2 can be saved from ARM CA35 while most low level platform initialization are moved to a preceding MCU. This patch updates the build configuration and also adds the SMP mailbox setup code to hold secondary cores until they are being waken up. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Change-Id: I7e0aa6416b92b97036153db1d9a26baaa41b7b18
34 lines
732 B
Makefile
34 lines
732 B
Makefile
#
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# Copyright (c) 2023, Aspeed Technology Inc.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include drivers/arm/gic/v3/gicv3.mk
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include lib/xlat_tables_v2/xlat_tables.mk
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PLAT_AST2700 := plat/aspeed/ast2700
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PLAT_INCLUDES := \
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-I${PLAT_AST2700}/include
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BL31_SOURCES += \
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common/desc_image_load.c \
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lib/cpus/aarch64/cortex_a35.S \
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plat/common/plat_gicv3.c \
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plat/common/plat_psci_common.c \
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drivers/ti/uart/aarch64/16550_console.S \
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${PLAT_AST2700}/plat_helpers.S \
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${PLAT_AST2700}/plat_topology.c \
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${PLAT_AST2700}/plat_bl31_setup.c \
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${PLAT_AST2700}/plat_pm.c \
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${GICV3_SOURCES} \
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${XLAT_TABLES_LIB_SRCS}
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RESET_TO_BL31 := 1
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PROGRAMMABLE_RESET_ADDRESS := 1
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COLD_BOOT_SINGLE_CPU := 0
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ENABLE_SVE_FOR_NS := 0
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