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d38c64d246
Most newer CPU's have DSU and CPU power control core-off bit which means before turning off CPUs from base power controller we need to turn individual cores off from CPU Power control. However there are certain older CPU's that don't have DSU and don't support CPUPWRCTRL_EL1, so populate them as a list and ignore setting core-off bit for those older CPU's as all newer CPU's have them. Note: unfortunately there is no mechanism to identify if a DSU is present and CPUPWRCTRL_EL1 is supported through any CPU control registers and CPUPWRCTRL_EL1 is supported only for ARM64 platforms and not available in ARM32 platforms. Change-Id: Iba6c3c8db60dbeb177cead7ebc65df8265860da7 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
45 lines
974 B
C
45 lines
974 B
C
/*
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* Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#if __aarch64__
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#include <aem_generic.h>
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#include <arch_helpers.h>
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#include <cortex_a35.h>
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#include <cortex_a53.h>
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#include <cortex_a57.h>
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#include <cortex_a72.h>
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#include <cortex_a73.h>
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#include <cortex_a78_ae.h>
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#include <drivers/arm/fvp/fvp_cpu_pwr.h>
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#include <lib/utils_def.h>
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#include <neoverse_e1.h>
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bool check_cpupwrctrl_el1_is_available(void)
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{
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/* Poupulate list of CPU midr that doesn't support CPUPWRCTL_EL1 */
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const unsigned int midr_no_cpupwrctl[] = {
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BASE_AEM_MIDR,
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CORTEX_A35_MIDR,
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CORTEX_A53_MIDR,
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CORTEX_A57_MIDR,
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CORTEX_A72_MIDR,
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CORTEX_A73_MIDR,
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CORTEX_A78_AE_MIDR,
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NEOVERSE_E1_MIDR
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};
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unsigned int midr = (unsigned int)read_midr();
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for (unsigned int i = 0U; i < ARRAY_SIZE(midr_no_cpupwrctl); i++) {
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if (midr_no_cpupwrctl[i] == midr) {
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return false;
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}
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}
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return true;
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}
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#endif /* __arch64__ */
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