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ca661a0092
This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
112 lines
4.3 KiB
C
112 lines
4.3 KiB
C
/*
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* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_SYSTEMMANAGER_H
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#define SOCFPGA_SYSTEMMANAGER_H
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#include "socfpga_plat_def.h"
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/* System Manager Register Map */
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#define SOCFPGA_SYSMGR_SDMMC 0x28
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#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0
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#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4
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#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8
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#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xcc
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#define SOCFPGA_SYSMGR_NOC_IDLEACK 0xd0
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#define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xd4
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208
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/* Field Masking */
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#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0)
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#define IDLE_DATA_LWSOC2FPGA BIT(0)
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#define IDLE_DATA_SOC2FPGA BIT(4)
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#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
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#define SCR_AXI_AP_MASK BIT(24)
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#define SCR_FPGA2SOC_MASK BIT(16)
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#define SCR_MPU_MASK BIT(0)
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#define DISABLE_L4_FIREWALL (SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \
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| SCR_MPU_MASK)
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#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
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/* Macros */
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#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
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+ (SOCFPGA_SYSMGR_##_reg))
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#define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \
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+ (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg))
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#define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \
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+ (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg))
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/* L3 Interconnect Register Map */
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#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000
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#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004
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#define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028
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#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030
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#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040
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#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044
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#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068
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#define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094
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#define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
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#define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
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void enable_ns_peripheral_access(void);
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void enable_ns_bridge_access(void);
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#endif /* SOCFPGA_SYSTEMMANAGER_H */
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