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https://github.com/ARM-software/arm-trusted-firmware.git
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391eeeef7f
Refactor reset manager into intel common platform directory as it can be shared by both Stratix 10 and Agilex. Register address and field is now referred through macros. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a
108 lines
3.6 KiB
C
108 lines
3.6 KiB
C
/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_RESETMANAGER_H
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#define SOCFPGA_RESETMANAGER_H
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#include "socfpga_plat_def.h"
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/* Register Mapping */
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#define SOCFPGA_RSTMGR_STAT 0x000
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#define SOCFPGA_RSTMGR_HDSKEN 0x010
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#define SOCFPGA_RSTMGR_MPUMODRST 0x020
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#define SOCFPGA_RSTMGR_PER0MODRST 0x024
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#define SOCFPGA_RSTMGR_PER1MODRST 0x028
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#define SOCFPGA_RSTMGR_BRGMODRST 0x02c
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#define SOCFPGA_RSTMGR_COLDMODRST 0x034
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#define SOCFPGA_RSTMGR_HDSKTIMEOUT 0x064
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/* Field Mapping */
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#define RSTMGR_PER0MODRST_EMAC0 0x00000001
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#define RSTMGR_PER0MODRST_EMAC1 0x00000002
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#define RSTMGR_PER0MODRST_EMAC2 0x00000004
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#define RSTMGR_PER0MODRST_USB0 0x00000008
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#define RSTMGR_PER0MODRST_USB1 0x00000010
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#define RSTMGR_PER0MODRST_NAND 0x00000020
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#define RSTMGR_PER0MODRST_SDMMC 0x00000080
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#define RSTMGR_PER0MODRST_EMAC0OCP 0x00000100
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#define RSTMGR_PER0MODRST_EMAC1OCP 0x00000200
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#define RSTMGR_PER0MODRST_EMAC2OCP 0x00000400
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#define RSTMGR_PER0MODRST_USB0OCP 0x00000800
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#define RSTMGR_PER0MODRST_USB1OCP 0x00001000
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#define RSTMGR_PER0MODRST_NANDOCP 0x00002000
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#define RSTMGR_PER0MODRST_SDMMCOCP 0x00008000
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#define RSTMGR_PER0MODRST_DMA 0x00010000
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#define RSTMGR_PER0MODRST_SPIM0 0x00020000
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#define RSTMGR_PER0MODRST_SPIM1 0x00040000
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#define RSTMGR_PER0MODRST_SPIS0 0x00080000
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#define RSTMGR_PER0MODRST_SPIS1 0x00100000
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#define RSTMGR_PER0MODRST_DMAOCP 0x00200000
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#define RSTMGR_PER0MODRST_EMACPTP 0x00400000
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#define RSTMGR_PER0MODRST_DMAIF0 0x01000000
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#define RSTMGR_PER0MODRST_DMAIF1 0x02000000
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#define RSTMGR_PER0MODRST_DMAIF2 0x04000000
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#define RSTMGR_PER0MODRST_DMAIF3 0x08000000
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#define RSTMGR_PER0MODRST_DMAIF4 0x10000000
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#define RSTMGR_PER0MODRST_DMAIF5 0x20000000
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#define RSTMGR_PER0MODRST_DMAIF6 0x40000000
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#define RSTMGR_PER0MODRST_DMAIF7 0x80000000
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#define RSTMGR_PER1MODRST_WATCHDOG0 0x00000001
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#define RSTMGR_PER1MODRST_WATCHDOG1 0x00000002
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#define RSTMGR_PER1MODRST_WATCHDOG2 0x00000004
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#define RSTMGR_PER1MODRST_WATCHDOG3 0x00000008
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#define RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010
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#define RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020
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#define RSTMGR_PER1MODRST_SPTIMER0 0x00000040
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#define RSTMGR_PER1MODRST_SPTIMER1 0x00000080
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#define RSTMGR_PER1MODRST_I2C0 0x00000100
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#define RSTMGR_PER1MODRST_I2C1 0x00000200
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#define RSTMGR_PER1MODRST_I2C2 0x00000400
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#define RSTMGR_PER1MODRST_I2C3 0x00000800
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#define RSTMGR_PER1MODRST_I2C4 0x00001000
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#define RSTMGR_PER1MODRST_UART0 0x00010000
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#define RSTMGR_PER1MODRST_UART1 0x00020000
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#define RSTMGR_PER1MODRST_GPIO0 0x01000000
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#define RSTMGR_PER1MODRST_GPIO1 0x02000000
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#define RSTMGR_HDSKEN_FPGAHSEN 0x00000004
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#define RSTMGR_HDSKEN_ETRSTALLEN 0x00000008
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#define RSTMGR_HDSKEN_L2FLUSHEN 0x00000100
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#define RSTMGR_HDSKEN_L3NOC_DBG 0x00010000
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#define RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000
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#define RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001
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#define RSTMGR_BRGMODRST_SOC2FPGA 0x1
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#define RSTMGR_BRGMODRST_LWHPS2FPGA 0x2
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#define RSTMGR_BRGMODRST_FPGA2SOC 0x4
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#define RSTMGR_BRGMODRST_F2SSDRAM1 0x10
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#define RSTMGR_BRGMODRST_F2SSDRAM2 0x20
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#define RSTMGR_BRGMODRST_MPFE 0x40
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#define RSTMGR_BRGMODRST_DDRSCH 0x40
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/* Definitions */
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#define RSTMGR_L2_MODRST 0x0100
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#define RSTMGR_HDSKEN_SET 0x010D
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/* Macros */
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#define SOCFPGA_RSTMGR(_reg) (SOCFPGA_RSTMGR_REG_BASE \
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+ (SOCFPGA_RSTMGR_##_reg))
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#define RSTMGR_FIELD(_reg, _field) (RSTMGR_##_reg##MODRST_##_field)
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/* Function Declarations */
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void deassert_peripheral_reset(void);
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void config_hps_hs_before_warm_reset(void);
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int socfpga_bridges_enable(void);
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int socfpga_bridges_disable(void);
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#endif /* SOCFPGA_RESETMANAGER_H */
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