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https://github.com/ARM-software/arm-trusted-firmware.git
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a62b47b87a
Fix mailbox driver incompatible cast bug and control flow issue that was flagged by Coverity Scan. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3f34e98d24e40139d31cf7d5b9b973cd2d981065
146 lines
4.5 KiB
C
146 lines
4.5 KiB
C
/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_MBOX_H
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#define SOCFPGA_MBOX_H
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#include <lib/utils_def.h>
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#define MBOX_OFFSET 0xffa30000
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#define MBOX_MAX_JOB_ID 0xf
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#define MBOX_ATF_CLIENT_ID 0x1
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#define MBOX_JOB_ID 0x1
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/* Mailbox interrupt flags and masks */
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#define MBOX_INT_FLAG_COE 0x1
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#define MBOX_INT_FLAG_RIE 0x2
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#define MBOX_INT_FLAG_UAE 0x100
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#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3)
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#define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8)))
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/* Mailbox response and status */
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#define MBOX_RESP_BUFFER_SIZE 16
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#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff)
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#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12)
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#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28)
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#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24)
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#define MBOX_STATUS_UA_MASK (1<<8)
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/* Mailbox command and response */
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#define MBOX_CMD_FREE_OFFSET 0x14
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#define MBOX_CMD_BUFFER_SIZE 32
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#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28)
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#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24)
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#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12)
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#define MBOX_INDIRECT (1 << 11)
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#define MBOX_INSUFFICIENT_BUFFER -2
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#define MBOX_CIN 0x00
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#define MBOX_ROUT 0x04
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#define MBOX_URG 0x08
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#define MBOX_INT 0x0C
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#define MBOX_COUT 0x20
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#define MBOX_RIN 0x24
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#define MBOX_STATUS 0x2C
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#define MBOX_CMD_BUFFER 0x40
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#define MBOX_RESP_BUFFER 0xC0
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#define MBOX_RESP_BUFFER_SIZE 16
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#define MBOX_RESP_OK 0
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#define MBOX_RESP_INVALID_CMD 1
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#define MBOX_RESP_UNKNOWN_BR 2
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#define MBOX_RESP_UNKNOWN 3
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#define MBOX_RESP_NOT_CONFIGURED 256
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/* Mailbox SDM doorbell */
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#define MBOX_DOORBELL_TO_SDM 0x400
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#define MBOX_DOORBELL_FROM_SDM 0x480
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/* Mailbox QSPI commands */
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#define MBOX_CMD_RESTART 2
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#define MBOX_CMD_QSPI_OPEN 50
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#define MBOX_CMD_QSPI_CLOSE 51
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#define MBOX_CMD_QSPI_DIRECT 59
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#define MBOX_CMD_GET_IDCODE 16
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#define MBOX_CMD_QSPI_SET_CS 52
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/* Mailbox CANCEL command */
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#define MBOX_CMD_CANCEL 0x3
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/* Mailbox REBOOT commands */
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#define MBOX_CMD_REBOOT_HPS 71
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/* Mailbox RSU commands */
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#define MBOX_GET_SUBPARTITION_TABLE 90
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#define MBOX_RSU_STATUS 91
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#define MBOX_RSU_UPDATE 92
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/* Mailbox RSU macros */
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#define RSU_VERSION_ACMF BIT(8)
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#define RSU_VERSION_ACMF_MASK 0xff00
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/* HPS stage notify command */
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#define MBOX_HPS_STAGE_NOTIFY 93
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/* Execution states for HPS_STAGE_NOTIFY */
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#define HPS_EXECUTION_STATE_FSBL 0
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#define HPS_EXECUTION_STATE_SSBL 1
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#define HPS_EXECUTION_STATE_OS 2
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/* Mailbox reconfiguration commands */
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#define MBOX_CONFIG_STATUS 4
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#define MBOX_RECONFIG 6
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#define MBOX_RECONFIG_DATA 8
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#define MBOX_RECONFIG_STATUS 9
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/* Generic error handling */
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#define MBOX_TIMEOUT -2047
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#define MBOX_NO_RESPONSE -2
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#define MBOX_WRONG_ID -3
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/* Mailbox status */
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#define RECONFIG_STATUS_STATE 0
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#define RECONFIG_STATUS_PIN_STATUS 2
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#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
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#define PIN_STATUS_NSTATUS (U(1) << 31)
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#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3)
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#define SOFTFUNC_STATUS_INIT_DONE (1 << 1)
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#define SOFTFUNC_STATUS_CONF_DONE (1 << 0)
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#define MBOX_CFGSTAT_STATE_IDLE 0x00000000
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#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000
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#define MBOX_CFGSTAT_STATE_FAILACK 0x08000000
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#define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001
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#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002
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#define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003
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#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004
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#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005
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#define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006
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#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007
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#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008
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void mailbox_set_int(int interrupt_input);
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int mailbox_init(void);
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void mailbox_set_qspi_close(void);
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void mailbox_set_qspi_open(void);
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void mailbox_set_qspi_direct(void);
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int mailbox_send_cmd(int job_id, unsigned int cmd, uint64_t *args,
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int len, int urgent, uint32_t *response, int resp_len);
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int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint64_t *args,
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int len, int urgent);
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int mailbox_read_response(int job_id, uint32_t *response, int resp_len);
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int mailbox_get_qspi_clock(void);
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void mailbox_reset_cold(void);
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void mailbox_clear_response(void);
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int intel_mailbox_get_config_status(uint32_t cmd);
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int intel_mailbox_is_fpga_not_ready(void);
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int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len);
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int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len);
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int mailbox_rsu_update(uint64_t *flash_offset);
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int mailbox_hps_stage_notify(uint64_t execution_stage);
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#endif /* SOCFPGA_MBOX_H */
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