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cedfa04ba5
ARMv8.4-TTST (Small Translation tables) relaxes the lower limit on the size of translation tables by increasing the maximum permitted value of the T1SZ and T0SZ fields in TCR_EL1, TCR_EL2, TCR_EL3, VTCR_EL2 and VSTCR_EL2. This feature is supported in AArch64 state only. This patch adds support for this feature to both versions of the translation tables library. It also removes the static build time checks for virtual address space size checks to runtime assertions. Change-Id: I4e8cebc197ec1c2092dc7d307486616786e6c093 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
141 lines
3.5 KiB
C
141 lines
3.5 KiB
C
/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <lib/utils.h>
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#include <lib/xlat_tables/xlat_tables_arch.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include "../xlat_tables_private.h"
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#if (ARM_ARCH_MAJOR == 7) && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)
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#error ARMv7 target does not support LPAE MMU descriptors
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#endif
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#define XLAT_TABLE_LEVEL_BASE \
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GET_XLAT_TABLE_LEVEL_BASE(PLAT_VIRT_ADDR_SPACE_SIZE)
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#define NUM_BASE_LEVEL_ENTRIES \
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GET_NUM_BASE_LEVEL_ENTRIES(PLAT_VIRT_ADDR_SPACE_SIZE)
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static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES]
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__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
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#if ENABLE_ASSERTIONS
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static unsigned long long get_max_supported_pa(void)
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{
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/* Physical address space size for long descriptor format. */
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return (1ULL << 40) - 1ULL;
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}
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#endif /* ENABLE_ASSERTIONS */
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unsigned int xlat_arch_current_el(void)
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{
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/*
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* If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, System,
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* SVC, Abort, UND, IRQ and FIQ modes) execute at EL3.
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*/
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return 3U;
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}
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uint64_t xlat_arch_get_xn_desc(unsigned int el __unused)
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{
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return UPPER_ATTRS(XN);
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}
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void init_xlat_tables(void)
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{
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unsigned long long max_pa;
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uintptr_t max_va;
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assert(PLAT_VIRT_ADDR_SPACE_SIZE >= MIN_VIRT_ADDR_SPACE_SIZE);
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assert(PLAT_VIRT_ADDR_SPACE_SIZE <= MAX_VIRT_ADDR_SPACE_SIZE);
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assert(IS_POWER_OF_TWO(PLAT_VIRT_ADDR_SPACE_SIZE));
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print_mmap();
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init_xlation_table(0U, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
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&max_va, &max_pa);
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assert(max_va <= (PLAT_VIRT_ADDR_SPACE_SIZE - 1U));
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assert(max_pa <= (PLAT_PHY_ADDR_SPACE_SIZE - 1U));
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assert((PLAT_PHY_ADDR_SPACE_SIZE - 1U) <= get_max_supported_pa());
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}
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void enable_mmu_svc_mon(unsigned int flags)
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{
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unsigned int mair0, ttbcr, sctlr;
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uint64_t ttbr0;
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assert(IS_IN_SECURE());
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assert((read_sctlr() & SCTLR_M_BIT) == 0U);
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/* Set attributes in the right indices of the MAIR */
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mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
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mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
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ATTR_IWBWA_OWBWA_NTR_INDEX);
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mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE,
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ATTR_NON_CACHEABLE_INDEX);
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write_mair0(mair0);
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/* Invalidate TLBs at the current exception level */
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tlbiall();
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/*
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* Set TTBCR bits as well. Set TTBR0 table properties. Disable TTBR1.
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*/
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int t0sz = 32 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE);
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if ((flags & XLAT_TABLE_NC) != 0U) {
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/* Inner & outer non-cacheable non-shareable. */
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ttbcr = TTBCR_EAE_BIT |
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TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC |
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TTBCR_RGN0_INNER_NC | (uint32_t) t0sz;
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} else {
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/* Inner & outer WBWA & shareable. */
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ttbcr = TTBCR_EAE_BIT |
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TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
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TTBCR_RGN0_INNER_WBA | (uint32_t) t0sz;
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}
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ttbcr |= TTBCR_EPD1_BIT;
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write_ttbcr(ttbcr);
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/* Set TTBR0 bits as well */
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ttbr0 = (uintptr_t) base_xlation_table;
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write64_ttbr0(ttbr0);
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write64_ttbr1(0U);
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/*
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* Ensure all translation table writes have drained
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* into memory, the TLB invalidation is complete,
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* and translation register writes are committed
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* before enabling the MMU
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*/
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dsbish();
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isb();
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sctlr = read_sctlr();
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT;
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if ((flags & DISABLE_DCACHE) != 0U)
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sctlr &= ~SCTLR_C_BIT;
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else
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sctlr |= SCTLR_C_BIT;
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write_sctlr(sctlr);
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/* Ensure the MMU enable takes effect immediately */
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isb();
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}
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void enable_mmu_direct_svc_mon(unsigned int flags)
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{
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enable_mmu_svc_mon(flags);
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}
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